JPH10214969A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the on-resistance of an insulated-gate transistor. SOLUTION: An insulated-gate semiconductor device is a three-dimensional device making use of an SOI structure, it adopts a double gate (G1, G2) structure, and a trench gate 230 and trench drains 220a, 220b which are faced with the trench gate are arranged. A low-resistance carrier accumulation layer which is formed around a gate electrode is formed such that it is continued to a channel region (inversion channel) and that it is in a shape extended to the vertical direction of a substrate. In addition, the entirely of a lightly doped drain region 200 which is sandwiched between the trench gate and the trench drains functions as the route of the uniform movement of carriers, and the cross-sectional area of a current route is increased. Thereby, an on-resistance can be reduced dramatically.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an insulated gate semiconductor device, and more particularly to a lateral power MOSFET used for electric power applications.

[0002]

2. Description of the Related Art The structure of a conventional lateral power MOSFET is described as follows.
As shown in FIG.

In FIG. 38, reference numeral 2000 denotes a p-type substrate, reference numeral 2100 denotes an n ⁻ -type epitaxial layer, reference numeral 2200 denotes a p ⁻ -type well region, and reference numeral 2300 denotes an n ⁺ -type source region. And reference number 24
00 indicates an n ⁺ type drain region, reference numeral 2500 indicates a gate electrode, reference numeral 2600 indicates a gate insulating film, reference numeral 2700 indicates an insulating film, and reference numeral 28
Reference numerals 00 and 2900 denote metal electrodes, respectively.

[0004]

In the structure of FIG. 38, in order to obtain a sufficient source / drain withstand voltage, a high impurity concentration drain region 240 is formed from the end of the gate electrode 2500.
A lightly doped drain region 2100 with a sufficient distance to zero
is necessary. Therefore, the area occupied by the device must be increased.

[0005] The on-resistance of the device is mainly determined by the resistance of the low-concentration drain region 2100. Therefore, in the structure of FIG. 38, it is difficult to reduce the on-resistance per unit area (hereinafter, referred to as normalized on-resistance).

Further, in order to obtain a sufficient withstand voltage, a sufficiently low concentration of the p-well region 2200 is required, so that there is a limit to the reduction of the channel distance. This also
This is a factor that hinders a reduction in the occupied area of the device and a factor that makes it difficult to lower the normalized on-resistance.

One of the objects of the present invention is to reduce the occupied area of an insulated gate semiconductor device and reduce the channel distance while securing a low-concentration drain region at a sufficient distance to obtain a desired breakdown voltage. By doing so, it is possible to further reduce the occupied area of the device and reduce the standardized on-resistance.

[0008]

[Means for Solving the Problems]

(1) In the insulated gate semiconductor device according to the first aspect of the present invention, a carrier accumulation layer forming function provided from a channel region to a low concentration drain region functioning as an electric field relaxation region is provided. With a trench gate
And a trench drain provided so as to face the trench gate.

The meaning of the "trench" in the present invention means "having a portion extending in a direction perpendicular to the substrate". In addition to forming a groove perpendicular to the substrate, a semiconductor material is deposited on the substrate. To form a vertical portion (in the case of a stack structure).

According to the present invention, carriers (electrons in the case of an n-type transistor) passing through the channel form a substantially uniform path to the opposing drain via the extremely low-resistance carrier accumulation layer. Moving.

Therefore, an increase in the on-resistance of the transistor is suppressed by passing through the low-resistance carrier accumulation layer.

Furthermore, since the entire low-concentration drain region sandwiched between the opposed trench gate and trench drain functions as a carrier path, the cross-sectional area of the current path is greatly increased, and the resistance due to the low-concentration drain region is reduced. It is possible to greatly reduce.

A second gate electrode is provided below or on the side of the channel region so as to face the first gate electrode, and a low-concentration drain region functioning as an electric field relaxation region is formed below the second gate electrode. In this case, the effect of reducing the channel resistance due to the provision of the two gates and the effect of reducing the element size by arranging the channel region and the low-concentration drain region vertically can be further obtained.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

(1) First Embodiment (Device Structure) FIG. 1 shows a cross-sectional structure of an insulated gate semiconductor device according to a first embodiment of the present invention.

The device shown in FIG. 1 is a lateral n-type power MOSFET employing an SOI structure.

That is, an insulating film 102 is formed on the surface of an n ⁻ -type single crystal substrate 100 (part of which functions as a low impurity concentration drain region), and a first gate made of polysilicon is formed on the insulating film 102. Electrodes 108a, 108b
(Bottom gate G1).

Channel regions (low-concentration p regions) 112a and 112b are formed on the first gate electrodes 108a and 108b via first gate oxide films 115a and 115b. On the channel regions 112a and 112b,
A second gate electrode 118 (top gate G2) made of polysilicon is formed via a second gate oxide film 116b.

Further, n ⁺ -type source regions 110a and 110b are provided in contact with the channel regions 112a and 112b, and a source electrode (S) 124 is connected to each region.

An n ⁻ type region (region forming part of a low concentration drain region) 114 is provided between channel regions 112 a and 112 b and n ⁻ type single crystal substrate 100.

Further, drain electrodes (D) 122a and 122b are formed so as to sandwich the source electrode (S) 124, and the drain electrodes 122a and 122b are connected to n ⁺ type drain regions 106a and 106b. . Reference numerals 116a and 116c are oxide films formed in the same step as the oxide films (gate oxide films 116b) covering the surfaces of the n ⁺ -type drain regions 106a and 106b, respectively.

When the transistor is turned on, electrons are emitted as shown in FIG.
In the middle, it moves from the source to the drain along the path indicated by the arrow (I _E ).

(Characteristics of the structure of the device of FIG. 1) The characteristic of the device of FIG. 1 is that a low-concentration drain region (part of the semiconductor substrate 100) functioning as an electric field relaxation region is located below the bottom gate electrodes 108a and 108b. (A three-dimensional structure) and the top gate 118 and the bottom gate 108 above and below the channel regions 112a and 112b.
a, 108b (double gate structure).

As described above, in order to obtain a sufficient source / drain breakdown voltage, it is necessary to provide a male low-concentration drain region with a sufficient distance from the end of the gate electrode to the high-concentration drain region. The drain region was arranged in a plane as shown in FIG. For this reason, the device area must be increased, and it is difficult to reduce the normalized on-resistance.

On the other hand, in the device of the present invention shown in FIG. 1, the n ⁻ type single crystal substrate 10 functioning as an electric field relaxation region is provided.
A single crystal silicon region is formed on the insulating film through an insulating film, and a channel region and a source region are formed in the single crystal silicon region on the insulating film. That is, SOI (S
The channel region and the low-concentration drain region have a three-dimensional structure employing an icon-on-insulator (i.e., insulator on insulator) structure. Therefore, it is not necessary to allocate a device area only for the low concentration drain region,
The occupied area of the device can be reduced.

In the conventional device structure shown in FIG.
Insulation between source / drain is low concentration p region (2200)
And the low-concentration n region (2100) is maintained at a junction (pn junction), and a sufficient low-concentration p-region depth is required to ensure a sufficient dielectric strength. Therefore, it has been difficult to reduce the channel distance to the depth of the low concentration p region or less.

On the other hand, since the present invention employs the SOI structure, the insulating film 102 covering the substrate surface functions to realize a desired breakdown voltage. Therefore, the depth of the channel region (low-concentration p region) is different from the conventional example of FIG.
It has nothing to do with the withstand voltage. That is, the channel region (low-concentration p region) only needs to have the function of the channel, and does not require any function related to insulation between the source and the drain as required in the conventional structure. Therefore, the channel distance can be shortened, and the device area can be reduced. Therefore, the occupied area of the device can be reduced.

Further, by adopting the double gate structure, the channel cross-sectional area in the channel regions 112a and 112b increases, and the channel resistance decreases. It is easy to further reduce the channel resistance as a fully depleted channel.

In FIG. 1, two gates G1,
G2 is driven in principle at the same time, but is not necessarily limited to this, and a driving method of driving one of them may be adopted.

As described above, the double gate reduces the channel resistance and reduces the occupied area of the device.
The normalized on-resistance can be significantly reduced.

(Method of Manufacturing Device of FIG. 1) FIGS. 2 to 7
A method for manufacturing the device of FIG. 1 will be described with reference to FIG.

[0032] Step 1 as shown in FIG. 2, n ^- -type semiconductor single crystal to form an oxide film 102 on the surface of the substrate 100, followed by forming a polysilicon processed polysilicon layer serving as the bottom gate electrode 1
08a and 108b are formed, and the polysilicon layer 108 is formed.
a, an oxide film (gate insulating film) 115 on the surface of 108b
a, 115b are formed.

Step 2 As shown in FIG. 3, openings 130a, 130b and 130c are provided by selectively removing the surface oxide film 102. The surface of the semiconductor substrate 100 exposed in this opening is formed by solid phase epitaxial growth (Solid) in the next step.
A seed crystal part (seed part) for Phase Epitaxy (hereinafter, referred to as SPE).

Step 3 As shown in FIG. 4, a single crystal layer 140 is formed on the surface insulating film 102 and the polysilicon layers 108a and 108b by using the SPE method.

Here, the SPE method will be described with reference to FIG.

That is, as shown in FIG. 37A, an SiO ₂ film 1100 is formed on a silicon single crystal substrate 1000, and the seed crystal portions 1200a, 1200a are formed as shown in FIG.
200b is formed.

Thereafter, the natural oxide film is removed by immersing the silicon substrate in a dilute HF solution for several seconds, and at the same time, the surface of the silicon substrate is terminated with hydrogen and inactivated to regrow the natural oxide film. Deter.

Subsequently, as shown in FIG. 37C, an amorphous silicon film 1210 is formed.

Next, heat treatment is performed at 600 ° C. for several tens of minutes to cause solid phase epitaxial growth (SPE) starting from the seed portion (seed crystal portion). The SPE also occurs in the horizontal direction via the SPE in the vertical direction.
Amorphous silicon layer 1210 (c) is changed to a single crystal layer, as shown in FIG. 37 (d), SiO ₂ film 110
0, a silicon single crystal layer 1300 is formed.

The conductivity type of the silicon single crystal layer 1300 can be controlled by using doped amorphous silicon in the step of depositing amorphous silicon. But you can control it.

The above is the outline of the formation of the SOI structure by the SPE method.

The single crystal layer 140 shown in FIG. 4 is a layer formed by using the above-mentioned SPE method. In the present embodiment, after forming an intrinsic single crystal, n ^{− is} implanted by ion implantation.
Type.

Step 4 Next, as shown in FIG. 5, after patterning the single crystal layer obtained by SPE, the surface thereof is oxidized to form oxide films 116a, 116b and 116c.

Step 5 Next, as shown in FIG. 6, a polysilicon layer 118 serving as a top gate electrode is formed. Subsequently, impurities are introduced using the polysilicon layer 118 as a mask and double diffusion is performed. P ^- channel regions 112a and 112b and source regions (n ⁺ ) 110a and 110b (and high-concentration drain regions 106a and 106b) are formed.

That is, first, boron (B) is ion-implanted over the entire surface using the polysilicon layer 118 as a mask.
By performing the heat treatment, boron is diffused inward from the end of the polysilicon layer 118 by a predetermined distance to form ap ⁻ type region.

Subsequently, arsenic (As) is implanted into the entire surface at a high concentration, and the p ^- type layer is changed to n ⁺ -type by the preceding boron implantation. Then, heat treatment is performed only for damage recovery. Thus, the p ^- channel region 1
12a, 112b and source region (n ⁺ ) 110
a, 110b (and the high concentration drain regions 106a, 1
06b) is formed.

Step 6 Next, as shown in FIG. 7, a protective film 120 such as a CVD SiO ₂ film is formed, and a contact hole for electrode connection is formed. Thereafter, by forming electrodes, the device of FIG. 1 is completed.

(2) Second Embodiment (Device Structure) FIG. 8 shows a cross-sectional structure of a power MOSFET according to this embodiment. In FIG. 8, FIG.
The same reference numerals are given to parts equivalent to.

The basic structure and operation of this device are the same as those of the device of FIG. 1, but the cross-sectional shape of the bottom gate electrode is different.

In other words, in the present embodiment, the bottom gate electrode 16 is extended to the region A surrounded by the alternate long and short dash line in FIG.
0a and 160b extend. That is, the bottom gate electrodes 160a and 160b have an inverted L-shaped cross section.

As a result, the channel regions 112a and 112a
In the n ⁻ -type region (part of the low concentration drain region) 114 on the side of 2b, the bottom gate electrodes 160a and 160
A carrier accumulation layer is formed around Ob, and the resistance of this portion is reduced as compared with the case of FIG. Therefore, it is possible to further reduce the on-resistance.

(Method of Manufacturing Device) Next, FIGS.
6, a method of manufacturing the device of FIG. 8 will be described.

Step 1 First, as shown in FIG. 9, an oxide film 102 is formed on a substrate 100.
Is formed, an opening is selectively formed, and the substrate surface exposed at the opening is oxidized again to form a thin oxide film 150.

Step 2 Next, as shown in FIG. 10, the openings SA1 and S
A2 and SA3 are formed. The surface of the substrate exposed at the opening functions later as a seed crystal part (seed part) in the SPE.

Step 3 Next, as shown in FIG.
Is deposited.

Step 4 Next, as shown in FIG. 12, the mask layers 172a, 172
b, RIE (reactive ion etching) is performed on the entire surface, and the mask layer 1 of the polysilicon layer 170 is formed.
All parts other than immediately below 72a and 172b are removed.

Step 5 Next, as shown in FIG. 13, the mask layers 172a, 172
After removing b, a single crystal layer 140 is formed by using the SPE method.

Step 6 Next, as shown in FIG. 14, after processing the single crystal layer 140,
The surface is oxidized to form oxide films 116a, 116b, 16c.
To form

Step 7 Next, as shown in FIG. 15, a polysilicon layer 118 is formed, impurities are introduced using the polysilicon layer 118 as a mask, and channel regions 112a, 1 are formed by double diffusion.
12b and n ⁺ type source regions 110a and 110b (and n ⁺ type drain regions 106a and 106b) are formed.

Step 8 Next, as shown in FIG. 16, an insulating film 120 such as a CVD SiO ₂ film is formed, and a contact hole for connecting an electrode is formed. Thereafter, electrodes are formed, and the device of FIG. 8 is completed.

(3) Third Embodiment (Structure of Device) FIG. 17 shows a cross-sectional structure of a power MOSFET according to a third embodiment of the present invention.

The feature of the device of FIG. 17 is that the second gate electrode (top gate electrode G2) has a structure having a horizontal portion 240 and a vertical portion (trench gate) 230, while the drain electrodes 220a and 220b also have a trench structure. That is, the trench gate 230 is opposed (surface opposed) with a predetermined area.

Hereinafter, the sectional structure will be described.

An insulating film 20 is formed on the surface of an n ⁻ -type single crystal substrate 200 (part of which functions as a low impurity concentration drain region).
2 are formed, and first gate electrodes 203a and 203b (bottom gate G1) made of polysilicon are formed on the insulating film 202. First gate electrode 20
The first gate oxide films 233a, 233a,
Channel region (low-concentration p region) 208 via 233b
a, 208b are formed. Channel region 208
a, 208b, a horizontal portion 240 of a second gate electrode (top gate G2) made of polysilicon via a second gate oxide film 231 (continuous with the oxide film 232 of the trench gate 230). Is formed. The upper end of trench gate 230 is connected to the lower surface of the central portion of horizontal portion 240, whereby top gate G1 has a T-shaped cross section.

Further, n ⁺ -type source regions 206a and 206b are provided in contact with channel regions 208a and 208b, and a source electrode (S) 250 is connected to each region.

Further, between the channel regions 208a, 208b and the n ⁻ -type single crystal substrate 200, n ⁻ -type regions (regions forming a part of the low concentration drain region) 210a, 210b are provided.

Further, drain electrodes (D) 260a and 260b are formed so as to sandwich the source electrode (S) 250, and the drain electrodes 260a and 260b are connected to the trench drains 220a and 220b. The trench drains 220a and 220b are connected to the trench gate 23.
0 with a predetermined area.

When the transistor is turned on, electrons are emitted as shown in FIG.
In the middle, it moves from the source to the drain along the path indicated by the arrow (I _E ).

(Characteristics of Device) The characteristics of the device of this embodiment will be described with reference to FIG. FIG. 18 shows FIG.
FIG. 4 is an enlarged view of a part of FIG.

[0070] Given a top gate G2 and the positive voltage at the same time the bottom gate G1 in the power MOSFET, the channel region 208b as shown in FIG. 18 (p ^-) in the channel CH1, CH2 is induced. A carrier accumulation layer (AC) is formed around the top gate G2. As shown, the carrier accumulation layer (AC) is formed so as to be continuous with the channel region (inversion channel) and extend in the vertical direction of the substrate.

Further, a vertical drain electrode (trench drain) 220b is provided opposite to the vertical portion (trench gate) 230 of the gate electrode with the low concentration drain region (electric field relaxation region) 200 interposed therebetween. The entire low-concentration drain region sandwiched therebetween functions as a path for uniform carrier movement. That is, as shown by the dotted line in FIG. 18, the area where the two electrodes face each other is the cross-sectional area (AS1) of the current path.

Therefore, the carriers (electrons in the case of an n-type transistor) passing through the channel whose resistance has been reduced by adopting the double gate structure are then passed through the extremely low resistance carrier accumulation layer to the opposite drain electrode. , Forming a uniform path and moving.

In this case, an increase in on-resistance is suppressed because the current passes through the low-resistance carrier accumulation layer.

Furthermore, a uniform carrier path (current path) is formed between the two electrodes facing each other with a plane, which means that the cross-sectional area of the current path has been greatly increased, and thus the low concentration The resistance due to the drain region can be extremely reduced. In other words, the demand for reducing the electric field by a sufficiently low-concentration drain region is contrary to the request for lowering the on-resistance by reducing the size of the low-concentration drain region. Is determined, the bulk resistance of the low-concentration drain region becomes the on-resistance as it is, which limits the on-resistance of the transistor.

However, according to the present invention, the gate electrode and the drain electrode are arranged in the vertical direction (the direction perpendicular to the main surface of the substrate), and the cross-sectional area of the current path is increased by the opposing area. The resistance of the concentration drain region is reduced. Therefore, it is possible to further reduce the on-resistance without sacrificing the electric field relaxation ability. Moreover, in the present structure, the electrodes are opposed to each other in a direction perpendicular to the main surface of the substrate, so that the planar size of the chip (the occupied area of the device) does not change and the chip size does not increase.

In this embodiment, the trench is formed by digging a groove in the substrate. However, the present invention is not limited to this. The structure is such that each electrode protrudes upward. (Stacked electrode).

Although the present embodiment employs a double gate structure, a single gate structure may be used.
The effect of reducing the normalized on-resistance is sufficiently obtained.

(Simulation and Experimental Results, etc.) FIG. 19 is a diagram simulating the current path of the device (FIG. 8) according to the second embodiment, and FIG. 20 is a diagram simulating the current path of the present embodiment. It is.

In the case of the device according to the second embodiment, it can be seen that the portion near the surface of the low-concentration drain region (n ⁻ ) is an effective current path. On the other hand, in the device of the present embodiment, the current flows almost uniformly through the low-concentration drain region (n ⁻ ) sandwiched between the trench gate and the trench drain, and is effectively used as a current path to a deep position in the low-concentration drain region. You can see that it is done.

FIG. 21 shows the relationship between the trench depth (length of the trench gate and the trench drain) and the normalized on-resistance (Ron) of the device according to the present embodiment. In the figure, a characteristic curve A shows characteristics when the gate voltage V _GS is 5 V, and a characteristic curve B shows characteristics when the gate voltage V _GS is 10 V.

FIG. 22 shows the relationship between the channel length (L) and the normalized on-resistance (Ron). The measurement conditions are
The trench depth is 5 μm, and the gate voltage V _GS is 10 V.

FIG. 23 shows drain voltage-drain current characteristics of a device according to the first embodiment (FIG. 1) and a device according to the third embodiment (FIG. 17), and a conventional example (FIG. 38). FIG. 3 is a diagram showing a comparison between drain voltage-drain current characteristics of FIG.

In FIG. 23, the characteristic curve A shows the drain voltage-drain current characteristic of the device according to the third embodiment (FIG. 17), and the characteristic curve B shows the device according to the first embodiment (FIG. 17). ) Shows the drain voltage-drain current characteristics, and the characteristic curve C shows the drain voltage-drain current characteristics of the conventional example (FIG. 38).

As is apparent, the device of the present invention can flow a much larger current at the same voltage as compared with the conventional example.

This means that the on-resistance of the device of the present invention is much lower than that of the conventional example.

FIG. 25 shows a comparison between each component of the on-resistance of the conventional vertical device and each component of the device of the present invention. FIG. 24 (a) shows the on-resistance component of the conventional device, and FIG. 24 (b) shows the on-resistance component of the device of the present invention shown in FIG. In the figure, R _S1 and R _S2 are source resistances, R _ch is a channel resistance, and R _jfet
Is the resistance of the parasitic junction transistor, R _epi is the resistance of the n ⁻ -type epitaxial layer (low-concentration drain layer),
_sub is the substrate resistance.

As is apparent from FIG. 25, in the present invention,
The channel resistance R _ch is remarkably reduced, the parasitic transistor resistance R _jfet becomes almost zero, the resistance of the epitaxial layer (resistance of the low-concentration drain region) R _epi is dramatically reduced, and the substrate resistance R _sub is reduced according to the present invention. Is inherently zero in the horizontal device. It is clear that the effect of reducing the on-resistance of the device of FIG. 17 is outstanding.

The vertical MOSFET shown in FIG.
In the case of, electrodes must be arranged on the front and back surfaces of the substrate, and it is difficult to integrate a plurality of transistors.
In the lateral MOSFET of the present invention, the electrode structure is a planar type, and integration of a plurality of transistors is easy.

(Method of Manufacturing Device of FIG. 17) FIGS.
A method for manufacturing the device in FIG. 17 will be described with reference to FIG.

Step 1 After the silicon single crystal substrate 280 is formed on the insulating film 202 through the steps of FIGS. 2 to 4 described above, trenches 282a, 282b, 282c are formed as shown in FIG. I do.

Step 2 As shown in FIG. 27, the inside of each trench is oxidized, and then the oxide film inside the other trenches is removed while leaving the oxide film 232 in the central trench 282b.

Step 3 As shown in FIG. 28, first, each trench is filled with doped polysilicon 220a, 220b, 230 having a high impurity concentration. Subsequently, the single crystal layer 280 is patterned,
The surface is oxidized to remove the oxide film on the surface of the buried doped polysilicon 220a, 220b.

Next, a polysilicon layer 240 serving as a horizontal portion of the top gate electrode is formed, and boron (B) is introduced and diffused using this polysilicon layer as a mask.
And heat treatment for damage recovery is performed. Thereafter, an insulating film is formed on the entire surface, a contact hole is formed, and an electrode is formed. Thus, the device shown in FIG.

(4) Fourth Embodiment (Structure of Device) FIG. 29 shows a sectional structure of a device according to a fourth embodiment of the present invention.

A feature of the device of this embodiment is that a channel is formed in the vertical direction (the direction of the trench). The basic structure and operation are the same as those of the device of FIG.

In FIG. 29, reference numerals 320a and 320a
0b is a channel area, and reference numerals 330a, 330
b is a source region. Reference numeral 306b is a trench gate, and reference numerals 310a and 310b are trench drains. Further, reference numerals 306a, 306b and 308 are gate oxide films, reference numeral 302 is a surface insulating film, reference numeral 340 is an interlayer insulating film,
Reference numerals 350a and 350b are drain electrodes, and reference numeral 360 is a source electrode. Also, reference numeral 30
0 is an n ^- epitaxial substrate.

(Method of Manufacturing Device) A method of manufacturing the device of FIG. 29 will be described with reference to FIGS.

Step 1 As shown in FIG. 30, oxide films 302 and 370 are formed on the surface of n ⁻ epitaxial substrate 300, and subsequently, a polysilicon layer 380 is formed on the entire surface.

Step 2 Next, as shown in FIG. 31, the entire surface of the polysilicon layer 380 is etched by RIE, leaving the polysilicons 304a and 304b only on the side walls of the oxide film 302. Subsequently, the polysilicon layer 304a , 304b are oxidized to form oxide films 306a, 306b. The polysilicon 304a, 304b on the side wall is the second gate electrode (G2).
Becomes

Step 3 Next, as shown in FIG. 32, a single crystal layer is formed by using the SPE method described above, and is patterned to form a single crystal island 380.

Step 4 Next, as shown in FIG. 33, trenches 390a, 390
b, 390c are formed.

Step 5 Next, as shown in FIG. 34, the inside of each trench is oxidized, and then the oxide films of the other trenches are removed, leaving only the oxide film 232 of the central trench. Thereafter, doped polysilicon is buried in each trench.

Step 6 Next, as shown in FIG. 35, doped polysilicon (to be a first gate electrode) 2 buried in the central trench 2
Oxidize the surface of 30 to form a cap oxide film 400,
Subsequently, boron (B) is ion-implanted over the entire surface and diffused by heat treatment. At this time, by controlling the heat treatment time, the lower end of the portion of the single crystal island 380 in FIG. 34 that overlaps the polysilicon layers 304a and 304b on the side becomes a p-type region.

Subsequently, arsenic (As) is ion-implanted on the entire surface to recover the damage by heat treatment. As a result, n ⁺ type source layers 330a and 330b are formed,
Further, p ⁻ type channel regions 320a and 320b are formed.

Step 7 Next, as shown in FIG. 36, an insulating film 250 such as CVD SiO ₂ is formed on the entire surface, and subsequently, a contact hole is selectively formed. Thereafter, electrodes are formed, and the device of FIG. 29 is completed.

Although the present invention has been described with reference to specific examples,
The present invention is not limited to this, and various modifications,
Application is possible. For example, the present invention provides a power MOSF
Not only ET but also power devices such as IGBT (insulated gate bipolar transistor) and insulated gate thyristor are applicable.

[0107]

[Brief description of the drawings]

FIG. 1 shows a power MO according to a first embodiment of the present invention.
FIG. 3 is a diagram illustrating a cross-sectional structure of an SFET.

FIG. 2 is a cross-sectional view of the device in a first step for manufacturing the device of FIG. 1;

FIG. 3 is a sectional view of the device in a second step for manufacturing the device of FIG. 1;

FIG. 4 is a sectional view of the device in a third step for manufacturing the device of FIG. 1;

FIG. 5 is a cross-sectional view of the device in a fourth step for manufacturing the device of FIG. 1;

FIG. 6 is a cross-sectional view of the device in a fifth step for manufacturing the device of FIG. 1;

FIG. 7 is a sectional view of the device in a sixth step for manufacturing the device of FIG. 1;

FIG. 8 shows a power MO according to a second embodiment of the present invention.
FIG. 3 is a diagram illustrating a cross-sectional structure of an SFET.

FIG. 9 is a sectional view of the device in a first step for manufacturing the device of FIG. 2;

FIG. 10 is a cross-sectional view of the device in a second step for manufacturing the device of FIG. 2;

FIG. 11 is a sectional view of the device in a third step for manufacturing the device of FIG. 2;

FIG. 12 is a sectional view of the device in a fourth step for manufacturing the device of FIG. 2;

FIG. 13 is a sectional view of the device in a fifth step for manufacturing the device of FIG. 2;

14 is a sectional view of the device in a sixth step for manufacturing the device of FIG.

FIG. 15 is a sectional view of the device in a seventh step for manufacturing the device of FIG. 2;

FIG. 16 is a sectional view of the device in an eighth step for manufacturing the device of FIG. 2;

FIG. 17 shows a power M according to the third embodiment of the present invention.
FIG. 3 is a diagram illustrating a cross-sectional structure of an OSFET.

18 is an enlarged view showing a cross section of a main part of the device of FIG. 17;

FIG. 19 is a diagram simulating a current path of the device shown in FIG. 8;

FIG. 20 is a diagram simulating a current path of the device shown in FIG. 17;

21 is a diagram illustrating a relationship between a trench depth (length of a trench gate and a trench drain) and a normalized on-resistance (Ron) of the device illustrated in FIG. 17;

FIG. 22 shows the channel length (L) of the device shown in FIG.
FIG. 4 is a diagram showing a relationship between the normalized on-resistance (Ron) and the normalized on-resistance (Ron).

FIG. 23 shows a device according to the first embodiment (FIG. 1)
And drain current characteristics of the device according to the third embodiment (FIG. 17) and a conventional example (FIG. 38).
FIG. 3 is a diagram showing a comparison between drain voltage-drain current characteristics of FIG.

24 (a) is a diagram showing the on-resistance component of a conventional vertical transistor, and FIG. 24 (b) is a diagram showing the on-resistance component of the transistor of the present invention in FIG. 17;

FIG. 25 shows each component of the on-resistance of the conventional vertical device;
It is a figure which shows each component of the device of the present invention in comparison.

FIG. 26 is a cross-sectional view of the device in a first step for manufacturing the device of FIG. 17;

FIG. 27 is a sectional view of the device in a second step for manufacturing the device of FIG. 17;

FIG. 28 is a sectional view of the device in a third step for manufacturing the device of FIG. 17;

FIG. 29 shows a power M according to the fourth embodiment of the present invention.
FIG. 3 is a diagram illustrating a cross-sectional structure of an OSFET.

30 is a cross-sectional view of the device in a first step for manufacturing the device of FIG. 29.

FIG. 31 is a cross-sectional view of the device in a second step for manufacturing the device of FIG. 29.

FIG. 32 is a cross-sectional view of the device in a third step for manufacturing the device of FIG. 29.

FIG. 33 is a cross-sectional view of the device in a fourth step for manufacturing the device of FIG. 29.

FIG. 34 is a cross-sectional view of the device in a fifth step for manufacturing the device of FIG. 29.

FIG. 35 is a cross-sectional view of the device in a sixth step for manufacturing the device of FIG. 29.

FIG. 36 is a cross-sectional view of the device in a seventh step for manufacturing the device of FIG. 29.

FIGS. 37 (a) to (d) are cross-sectional views of a device in each step for explaining a solid phase epitaxial growth method (SPE method).

FIG. 38 is a diagram showing a cross-sectional structure of a conventional lateral power MOSFET.

[Explanation of symbols]

200 n ^- epitaxial substrate (lightly doped drain region) 203a, 203b first gate electrode (polysilicon layer) 208a, 208b channel region ^(p -) 206a, 206b the source layer ^{(n +) 210a, 210b n} - -type single crystal layer (Part of low concentration drain region) 220a, 220b Trench drain (polysilicon layer) 230 Trench gate (polysilicon layer) of second gate electrode 240 Horizontal portion of second gate electrode (polysilicon layer) 260a, 260b Drain electrode 270 source electrode

Claims (1)

[Claims] 1. An insulated gate semiconductor device, comprising: a trench gate having a function of forming a carrier accumulation layer, extending from a channel region to a low-concentration drain region functioning as an electric field relaxation region; And a trench drain provided so as to face the semiconductor device.