JPH10214835A - Manufacturing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reconcile a good smoothness of an insulation film by etching-back and a high reliability in an upper-layer wiring pattern. SOLUTION: On an SOG film 7 where wafer's surface steps, caused by lower- layer wiring, are arrested to some extent, a positive photo-resist film 8 is formed, and exposed entirely. With the exposure amount so set that an exposure threshold is exceeded only in the region directly above 1st layer Al patterns 5a-5e where increase in light amount due to superposition of reflection light is expected, a resist pattern 8p remains in self-conformity manner in the region corresponding to the recess of surface steps after development. The resist pattern 8p and the SOG film 7 are etch-backed at the same time. Since an SOG remaining film 7r of sufficient thickness remains at the recess even if the etch- back is performed until the SOG film 7 disappeared in the region directly above 1st layer Al patterns 5a-5e, smoothness on wafer surface is improved, and occurrence of poisoned via and step-breakage of an upper-layer wiring are prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for improving the reliability of forming a multilayer wiring in a semiconductor device manufacturing process.

[0002]

2. Description of the Related Art As the design rules of semiconductor devices have been highly reduced and the degree of integration has increased, the area ratio of wiring portions to the total area of device chips has increased. The multilayer wiring technology in which wiring patterns are stacked on a wafer via an insulating film in many layers has been regarded as an essential technology in recent semiconductor processes in order to suppress an increase in the size of a chip due to an increase in a wiring area.

In adopting the multilayer wiring technology, the following must be considered. First, in the most common upper layer wiring pattern forming process, an Al-based material film is deposited by sputtering. However, since sputtering is not originally a film forming method having a very good step coverage (step coverage), on a substrate having a large surface step, the Al-based material film becomes extremely thin at the step or in the worst case. In some cases, disconnection (so-called step disconnection) may occur. In addition, regarding photolithography, the depth of focus has recently been reduced due to the use of g-line or i-line of a high-pressure mercury lamp or a short-wavelength light source such as a KrF excimer laser as an exposure light source. Since the exposure light is monochromatic light, the degradation of resolution performance due to diffraction and interference is also becoming serious. For this reason,
If the surface of the substrate is smoothed with a photoresist film while leaving large surface irregularities in the insulating film, poor resolution may occur in a portion where the thickness of the photoresist film is large, or reflected light from a step portion of the base may be generated. There are inconveniences, such as the occurrence of so-called halation, which causes a variation in pattern width and a decrease in contrast, concentrated on a specific region of the photoresist film.

Therefore, in order to achieve higher reliability of the upper wiring pattern and higher accuracy of photolithography,
It is extremely important to smooth the surface of the insulating film. As a method of smoothing the insulating film, a method of forming the insulating film itself with a material having a high fluidity, a method of reflowing the film by heating the substrate after the film formation, a method of forming a resist material or SOG (spin After smoothing with a smoothing film such as on-glass), the insulating film and the smoothing film are etched back at substantially the same etching rate, and the convex portion of the insulating film is made horizontal by chemical mechanical polishing (CMP). Methods for removing the same have been proposed. Among these, etchback is a method that is excellent in completeness, simplicity, and economy as a process, and is widely adopted.

Here, an example of a process in the case where the insulating film is ideally smoothed by etch-back will be described with reference to FIGS. FIG. 5 shows a field oxide film 12 (Si) formed by selective oxidation of a Si substrate 11.
Ox), a first-layer polysilicon pattern 13 and first-layer Al patterns 15a to 15e are extended, and the surface of this wafer is formed by plasma CVD using tetraethoxysilane (TEOS) as a source gas. After being covered with the second insulating film 16 (p-TEOS), the SOG film 17 is formed.
Indicates a smoothed state. The first-layer polysilicon pattern 13 and the first-layer Al patterns 15a to 15
e are insulated using the first-layer insulating film 14 (p-TEOS), of which the first-layer Al patterns 15 c and 15
“e” is arranged at a position overlapping the first-layer polysilicon pattern 13. A large surface step generated on the surface of the wafer at the stage when the second insulating film 16 is formed is caused by SO
It is considerably alleviated by the G film 17.

Next, the SOG film 17 is anisotropically etched back. The SOG film 1 in this etch back
7 and the etching rate of the underlying second insulating film 16 are:
Set almost equal. FIG. 6 shows that the above-mentioned etch back is completed in an ideal state, and S
This shows a state where the OG residual film 17r is left. The “ideal state” described here refers to the first-layer Al patterns 15a to 15a.
In the region directly above 5e, no SOG film 17
The first-layer insulating film 16 is exposed and, for example, the first-layer Al
In this state, the SOG residual film 17r is almost flatly buried in a region corresponding to a space between wirings between the patterns 15a and 15b. That is, the SOG residual film 17r improves the smoothness of the wafer surface.

After that, as shown in FIG. 7, the entire surface of the wafer is covered with a third-layer insulating film 19 (p-TEOS).
Via hole 19 facing layer Al patterns 15d and 15e
After openings d and 19e, a second layer Al film is formed on the entire surface of the wafer, and this film is patterned to form second layer Al patterns 20, 20d and 20e as upper wiring patterns. FIG. 7 shows the second-layer Al patterns 20, 20d,
The case where the formation of 20e is ideally performed is shown. Here, the third insulating film 19 is formed smoothly due to the presence of the SOG residual film 17r. Therefore, the accuracy of photolithography performed on the third insulating film 19 is extremely high, and the shape and dimensional accuracy of a resist pattern (not shown) formed by the photolithography are improved. Also,
Via holes 19 formed by dry-etching the insulating film using this resist pattern as a mask
The shape and dimensional accuracy of d and 19e are also improved. Further, the formation and patterning of the second-layer Al film on the third-layer insulating film 19 are also favorably performed.

[0008]

In the above-described smoothing process, the end point of the etch back of the SOG film 17 determines the success or failure of the smoothing. However, since the structure of the SOG film, which is a coating type insulating film, is amorphous, even if the same silicon oxide-based material film is used as the plasma CV film,
Generally, etching is easier than a polycrystalline p-TEOS film formed by D. For this reason, it is actually difficult to end the etch-back in the ideal state shown in FIG. 6 described above. At the start of the etch-back, the etching rates of the SOG film 17 and the second insulating film 16 are set to be substantially equal. In the case of FIG.
In many cases, an over-etched state as shown in FIG. When such an over-etching state occurs,
The thickness of the SOG residual film 17r is insufficient, for example, the first layer Al
The smoothing characteristic of the space between the wirings between the patterns 15a and 15b deteriorates. As a result, as shown in FIG.
The step coverage of the layer Al pattern 20 is degraded, and the reliability of the upper layer wiring is impaired.

Therefore, in order to avoid the above-mentioned over-etching, as shown in FIG.
It is also conceivable to stop the etch back of 7 slightly before the end point. In this case, for example, the first layer Al pattern 15
The region immediately above d is covered with the SOG residual film 17r. A third-layer insulating film 19 is formed on the entire surface of the wafer. Similarly, openings for via holes 19d and 19e are formed, and second-layer Al patterns 20 and 2 are formed by patterning and patterning a second-layer Al film.
When 0d and 20e are formed, as shown in FIG. 11, the Al pattern of the second layer is altered inside the via hole 19d, and there is a high possibility that conduction failure called poisoned via occurs. No particular change occurs in the via hole 19e.

[0010] This is due to moisture contained in the SOG residual film 17r. In the process of forming the SOG film 17, water is generated as a reaction by-product. Depending on the film forming conditions, a large amount of the water or unreacted Si—OH groups is taken into the film. The water content of the SOG film is generally one order of magnitude higher than that of the p-TEOS film. On the side wall surface of the via hole 19d,
Unlike the via hole 19e, the cross section of the SOG residual film 17r is exposed, and moisture is released from the exposed surface under the sputtering environment when forming the second Al film. This moisture prevents normal formation of the second-layer Al pattern 20d.

As described above, in the conventional method of smoothing the surface of the substrate by etching back the SOG film, if the amount of etch back is excessive, disconnection of the upper wiring pattern occurs, and if the amount is insufficient, poisoned vias are generated. Are in a trade-off relationship with each other. However, considering the in-plane variation of the coating thickness of the SOG film and the etch-back speed,
It is very difficult to optimize the amount of etch back. Therefore,
An object of the present invention is to solve this problem and to provide a method of manufacturing a semiconductor device capable of achieving both good smoothing of the surface of a base and high reliability of an upper wiring pattern.

[0012]

SUMMARY OF THE INVENTION A method of manufacturing a semiconductor device according to the present invention is proposed to achieve the above-mentioned object, and comprises a lower wiring pattern and a surface step of a substrate caused by an insulating film covering the lower wiring pattern. Is absorbed by the smoothing insulating film to some extent, and after the etch-back, a region where the remaining film thickness of the smoothing insulating film is likely to be insufficient, that is, a region corresponding to the concave portion of the surface step, is an auxiliary whose etching rate is similar to that of the flattening insulating film. A material pattern is selectively formed in advance to compensate for the total thickness of the object to be etched in this region, and the auxiliary material pattern and the planarizing insulating film are simultaneously etched back, and then the upper wiring pattern is formed on the lower wiring pattern. Make contact.

In particular, when the lower wiring pattern has a high reflectance to exposure light of photolithography and the smoothing insulating film and the insulating film covering the lower wiring pattern are transparent, The auxiliary material pattern can be formed in a self-aligned manner using a mold photoresist film. That is, the entire surface of the positive photoresist film on the smoothing insulating film, the entire surface exposure based on the setting of the amount of light exceeding the exposure threshold only in the region directly above the lower wiring pattern, and the development process may be sequentially performed.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the present invention, an object to be etched back is formed by selectively forming an auxiliary material pattern whose etching rate is similar to that of a smoothing insulating film in a region corresponding to a concave portion of a surface step. The same state as the apparent increase in the thickness of the smoothing insulating film is generated. Here, the concave portion of the surface step is an area corresponding to the inter-wiring space of the lower wiring pattern.

In forming the auxiliary material pattern, a material whose etching rate can be adjusted to a value close to that of the smoothing insulating film, that is, a material whose etching selectivity to the smoothing insulating film can be set to a value close to 1 is selected. I do. At this time, if the etching selectivity is too low, it is necessary to form the auxiliary material pattern thick, and the time and cost required for forming the auxiliary material pattern itself may increase, and the generation of particles due to etch back may increase. . On the other hand, if the etching selectivity is too large, the auxiliary material pattern functions as an etching mask, and there is a possibility that the concave portion of the surface step may become a convex portion at the end of the etch back. Therefore, a preferable range of the etching selectivity is about 0.7 to 1.4.

As a constituent material of the auxiliary material pattern capable of obtaining the above etching selectivity, a photoresist material can be exemplified. By the way, in a general Si-based semiconductor process, an insulating film is generally made of SiO or SiN.
In the exposure wavelength range where normal photolithography is performed, the optical wiring layer is formed using an optically transparent material, and the lower wiring pattern generally uses a metal material having a high reflectance in the above wavelength range, such as Al or W. It is formed. Therefore, the light intensity distribution on the surface of the wafer in a state where the lower wiring pattern having high light reflectance is covered with the optically transparent insulating film is high in the region directly above the lower wiring pattern and low in other regions. ing.

On the surface of the wafer having such a light intensity distribution, if a positive type photoresist film in which an exposed portion becomes soluble in a developing solution by a photodecomposition reaction of a base resin is used, an auxiliary material pattern can be self-aligned. It can be formed. That is, in the region immediately above the lower wiring pattern, the amount of reflected light is added to the amount of incident light of exposure light, and the apparent amount of exposure becomes larger than that in the peripheral region. Therefore, the resist reaction cannot be started only by the original exposure light amount, but if the exposure light amount is set such that the resist reaction proceeds only after the reflected light is added, and the entire surface of the positive type photoresist film is exposed, the lower wiring The positive photoresist film can be solubilized only in the region directly above the pattern. The positive type photoresist film remains only in the other region, that is, the region corresponding to the concave portion of the surface unevenness, and thus the auxiliary material pattern is formed in a self-aligned manner. Such overall exposure does not require a photomask or alignment, and does not significantly impair throughput.

As the smoothing insulating film in the present invention, a film having excellent smoothing characteristics can be appropriately selected and used. For example, normal pressure C using O ₃ and TEOS mixed gas
SiOx film (O ₃ -TEOS) formed by VD method
BPSG film (boron-phosphorus-silicate-glass film) in which B (boron) or P (phosphorus) is vapor-phase doped to the SiOx film to further improve the fluidity.

However, the smoothing insulating film which is the simplest and easy to form and thicken the film forming process is the SOG film. SO
G includes an inorganic SOG utilizing a polymerization reaction of an -OH group,
A part of -OH groups is an organic SOG substituted hydrocarbon groups such as -CH ₃ group, but may be used either. However, since the SOG film has a large amount of residual moisture in the film as described above, when etching back the SOG film, it is necessary to perform the etching so as not to leave this film in the region immediately above the lower wiring pattern. This is because if the SOG film remains, the SOG film is exposed on the side surface of the via hole formed facing the lower wiring pattern in a later step, and moisture is released from the exposed surface when the upper wiring film is formed. This is because there is a great risk of generating a poisoned via.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A specific embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows a field oxide film 2 formed by selective oxidation of a Si substrate 1.
On (SiOx), a first-layer polysilicon pattern 3 and first-layer Al patterns 5a to 5e are extended, and the surface of this wafer is formed by plasma CVD using tetraethoxysilane (TEOS) as a source gas. After being covered with the second insulating film 6 (p-TEOS), an SOG film 7 as a smoothing insulating film and a positive type photoresist film 8 for forming an auxiliary material pattern are sequentially laminated. This shows a state where the entire surface of the photoresist film 8 is exposed.

The first-layer polysilicon pattern 3 is
For example, in the element formation region, a portion extending on a field of a pattern used as a gate electrode of a MOS transistor, or a portion functioning as an upper electrode of a MIS type capacitance element patterned on the field oxide film 2 or a resistance layer of a resistance element. Yes, for example, about 100-300n thick
m, and a pattern width of 1 to 3 μm. The first polysilicon pattern 3 has a thickness of about 200 to 400 n.
m of the first-layer insulating film 4. The first-layer insulating film is laminated on the upper surface of the first-layer polysilicon pattern 3, and an offset portion patterned simultaneously with the first-layer polysilicon pattern 3, and another insulating film covering this pattern Is etched back to form a sidewall portion formed on the side wall surface of the first-layer polysilicon pattern 3.

The first-layer Al pattern is formed, for example, with a thickness of about 500 to 700 nm and a pattern width of about 1 to 3 μm.
m, a maximum of 10 μm or more. The first-layer polysilicon pattern 3 and the first-layer Al patterns 5a to 5e are insulated by using a first-layer insulating film 4 (p-TEOS), of which the first-layer Al patterns 15c and 15e are 1-layer. It is arranged at a position overlapping with the polysilicon pattern 3. In this specification, when it is referred to as “Al pattern”,
It is not limited to a single layer film of pure Al. For example, a Ti barrier metal having a laminated structure such as Ti / TiN and an Al-based conductive film such as an Al-1% Si film or an Al or Al-1% Si-0.5% Cu film. A laminated film in which a film is laminated is also included. Second layer Al described later
The same applies to the patterns (reference numerals 10, 10d, and 10e in FIG. 4). However, an antireflection film such as a TiN film often used in a general Al patterning process is
It is not used in at least the first-layer Al patterns 5a to 5e. This is because when the entire surface of the positive photoresist film is exposed in a later step, the reflected light from the first-layer Al patterns 5a to 5e is formed in order to form a locally increased area of the exposure light amount in the resist film. Is necessary. 2 below
Layer Al pattern (10, 10d, 10e in FIG. 4)
In the case of performing resist exposure in a more self-aligned manner, the same consideration must be taken.

The second insulating film 6 is, for example, about 500
It is formed almost conformally over the entire surface of the wafer with a thickness of about 700 nm. At this stage, a surface step having a maximum of about 700 to 900 nm is generated on the wafer. The above-mentioned surface step is reduced by about 300 to 5 by covering the entire surface of the wafer with the SOG film 7 which is a smooth insulating film having high fluidity.
Relaxed to 00 nm. The SOG film 7 is formed by, for example, using an organic SOG material (manufactured by Tokyo Ohka Kogyo Co., Ltd., trade name: OC).
DT-11), and the film thickness at the flat part is about 400 to
It was 600 nm.

The positive photoresist film 8 laminated on the SOG film 7 is made of, for example, a novolak-based resist material for i-line (THMR-iP345 manufactured by Tokyo Ohka Kogyo Co., Ltd.).
0)), and the maximum film thickness was about 1 μm. At this stage, the surface steps of the wafer were almost absorbed. The entire surface of the positive photoresist film 8 was exposed using an i-line stepper with an exposure light amount of 200 to 300 mJ / cm ² . Under these conditions, the first layer Al patterns 5a to 5a
In the region directly above e, the amount of exposure light exceeds the exposure threshold value due to the influence of the reflected light, and the molecular weight of the base resin is reduced. The resin does not decompose.

After the post-baking, the positive photoresist film 8 was developed. As shown in FIG. 2, a resist pattern 8p was formed in a self-aligned manner as an auxiliary material pattern in a region corresponding to the concave portion of the surface step. Formed.

Next, the wafer was carried into a magnetron RIE apparatus, and as an example, the SOG film 7 and the resist pattern 8p were simultaneously etched back under the following conditions. CHF ₃ flow rate of 20~30 SCCM pressure 30~40 Pa RF power 500~600 W (13.56 M
Hz) The resist of the SOG film 7 under the above etch-back condition
The etching selectivity for the pattern 8p was almost 1. Since this etch back is performed in a state where the thickness of the SOG film is apparently increased in a region corresponding to the concave portion of the surface step, the margin of the end point determination timing is much larger than that of the conventional process. As a result, at the end of the etch-back, as shown in FIG. 3, the SOG residual film 7r having a sufficient thickness remains in the region corresponding to the concave portion of the surface step, and the convex portion of the surface step, that is, the lower wiring patterns 5a to 5g.
In the region directly above 5e, the SOG film 7r was completely removed.
The SOG residual film 7r improves the smoothness of the wafer surface.

Thereafter, as shown in FIG. 4, the entire surface of the wafer is covered with a third insulating film 9 (p-layer) having a thickness of about 500 to 700 nm.
-TEOS). Due to the presence of the SOG residual film 7r, the smoothness of the third insulating film 9 was good. Subsequently, photolithography was performed on the third insulating film 9 to form a resist pattern (not shown). The precision of this photolithography performed on a highly smooth surface was extremely high, and the shape and dimensional precision of the resist pattern (not shown) were good. Further, the third-layer insulating film 9 is dry-etched using this resist pattern as a mask, thereby forming the first-layer Al patterns 5d and 5e.
The via holes 9d and 9e having a diameter of about 0.35 μm facing the substrate were opened. Since the shape and dimensional accuracy of the resist pattern were high, the shapes and dimensional accuracy of the formed via holes 9d and 9e were also good.

Further, Ti and having a thickness of about 30 nm are formed on the entire surface of the wafer by sputtering and reactive sputtering.
Film and TiN film with a thickness of about 70 nm (both not shown)
Were formed sequentially to form a Ti-based barrier metal, and an Al-1% Si film having a thickness of about 0.8 to 1.0 μm was formed by a sputtering method. The coverage of the laminated film composed of the Ti-based barrier metal and the Al-1% Si film was extremely good.

Further, the above-mentioned laminated film is patterned to form a second layer Al as shown in FIG.
Patterns 10, 10d, and 10e were formed. First layer Al
In the second-layer Al pattern 10 formed in the area corresponding to the space between the wirings of the patterns 5a and 5b, the occurrence of the disconnection as in the related art was not observed. Also, the first layer A
2nd layer Al pattern 1 contacting 1 pattern 5d
For 0d, generation of a poisoned via as in the related art was not observed. This is because the SOG film 7 has disappeared from the upper region of the lower wiring pattern 5d,
This is because the exposure of the SOG residual film 7r on the side wall surface of d is prevented.

Although the specific embodiments of the present invention have been described above, the present invention is not limited to these embodiments. For example, details such as details of the wafer configuration, dimensions and film thickness of each part, and process conditions can be appropriately changed, selected, and combined.

[0031]

As is clear from the above description, according to the present invention, it is possible to achieve both the smoothing of the insulating film and the high reliability of the upper layer wiring pattern, which were conventionally difficult to achieve at the same time. In particular, if the auxiliary material pattern is formed on the smoothing insulating film in a self-aligned manner by utilizing the difference in the optimal exposure light amount existing in the wafer surface, the multi-layer wiring can be performed without significantly increasing the number of steps. The yield and reliability in formation can be greatly improved. Therefore, the present invention
It makes an extremely large contribution to the manufacture of highly integrated, high-performance, and ultra-fine semiconductor devices.

[Brief description of the drawings]

FIG. 1 illustrates an example of a process to which the present invention is applied.
FIG. 4 is a schematic cross-sectional view showing a state in which a positive photoresist film covering the wafer surface smoothed by the film is entirely exposed.

FIG. 2 is a schematic cross-sectional view showing a state where a positive photoresist film of FIG. 1 is developed and a resist pattern is formed in a region corresponding to a concave portion of a surface step.

FIG. 3 is a schematic cross-sectional view showing a state in which the resist pattern and the SOG film of FIG. 2 are etched back, and an SOG residual film is left in a recess at a surface step.

4 is a schematic cross-sectional view showing a state in which a third-layer insulating film has been formed, a via hole has been opened, and an upper-layer wiring has been formed on the wafer of FIG. 3;

FIG. 5 is a schematic cross-sectional view showing a state in which a wafer surface is smoothed with an SOG film in a conventional process example.

6 is a schematic cross-sectional view showing a state where the etch back of the SOG film of FIG. 5 is ideally performed.

7 is a schematic cross-sectional view showing a state in which a third-layer insulating film has been formed, a via hole has been opened, and an upper-layer wiring has been formed on the wafer of FIG. 6;

FIG. 8 is a schematic cross-sectional view showing a state in which the SOG film of FIG. 5 is over-etched and the smoothness of an insulating film is deteriorated.

FIG. 9 is a schematic cross-sectional view showing a state in which formation of a third-layer insulating film, opening of a via hole, and formation of an upper-layer wiring are performed on the wafer of FIG. 8 and disconnection of the upper-layer wiring has occurred.

FIG. 10 is a schematic cross-sectional view showing a state in which the etch back of the SOG film of FIG. 5 is insufficient and an SOG residual film is generated on some wirings.

11 is a schematic diagram showing a state in which a third insulating film is formed, a via hole is opened, and an upper layer wiring is formed on the wafer of FIG. 10, and a poisoned via is generated by exposing the SOG film to the side wall surface of the via hole. FIG.

[Explanation of symbols]

2. Field oxide film 3. First-layer polysilicon pattern 4. First-layer insulating film (p-TEOS) 5a, 5
b, 5c, 5d, 5e: First layer Al pattern 6: Second layer insulating film 7: SOG film 7r: SOG residual film 8: Positive photoresist film 8p: Resist pattern 9: Third layer insulating film 9d,
9e: Via hole 10, 10d, 10e: Second layer Al
pattern

Claims (4)

[Claims] A first step of covering the entire surface of a substrate having a surface step caused by disposing a lower wiring pattern covered with an insulating film with a smoothing insulating film; A second step of forming an auxiliary material pattern made of a material having an approximate etching rate with the smoothing insulating film in a region corresponding to the concave portion of the surface step, and simultaneously etching the auxiliary material pattern and the smoothing insulating film. A semiconductor device comprising: a third step of selectively leaving the smoothing insulating film in the concave portion of the surface step by backing; and a fourth step of contacting the lower wiring pattern with an upper wiring pattern. Manufacturing method. 2. The method according to claim 1, wherein the auxiliary material pattern is formed using a positive photoresist film. 3. The smoothing insulating film and the insulating film have a relatively high transmittance to exposure light, and the lower wiring pattern has a relatively high reflectance to the exposure light. In the case of having the above, in the second step, the entire surface of the positive type photoresist film is formed on the smoothing insulating film, the entire surface is exposed based on the light amount setting that exceeds the exposure threshold only in the region directly above the lower wiring pattern, and 3. The method according to claim 2, wherein the auxiliary material pattern is formed in a self-aligned manner through successive development processes. 4. The method according to claim 1, wherein the smoothing insulating film is formed using an SOG film, and the etch back in the third step is performed from a region immediately above the lower wiring pattern until the SOG film disappears. A method for manufacturing a semiconductor device according to claim 1.