JPH10214796A - Formation method of wiring connecting structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring connecting structure forming method for semiconductor device, by which a high-speed semiconductor device having a low contact resistance can be obtained. SOLUTION: A second wiring layer 19 composed of a tungsten silicide is formed so that at least part of the layer 19 may be directly brought into contact with the N<+> diffusion area of a silicon substrate 11. Then the silicon substrate 11 is subjected to lamp annealing. After annealing, a silicon oxide film 20 is formed on the wiring layer 19 by the HTO-CVD method. When the film 20 is formed, the silicon substrate 11 and wiring layer 19 are exposed to a high temperature.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for forming a wiring connection structure in a semiconductor device.

[0002]

2. Description of the Related Art In a semiconductor device, when a contact is made between a wiring layer and a source / drain region on a semiconductor substrate, titanium is provided in the source / drain region in order to reduce the contact resistance at the contact portion. Forming a silicide layer such as silicide (TiSi) has been performed. Thereby, the operation speed of the device is improved.

[0003]

In recent years, refractory metal silicides such as tungsten silicide (WSi) have been used for wiring layers for the purpose of reducing contact resistance and increasing the speed of devices. In the connection structure between the wiring layer made of the refractory metal silicide and the source / drain region, the silicide layer is formed in the source / drain region as described above in order to further reduce the contact resistance. Can be considered.

However, above a wiring layer made of a refractory metal silicide (hereinafter referred to as a silicide wiring layer),
When forming an interlayer insulating film or an upper wiring layer, a high-temperature heat treatment may be performed. For example, when a high-temperature oxide film (HTO) is used as an interlayer insulating film, a CVD process is performed at about 800 ° C. In addition, in order to planarize a layer above the silicide wiring layer, for example, reflow may be performed at 850 ° C. or higher.

[0005] The inventors have found that the contact resistance between the silicide wiring layer in which the silicide layer is formed in the source / drain regions and the substrate is exposed to high heat by such a heat treatment, the contact resistance is significantly increased. I found something. Therefore, in order to reduce the resistance of the contact portion,
Forming a silicide layer in a contact portion and using a refractory metal silicide in a wiring layer means that after forming the contact portion, a silicon thermal oxide film or HTO is formed on the upper side of the silicide wiring layer, or reflow is performed. If this is done, the contact resistance is rather increased and the speed of the device is reduced.

For example, when a silicide wiring layer is used as a wiring layer in a multilayer wiring structure such as a TFT load type SRAM, an interlayer insulating film and an upper wiring layer need to be formed above the silicide wiring layer. As described above, it is not preferable that the high-temperature heat treatment be limited.

The present invention has been made in view of the above, and provides a method of forming a wiring connection structure in a semiconductor device capable of obtaining a high-speed semiconductor device with lower contact resistance.

[0008]

SUMMARY OF THE INVENTION The present invention comprises a step of forming a wiring layer such that at least a part thereof is in direct contact with a silicon substrate, a step of annealing the substrate and the wiring layer, and a step of annealing the wiring layer. And performing a heat treatment for exposing the substrate and the wiring layer to a high temperature after performing the method.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail. An embodiment of the present invention to be described next
This is an application of the method for forming a wiring connection structure of the present invention to an SRAM having an FT load type memory cell. In the following description, for convenience, of the TFT load type memory cells,
A structure in which a pair of pull-down transistors Tr1 and Tr2 and a TFT transistor formed above the pair of pull-down transistors Tr1 and Tr2 will be described.

First, as shown in FIG. 1A, a pair of pull-down transistors Tr1 and Tr
Form 2 Pull-down transistors Tr1, Tr2
Is as follows. For example, LOCOS is applied to the P well 12 formed on the main surface of the N-type silicon substrate 11.
According to the method, field oxide film 13 having a thickness of, for example, 4000 ° is formed. In the active region surrounded by the field oxide film 13, a common source region S of the pull-down transistors Tr1 and Tr2 of the TFT-SRAM and separate and independent drain regions D1 and D2 are set to N ^+.
Each is formed of an impurity diffusion layer. Further, a first gate electrode G1 for one pull-down transistor Tr1 is provided on a channel region between the source region S and one drain region D1 via a thin gate oxide film 14. A gate insulating film 1 is formed on a channel region between the source region S and the other drain region D1.
4 through the second pull-down transistor Tr2.
A gate electrode G2 is provided. The first and second gate electrodes G1 and G2 are formed, for example, of a first polysilicon film 15 having a thickness of 3000Å and a silicon nitride film 17 having a thickness of 1800１.
Are sequentially laminated, but the silicon nitride film 17 is removed from the second gate electrode G1. A first polysilicon film 15 is formed. These gate electrodes G1,
Spacer oxide films 16 are formed on the side surfaces of G2.

A silicon oxide film 18 as an interlayer insulating film is formed on the surface of the silicon substrate 11 including the pair of pull-down transistors Tr1 and Tr2 and the field oxide film 13 as described above. A contact hole H1 and a via hole H2 are formed in a part of the silicon oxide film 18, respectively. As shown in FIG. 1A, the surface of the gate electrode G1 of one pull-down transistor Tr1 and the surface of the drain region D2 on the other pull-down transistor Tr2 side are exposed in these contact holes H1 and via holes H2.

A tungsten silicide (WSix) film having a thickness of, for example, 600 ° is directly formed on the surface of the silicon insulating film 18 including the exposed surfaces of the gate electrode G1 and the drain region D2, for example, at a CV of 600 to 1200 ° C.
D. Next, the WSix film is patterned into a desired wiring pattern by a general photolithography technique, and as shown in FIG.
9 is formed. More specifically, the WSix film is patterned by applying a resist on the surface of the WSix film, then exposing and developing to form a resist pattern, and using the obtained resist pattern as a mask to form the WSix film with SF6, for example. This can be performed by etching with RIE.

After forming the second wiring layer 19 as described above, the silicon substrate 11 including the pull-down transistors Tr1 and Tr2 and the second wiring layer 19 is subjected to a high-temperature heat treatment. This heat treatment is specifically performed at 800
Lamp annealing for 15 to 60 seconds at a temperature of 900 to 900C. More specifically, lamp annealing is performed at 850 ° C. for 30 seconds in a nitrogen gas atmosphere or in a vacuum.

Here, WSix is used as the second wiring layer 19.
Although a film is used, any conductive film containing at least silicon atoms, such as polysilicon or high melting point silicide, such as a polysilicon film, may be used.

After the heat treatment, as shown in FIG.
On the surface of the silicon oxide film 18 including the second wiring layer 19, as an interlayer insulating film, for example, 800 ° C. HTO-CVD
(High-temperature-oxide chemical vapor depositio
n) or LTO-CVD (Low-temperature-ox) at 400 ° C
A silicon oxide film 20 of 600 to 1200 ° is formed by ide chemical vapor deposition).

Next, a resist is applied on the surface of the silicon oxide film 20, exposed and developed to form a resist pattern 21 as shown in FIG. Using this resist pattern 21 as a mask, RIE using, for example, CF4 and CHF3 is performed to form a via hole H3 in the silicon oxide film 20 as shown in FIG. After that, the resist pattern 21 is removed by an ordinary method.

Thereafter, as shown in FIG. 3A, for example, LPCVD at 550 ° C. is performed on the surface of the silicon oxide film 20 including the second wiring layer 19 exposed in the via hole H3.
(Low-pressure chemical vapor deposition)
For example, an amorphous silicon film 22 having a thickness of 180 ° is formed. Next, annealing is performed at, for example, 600 ° C. for 10 hours to recrystallize the amorphous silicon film 22 to obtain a polysilicon film 23.

Next, the polysilicon film 23 is patterned by using a known photolithography technique. As a result, a third wiring layer 24 is obtained as shown in FIG. The third wiring layer 24 becomes a base of the TFT transistor, and a channel region (not shown) and a source / drain region (not shown) of the TFT transistor are formed in a conventional manner.

Thereafter, the third wiring layer 2 shown in FIG.
Non-doped silicate glass (NSG) and borophosphosilicate glass (BPSG) are sequentially deposited on the surface of the silicon oxide film 20 including the silicon oxide film 20 by CVD to form an interlayer insulating film 25. Next, as shown in FIG. 6, which is a cross-sectional view corresponding to the cross section MM in FIG.
After a via hole VH is formed in the interlayer insulating film 25 and the silicon oxide film 20 above the pad portion PD, a tungsten plug WP is formed in the via hole VH. Further, a bit line 26 made of an aluminum layer is formed on the interlayer insulating film 25. The bit line 26 is formed so as to be electrically connected to the drain region D of the pass transistor via the pad portion PD and the tungsten plug WP in the via hole. Through the above steps, the TFT load type SRAM 10 is formed.

4 (A), (B) and FIG. 5 (A),
(B) is a plan view showing a layout of a memory cell of the TFT load type SRAM 10. FIG. 4A shows FIG.
As shown in FIG. 1A, a contact formed on a field oxide film 13, a first polysilicon film 15 as a first wiring layer forming gates G1 and G2 of pull-down transistors Tr1 and Tr2 and a word line WL, and a silicon oxide film 18 are formed. 2 shows a layout of a hole H1 and a via hole H2. The silicon oxide film 18 is omitted for convenience.

FIG. 4B shows a state in which a second wiring layer 19 is formed on the layout shown in FIG.
FIG. 5A shows the second wiring layer 1 shown in FIG.
9 shows a state in which a silicon oxide film 20 is formed on the surface of a silicon oxide film 18 including the silicon oxide film 9 and a via hole H3 is formed.
The silicon oxide film 20 is omitted for convenience. The third wiring layer 24 is indicated by a virtual line. FIG.
A state in which a third wiring layer 24 is formed on the layout shown in FIG.

In the TFT load type SRAM 10 described above, the silicon oxide film 20 as an interlayer insulating film between the second wiring layer 19 and the third wiring layer 24 becomes a gate oxide film of the TFT, and is as small as possible. Thinner is TFT
Is preferred in terms of the characteristics of However, the silicon oxide film 20
Is thin (for example, 300 °) or when it is a plasma CVD oxide film or a low temperature oxide film (LTO film), the interlayer breakdown voltage cannot be maintained. In order to solve this problem, it is preferable to use an oxide film having a high oxide film breakdown voltage, for example, HTO.

However, as in the prior art, the silicon substrate 11
Source / drain region and second wiring layer 19 formed in
In the case where a high melting point metal silicide such as titanium silicide is formed in the contact portion for the purpose of reducing the contact resistance in the contact portion and improving the speed, as described above, the silicon substrate such as the HTO is formed. When heat treatment is performed to expose the 11th and second wiring layers 19 to a high temperature, the contact resistance is reduced to about 10
It rises to 0 times.

Therefore, the TFT-SRA according to the present embodiment
In M10, the silicon substrate 11 and the second wiring layer 19
Without forming refractory metal silicide on the contact part of
By forming the second wiring layer 19 so that a part thereof is in direct contact with the silicon substrate 11, if the HTO is to be formed thereafter, the source S
In addition, the contact resistance between the N ⁺ diffusion layer constituting the drains D1 and D2 and the second wiring layer can be reduced. Further, the contact resistance between the second wiring layer 19 and the third wiring layer 24 in the via hole H3 can be reduced. Furthermore, the junction leakage current between the N ⁺ diffusion layer and the P-well also decreases.

After the formation of the second wiring layer 19, for example, 800
By performing the annealing at 1000 ° C., various characteristics can be further improved.

According to the wiring structure forming method of the present invention, the HT
Not only the formation of O but also high temperature such as reflow, for example, 8
Similar effects are obtained when heat treatment is performed at 50 to 900 ° C. to expose the silicon substrate 11 and the second wiring layer.

After the formation of TiSi / WSi, a high-temperature oxide film (H
A TiWSi alloy layer is formed at the interface in the thermal process by the deposition of the (TO film). This TiWSi is composed of TiSi, WSi
Since the resistance is higher than that of the two-phase alloy, the contact resistance increases. According to the method for forming a wiring connection structure of the present invention, the formation of this TiWSi alloy layer can be prevented.

[0028]

7 to 9 are explanatory diagrams showing the results of tests performed to prove the effects of the present invention.

FIG. 7 shows the contact resistance between the second wiring layer made of tungsten silicide and the N ⁺ diffusion region formed on the silicon substrate, in the case where titanium silicide is formed in the contact portion (comparative example). When the second wiring layer is formed directly on the N ⁺ diffusion region without forming titanium silicide (Example 1), the second wiring layer is formed after forming the second wiring layer in the same manner as in Example 1. 850 ° C for wiring layer
FIG. 9 is a characteristic diagram showing a result of an investigation on a case where the lamp annealing process is performed in Example (Example 2). As is clear from FIG. 7, the contact resistance of Example 1 was lower than that of Comparative Example, and Example 2 was lower than that of Comparative Example.

FIG. 8 shows the results of examining the contact resistance between the second wiring layer made of tungsten silicide and the third wiring layer made of polysilicon in Comparative Examples, Examples 1 and 2. It is a characteristic diagram. As is clear from FIG. 8, the contact resistance of Example 1 was lower than that of Comparative Example, and the contact resistance of Example 2 was lower.

FIG. 9 is a characteristic diagram showing the results of examining the junction leakage of the N ⁺ diffusion region and the P-well for the comparative example, the first embodiment and the second embodiment. From FIG. 9, it was found that the junction leakage current was lower in Examples 1 and 2.

[0032]

As described above, according to the method for forming a wiring connection structure of the present invention, the wiring layer is formed so that at least a part thereof is in direct contact with the substrate, and the HT is formed later.
When a high-temperature heat treatment such as O formation or reflow is performed, a reduction in contact resistance between the substrate and the wiring layer can be achieved.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views showing each step of an embodiment of a method for forming a wiring connection structure of the present invention.

FIGS. 2A and 2B are explanatory views showing each step of an embodiment of a method for forming a wiring connection structure of the present invention.

FIGS. 3A to 3C are cross-sectional views showing respective steps of one embodiment of a method for forming a wiring connection structure of the present invention.

FIGS. 4A and 4B are TFT load type SRAMs to which the method for forming a wiring connection structure according to the first embodiment is applied;
FIG. 4 is a plan view showing a layout of a memory cell of FIG.

FIGS. 5A and 5B are TFT load type SRAMs to which the wiring connection structure forming method according to the first embodiment is applied;
FIG. 4 is a plan view showing a layout of a memory cell of FIG.

FIG. 6 is a sectional view showing a memory cell of the TFT load type SRAM corresponding to a section MM in FIG. 5B.

FIG. 7 is a characteristic diagram showing contact resistance between a second wiring layer and an N ⁺ diffusion region on a silicon substrate.

FIG. 8 is a characteristic diagram showing contact resistance between a second wiring layer and a third wiring layer.

FIG. 9 is a characteristic diagram showing a leak current between an N ⁺ diffusion region and a P-well on a silicon substrate.

[Explanation of symbols]

10: TFT load type SRAM, 11: silicon substrate, 1
2 ... P-well, 13 ... Field oxide film, 14 ... Gate oxide film, 15 ... First polysilicon film, 16 ... Space oxide film, 17 ... Silicon nitride film, 18 ... Silicon oxide film, 19 ... Second layer wiring Layers, 24... Third wiring layer, 25.
Interlayer insulating film, 26 ... bit line.

Continuing on the front page (72) Inventor Taketoshi Hayashi 1-2-1, Marunouchi, Chiyoda-ku, Tokyo Nihon Kokan Co., Ltd. (72) Inventor Masahiko Omatsu 1-2-1, Marunouchi, Chiyoda-ku, Tokyo Nihon Kokan Inside the corporation

Claims (2)

[Claims] Forming a wiring layer so that at least a part thereof is in direct contact with a silicon substrate; and performing a heat treatment for exposing the substrate and the wiring layer to a high temperature. Method. 2. The method for forming a wiring connection structure according to claim 1, wherein after annealing the substrate and the wiring layer, a heat treatment is performed to expose the substrate and the wiring layer to a high temperature.