JPH10209438A - Manufacture of mis-type semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve insulation-resistance characteristics and reliability by coating an oxidation-preventive film on a polycrystalline silicon layer which is such a part as to be a gate electrode layer, and allowing other part to be a silicon oxide film through thermal oxidation, for forming an insulating film against a metal wiring. SOLUTION: On a polycrystalline silicon layer 44, a silicon nitride film 55 is deposited by plasma CVD method. Then, the silicon nitride film 55, polycrystalline silicon layer 44, and an oxide film 43 on a p-type wafer 41 are selectively etched to form an opening 45. A phosphorus ion is implanted though the opening 45, and by thermal treatment, an n source region 46 and an n drain region 47 are formed. By thermal oxidation, such polycrystalline silicon layer 44b as part with no silicon nitride film 55 is made to be a thermal oxide film 43b. At the same time, the thermal oxide film 43b is also formed on the surface of exposed n source region 46 and n drain region 47. By this method, the p-type wafer 41 and a metal wiring are insulated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a basic element of an integrated circuit formed on a semiconductor substrate, and more particularly to a MIS element having an insulated gate structure composed of a metal, an insulating film and a semiconductor, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Semiconductor integrated circuits have become indispensable components for all electronic devices. Therefore, with the advancement of electronic devices, the performance required for such semiconductor integrated circuits is also becoming higher and higher in function and higher in response to the downsizing of the devices, and lowering the voltage and lowering the power consumption in order to respond to battery driving of the devices. It has been diversified.

FIGS. 6A to 6E show one MOSFET (metal-oxide-semiconductor field effect transistor) of a MIS (metal-insulator-semiconductor) type element which is a basic unit of a semiconductor integrated circuit. FIGS. 7A to 7C are cross-sectional views in main steps shown in the order of steps for explaining the conventional manufacturing method of FIG.
At present, MOSF is a basic unit in semiconductor integrated circuits.
A method of manufacturing an ET includes a trench MOSFET in which a trench (trench) is formed and a gate electrode is buried in the trench,
Although there are some variations such as a change or addition of a process procedure, the process is basically based on the process flow shown in FIG. Hereinafter, a conventional n-channel MOSFET will be described with reference to FIG.
Will be described.

[0004] The (100) plane is the main surface, and the specific resistance is 3Ω ·
A p-type wafer 1 having a thickness of 500 μm and a thickness of 500 μm is cleaned by pretreatment, and then thermally oxidized to form a thin oxide film 3 having a thickness of about 70 nm on the surface. Is deposited by 0.5 μm [FIG. 6A].
Next, a photoresist is applied, a pattern is formed by processes such as exposure and development using a photomask, and the polycrystalline silicon layer 4 and the oxide film 3 on the p-type wafer 1 are selectively etched to form openings 5. Is provided [FIG. 2 (b)].

After the photoresist is stripped, phosphorus ions are implanted through the opening 5 and heat-treated to form an n source region 6 and an n drain region 7 in a self-aligned manner (FIG. 1C). The diffusion depth is 0.25 μm. The dose of phosphorus ions is 1 × 10 ¹⁶ / cm ² . At this time, phosphorus ions are also implanted into the polycrystalline silicon layer 4 and heat treatment is performed, so that the polycrystalline silicon layer 4 has sufficient conductivity.

After depositing a phosphor glass film (PSG film) 8 on the entire surface by a plasma CVD method, a contact hole 9 for making an electrical connection to a necessary portion of the PSG film 8 is formed by using a photolithography technique [ FIG. After depositing an Al alloy film 10 on the entire surface by sputtering, the source electrode 11 in contact with the n source region 6, the drain electrode 12 in contact with the n drain region 7, and the n source region 6 and n drain using photolithography technology. A gate electrode 13 is formed in contact with the polycrystalline silicon layer 4a on the surface exposed portion 1a of the p-type wafer 1 sandwiched between the region 7, and a wiring 14 is formed from the gate electrode 13 [FIG. Oxide film 3a on surface exposed portion 1a of p-type wafer 1 sandwiched between n source region 6 and n drain region 7 is a gate oxide film, and polycrystalline silicon layer 4a thereon is a gate electrode layer. Thereafter, a nitride film for protecting the surface is deposited by a plasma CVD method to complete the MOSFET.

The above is the basic process of forming a MOS structure. A thin oxide film 2 serving as a gate oxide film is formed on a p-type wafer 1, and a polycrystalline silicon layer 3 serving as a gate electrode layer is formed of the thin oxide film. 2 is deposited. recent years,
Higher functionality, higher integration, higher speed, lower voltage,
In order to respond to these trends, such as lower power consumption and higher memory densities, the gate oxide film has been further thinned and improved with the progress of miniaturization, and the gate electrode for high-speed driving There are problems such as low resistance.

In other words, with regard to the further reduction of the thickness of the gate oxide film, in recent years, this gate oxide film has tended to become thinner and thinner as devices have become finer and driven at lower voltages. For example, in a power MOSFET or the like, 100 n
m to 50 nm, for computer DRAM, 30 nm for 1 Mbit to 20 nm for 4 Mbit,
The thickness has been reduced to 10 nm for 16 Mbit and 8 nm for 64 Mbit. In the conventional method, the silicon surface before the gate oxide film is formed is not perfect even though it is cleaned by various pretreatment methods, and the natural oxide film grows before the gate oxide film is formed. As the oxide film becomes thinner, it becomes more difficult to keep the film thickness uniform, and the importance of interface cleanliness increases.

[0009] Regarding the conventional method, since the polycrystalline silicon layer is used in the conventional method, even if an attempt is made to lower the resistance by doping impurities, the expected low resistance is due to the grain boundary of the polycrystalline silicon layer. There is a problem that can not be achieved. In this regard, a silicide which is a compound of silicon and a metal such as molybdenum or titanium may be used instead of the polycrystalline silicon layer. However, in the case of silicide formation, since it is an intermetallic compound of silicon,
Depending on the formation method, there is a problem that impurities caused by metal contaminate the gate oxide film and deteriorate the quality of the gate oxide film.

[0010] To solve these problems, one of the inventors described in Japanese Patent Application Laid-Open No. 8-250721 a so-called SOI
(Silicon on insulator) using wafer
A MIS type semiconductor device including a gate insulating film formed of a buried insulating layer formed inside a semiconductor substrate and a gate electrode processed from a single crystal semiconductor substrate on the insulating layer has been proposed.

In this case, a gate oxide film and a gate electrode can be formed without using the substrate surface. That is, since the interface between the gate oxide film and silicon is formed inside the silicon substrate, a natural oxide film and an interface having no problem with the substrate surface due to pretreatment can be formed. Also,
Since the gate electrode is a single crystal that retains crystallinity, there is no problem due to the grain boundary of polycrystalline silicon as in the prior art, and there are advantages such as low resistance.

In particular, if a second conductivity type diffusion region is formed by introducing a second conductivity type impurity and then performing a heat treatment in a portion of the single crystal silicon substrate having less crystal defects located under the buried insulating layer, A strong junction is formed, and a semiconductor element that can withstand a high withstand voltage without being affected by crystal defects is obtained. FIGS. 7A to 7E are cross-sectional views showing main steps in the order of manufacturing steps of a MOSFET using such an SOI wafer. .

SOI wafer 2 having (100) plane as main surface
Boron ions 38 are implanted into the SOI layer 24 of FIG.
(A)]. The SOI layer 24 is activated by the subsequent heat treatment, so that the implanted boron ions are activated and have sufficient conductivity. In the case of the single crystal SOI layer 24, the specific resistance can be reduced by about one digit compared to the case of the polycrystalline silicon layer. SOI layer 24
A photoresist is applied to the surface, a pattern is formed by a process such as exposure and development using a photomask, and an opening 25 is provided by selectively etching the SOI layer 24 and the buried oxide film 23 of the SOI wafer 21. Fig. (B)]. The specific resistance of the SOI substrate 22 is 3 Ω · cm, the thickness is 500 μm, the thickness of the buried oxide film 23 is 50 nm, and the thickness of the SOI layer 24 is 200 nm.

Next, after the photoresist is stripped, phosphorus ions are implanted through the openings 25 and heat-treated.
An n source region 26 and an n drain region 27 are formed in a self-aligned manner (FIG. 3C). The diffusion depth is 0.25 μm. The dose of phosphorus ions is 1 × 10 ¹⁶ / cm ² .
A phosphor glass film (PSG) is formed on the entire surface by plasma CVD.
After depositing a film (film) 28 of 1 μm, a contact hole 29 for making an electrical connection to a necessary portion of the PSG film 28 is formed by using a photolithography technique [FIG.

After an Al alloy film 30 having a thickness of 1 μm is deposited on the entire surface by a sputtering method, a photolithography technique is used.
Source electrode 31 in contact with n source region 26, drain electrode 32 in contact with n drain region 27, and substrate portion 2 sandwiched between n source region 26 and n drain region 27
A gate electrode 33 that contacts the SOI layer 24a on the second surface exposed portion 22a and a wiring 34 formed therefrom are formed [FIG. Oxide film 23a on surface exposed portion 22a
Is a gate oxide film, and the SOI layer 24a thereon is a gate electrode layer. Thereafter, a nitride film for protecting the surface is deposited by a plasma CVD method to complete the MOSFET.

There are two known SOI wafer manufacturing methods. One method is to bond two silicon wafers via an oxide film and scrape off one silicon wafer surface to a desired SOI thickness. Another method is to apply oxygen ions to the surface of the silicon wafer. It is a method of implanting and annealing. The latter method is called SIMOX (name created from the acronym Separation by Implanted Oxygen), and its wafer is SIM
OX wafer [Izumi et al .: Japanese Journal of Applied Physics, Vol. 19, Volume 1
9-1, page 151, 1980]. For example, oxygen can be implanted at 3 × 10 ¹⁷ / cm ² and heat-treated at 1330 ° C. to form a 200 nm SOI layer and a 50 nm buried oxide film.

[0017]

However, FIG.
In the conventional method for manufacturing a MIS type semiconductor device as shown in FIG. 7, a polycrystalline silicon layer or a single crystal silicon layer other than a part to be a gate electrode layer is covered with an insulating film such as a PSG by a CVD method. However, the insulating film formed by the CVD method is inferior in film quality to, for example, a thermal oxide film, and has poor uniformity in thickness. However, there is a problem that reliability is low.

In view of this problem, an object of the present invention is to provide a method for manufacturing a highly reliable MIS type semiconductor device having a high withstand voltage.

[0019]

According to the present invention, there is provided an MIS type semiconductor device having a gate insulating film on a surface of a semiconductor substrate and a gate electrode layer made of a polycrystalline silicon layer on the gate insulating film. Forming the insulating film and the polycrystalline silicon layer on the surface of the semiconductor substrate sequentially, and preventing oxidation on the polycrystalline silicon layer in a portion of the insulating film and the polycrystalline silicon layer to be the gate electrode layer. The method includes a step of coating the film and converting the polycrystalline silicon layer other than that portion into a silicon oxide film by thermal oxidation.

In the case of a MIS type semiconductor device having a gate insulating film on one surface of a semiconductor substrate and a gate electrode layer made of a single crystal silicon layer on the gate insulating film,
An antioxidant film is coated on a portion of the single crystal silicon layer which is to be the gate electrode layer on one surface of the I-substrate, and the single crystal silicon layer other than the portion is formed into a silicon oxide film by thermal oxidation.

By taking the above measures and converting the polycrystalline silicon layer or the single crystal layer other than the part to be the gate electrode layer into a silicon oxide film by thermal oxidation, the thermal oxide film can be formed without using a CVD insulating film. It can be used as an insulating film with wiring. In particular, it is assumed that the oxidation prevention film is a silicon nitride film. The silicon nitride film has a function as an antioxidant film and can be formed by a plasma CVD method or the like.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 and FIG. 2 are cross-sectional views showing the main steps in the order of steps for explaining the method for manufacturing the first MOSFET according to the present invention. Hereinafter, description will be made with reference to FIG.

The (100) plane is the main surface and the specific resistance is 10Ω.
A p-type wafer 41 having a thickness of 500 μm and a thickness of 500 μm is cleaned by pretreatment, and then thermally oxidized to form a thin oxide film 43 having a thickness of about 0.07 μm on the surface. After depositing a silicon layer 44 of 0.5 μm,
Phosphorus ions 56 are implanted into the polycrystalline silicon layer 44 (FIG. 1A).

Subsequently, a silicon nitride film 55 is formed on the polycrystalline silicon layer 44 by a plasma CVD method to a thickness of 0.15 μm.
It is deposited [FIG. Next, a photoresist is applied, and a pattern is formed by processes such as exposure and development using a photomask. The silicon nitride film 55, the polycrystalline silicon layer 44, and the oxide film 43 on the p-type wafer 41 are selectively formed. An opening 45 is provided by etching [FIG.

After the photoresist is stripped, phosphorus ions are implanted through the opening 45 and heat-treated to form an n-source region 46 and an n-drain region 47 in a self-aligned manner (FIG. 2D). The dose of phosphorus ions is 1 × 10 ¹⁶ /
cm ² and the diffusion depth is 0.25 μm. At this time, the silicon nitride film 55a on the polycrystalline silicon layer 44a on the surface exposed portion 41a of the p-type wafer 41 sandwiched between the n source region 46 and the n drain region 47 is left, and the other polycrystalline silicon layers The silicon nitride film on 44b may be removed, and phosphorus ions may be implanted there. The polycrystalline silicon layers 44a and 44b become 10 ²⁰ to 10 by heat treatment.
The impurity concentration becomes ²¹ cm ^-3 , and both have sufficient conductivity.

By thermal oxidation, a portion of the polycrystalline silicon layer 44b where there is no silicon nitride film 55 is converted into a thermal oxide film 43b (FIG. 4E). At this time, an oxide film is also formed on the exposed surfaces of the n source region 46 and the n drain region 47. A contact hole 49 for making an electrical connection to a necessary portion of the oxide film 43b using a photolithography technique.
[FIG. 2 (a)].

After an Al alloy film 50 is deposited on the entire surface by sputtering, the source electrode 51 in contact with the n source region 46, the drain electrode 52 and the n source region 4 in contact with the n drain region 47 are formed by photolithography.
A gate electrode 53 is formed in contact with the polycrystalline silicon layer 44a on the surface exposed portion 41a of the p-type wafer 41 sandwiched between the gate electrode 53 and the n drain region 47, and a wiring 54 is formed therefrom [FIG. . Oxide film 4 on surface exposed portion 41a
3a denotes a gate oxide film and a polycrystalline silicon layer 44 thereon.
a becomes a gate electrode layer.

Although not shown in the figure, a nitride film for protecting the surface was deposited by a plasma CVD method, and only an electrode pad portion for taking out an external terminal was exposed to evaluate MOS characteristics. The operation of this MOSFET is similar to that of a conventional MOSFET.
Similarly to the above, the application of the positive voltage to the gate electrode 53 causes conduction between the source electrode 51 and the drain electrode 52, and a stable MOS operation with the threshold voltage V _TH was confirmed.

As described above, according to the production method of the present invention,
The insulation between the p-type wafer 41 and the metal wiring 54 is provided by a thermal oxide film, and there is no problem of reduced withstand voltage or poor reliability due to a CVD insulating film as in a conventional MOS type semiconductor device, and a high withstand voltage. Thus, a highly reliable MOS semiconductor device is obtained. It can be easily implemented without any particularly difficult steps as compared with the prior art.

FIGS. 3 and 4 show an n-channel MOSFET according to the manufacturing method of the present invention using an SOI wafer.
FIG. 6 is a cross-sectional view of a main step shown in the order of steps. Hereinafter, description will be made with reference to FIG. Oxygen ions 77 are implanted into one surface of a p-type wafer 61 having a specific resistance of 3 Ω · cm and a thickness of 500 μm with the (100) plane as a main surface [FIG. The conditions for the implantation were an acceleration voltage of 130 keV and a dose of 2 × 10
¹⁷ / cm ² .

This wafer p-type 61 is subjected to a heat treatment at 1330 ° C. for 6 hours to obtain a SO having an embedded oxide film 63.
The wafer is referred to as an I wafer [FIG. The thickness of the buried oxide film 63 is 50 nm and the thickness of the SOI layer 64 is 200 nm.
It is. Next, boron ions 7 are deposited on the surface of the SOI layer 64.
After the implantation of No. 8, a silicon nitride film 75 is deposited thereon by 0.15 μm by plasma CVD [FIG.

Next, a photoresist is applied,
Form a pattern by exposure, development, etc. using a mask
And the silicon nitride film 75, the SOI layer 64 and the buried
The oxide film 63 is selectively etched to form a buried oxide film.
An opening 65 is provided to reach the substrate portion 62 below the 63.
Figure (d)]. After removing the photoresist, the silicon nitride
Of phosphorus ions through the opening 65 while leaving the phosphor film 75
Is performed, and heat treatment is performed.
The formation region 67 is formed in a self-aligned manner [FIG. phosphorus
The ion dose is 1 × 10 ¹⁶/ Cm^Two, The diffusion depth is
0.25 μm. SOI layers 64a, 6 by heat treatment
4b is 10²⁰-10^{twenty one}cm^-3Impurity concentration
Will have sufficient conductivity.

The silicon nitride film other than the silicon nitride film 75a on the surface exposed portion 62a of the substrate portion 62 sandwiched between the n source region 66 and the n drain region 67 was removed, and the silicon nitride film was removed by thermal oxidation. Part of SOI layer 6
4b is changed to an oxide film 63b [FIG. 4 (a)]. At this time,
An oxide film is also formed on the exposed surfaces of the n source region 66 and the n drain region 67 and on the back surface of the substrate portion 62.

The oxide film 6 is formed by using the photolithography technique.
A contact hole 69 for making electrical connection is formed in a necessary portion of 3b, and the remaining silicon nitride film 75a on the SOI layer 64a is removed [FIG. 4 (b)]. After depositing an Al alloy film 70 over the entire surface by sputtering, the source electrode 71 in contact with the n source region 66 and the drain electrode 7 in contact with the n drain region 67 by using photolithography technology.
2 and gate electrode 7 in contact with remaining SOI layer 64a
3 and the wiring 74 from them are formed [FIG. The oxide film 63a on the surface exposed portion 61a serves as a gate oxide film, and the SOI layer 64a thereon serves as a gate electrode layer.

Although not shown, a nitride film for protecting the surface was deposited by plasma CVD, and only the electrode pads for taking out external terminals were exposed to evaluate the MOS characteristics. The operation of this MOSFET is similar to that of a conventional MOSFET.
Similarly to the above, the application of a positive voltage to the gate electrode 30 causes conduction between the source electrode 31 and the drain electrode 32, and a stable MOS operation with the threshold voltage V _TH was confirmed.

According to the manufacturing method of the present invention, the p-type wafer 4
1 and metal wiring is provided by a thermal oxide film.
To form a CVD insulating film like a conventional MOS type semiconductor device.
There is no problem of reduced withstand voltage and poor reliability due to
A high-voltage, high-reliability MOS semiconductor device is obtained. And this
In the example, a gate oxide film is formed inside a semiconductor substrate
Therefore, it has a clean interface without the influence of natural oxide film etc.
Further, a thin gate oxide film having a uniform thickness can be realized. Only
Also allows single crystallization of the gate electrode, and the gate electrode layer
Processed from the single crystal silicon SOI layer 64
10 by ion implantation of phosphorus ^-FourΩcm compared with conventional
Then about one tenth of the resistance has been reduced. To the gate electrode
Signal delay time is almost proportional to the resistance of the gate electrode.
Therefore, by reducing such resistance, the signal delay time
It can be shortened and the operating speed can be increased. Conversely, signal delay time
The size of the gate electrode layer by an order of magnitude if
It can be small.

Of course, the SOI wafer may be manufactured by bonding. FIG. 5 is a sectional view of a main part of a vertical n-channel MOSFET according to the second manufacturing method of the present invention, in which a double diffusion region is required below a buried oxide film. Power MOSFET and IGBT
When a diffusion layer corresponding to the base region is required in addition to the source and drain regions as in (insulated gate bipolar transistor), such a diffusion region is required below the buried oxide film.

The buried oxide film 83a on the substrate portion 82 of the SOI wafer 81 serves as a gate oxide film, and the SOI layer 84, which is single crystal silicon thereon, serves as a gate electrode layer, as shown in FIG. Same as, but with substrate portion 82
Is an n-type, and a p-base region 99 and an n-source region 86 are formed in the surface layer thereof by ion implantation of boron and phosphorus and heat treatment using the gate electrode layer as one mask end. N ⁺ drain region 87 is formed on the surface of substrate portion 82 opposite to n source region 86. And
A source electrode 91, a drain electrode 92, and a gate electrode 93 are provided in contact with the n source region 86, the n ⁺ drain region 87, and the SOI layer 84, which is a gate electrode layer, respectively. Reference numeral 94 denotes an extended portion or a wiring portion of the source electrode 91.

The vertical power MOSFET shown in FIG. 5 is different from the manufacturing method shown in FIG. 1, 2 or 3 or 4 in that the conductivity type of the silicon substrate is changed and a patterned insulating film, polycrystalline silicon layer, single crystal silicon layer is further formed. P-type with
It is easily understood that the semiconductor device can be manufactured by performing the n-type impurity introduction and the heat treatment twice. The operation of the power MOSFET is such that conduction between the drain electrode 92 and the source electrode 91 is achieved by applying a positive voltage to the gate electrode 93. That is, in this power MOSFET, a current flows vertically from the bottom to the top in the drawing.

Also in this example, the insulation between the p-type wafer 81 and the metal wiring is provided by the thermal oxide film 83b, and the breakdown voltage and reliability are deteriorated due to the CVD insulating film as in the conventional MOS type semiconductor device. Thus, a MOS type semiconductor device having a high breakdown voltage and a high reliability can be obtained without the problem described above. In addition, as in the examples of FIGS. 3 and 4, the gate oxide film is a buried oxide film 83 formed inside the silicon substrate, the interface is kept extremely clean, and a thin gate oxide film having a uniform thickness can be formed. And
Since the gate electrode layer is made of the single-crystal SOI layer 84, high-concentration doping of impurities is possible, and a reduction in resistance of the gate electrode, which cannot be obtained with a conventional polycrystalline silicon film, can be realized.

Here, the n-channel type MOSFE
Although only examples of T and power MOSFET have been described, MOSF
The same applies to an IC integrated with ET, and it is apparent that CMOS can be easily realized by replacing the base diffusion region formation in the power MOSFET with the well region formation. The same applies to the IGBT.

Further, in the embodiments of the present invention, only an example in which the gate insulating film is an oxide film has been described. However, it is easy to form an MIS type device using a silicon nitride film as the gate insulating film. Can be inferred.

[0043]

As described above, according to the present invention, an antioxidant film is coated on a portion of a polycrystalline silicon layer or a monocrystalline silicon layer which is to be a gate electrode layer, and a polycrystalline silicon layer other than that portion is formed. By forming the single crystal silicon layer into a silicon oxide film by thermal oxidation, the insulating film with the metal wiring becomes a thermal oxide film, and a high breakdown voltage and high reliability MIS semiconductor device can be obtained. The problem caused by the CVD insulating film such as a semiconductor device is eliminated.

The present invention can be applied to a MIS type integrated circuit, and the same effects can be obtained, which contributes to a higher breakdown voltage and higher reliability of the MIS type integrated circuit.

[Brief description of the drawings]

FIGS. 1A to 1E show the first MOSFE of the present invention.
Sectional drawing for every main process for explaining the manufacturing method of T

FIGS. 2A and 2B are cross-sectional views showing main steps for explaining the method for manufacturing the first MOSFET of the present invention following FIG. 1E;

3 (a) to 3 (e) show a second MOSFET according to the present invention.
Sectional drawing for every main process for explaining the manufacturing method of T

FIGS. 4 (a) to 4 (c) are cross-sectional views showing main steps for explaining the method for manufacturing the second MOSFET of the present invention following FIG. 3 (e).

FIG. 5 is a sectional view of another MOSFET according to the manufacturing method of the present invention.

6 (a) to 6 (e) are cross-sectional views showing main steps for explaining a conventional method for manufacturing a MOSFET.

FIGS. 7A to 7E show another conventional MOSFET.
Sectional view for each main process for explaining a method of manufacturing

[Explanation of symbols]

1, 41, 61 P-type wafer 1a, 22a, 41a, 62a Surface exposed portion 3, 3a, 43, 43a Oxide film 4, 4a, 44, 44a, 44b Polycrystalline silicon layer 5, 25, 45, 65, 85 Opening Part 6, 26, 46, 66, 86 n Source region 7, 27, 47, 67 n Drain region 8, 28, 68 PSG film 9, 29, 49, 69 Contact hole 10, 30, 50, 70 Al alloy film 11 , 31, 51, 71, 91 Source electrode 12, 32, 52, 72, 92 Drain electrode 13, 33, 53, 73, 93 Gate electrode 14, 34, 54, 74, 94 Metal wiring 21, 81 SOI wafer 22, 62, 82 Substrate portion 23, 23a, 63, 63a, 83a Buried oxide film 24, 24a, 64, 64a, 64b, 84a SOI
Layers 38, 78 Boron ions 43b, 63b, 83b Thermal oxide films 55, 55a, 75, 75a Silicon nitride film 56 Phosphorus ions 77 Oxygen ions 87 n ⁺ Drain region 99 p Base region

Claims (3)

[Claims] 1. A method for manufacturing a MIS type semiconductor device having a gate insulating film on a surface of a semiconductor substrate and a gate electrode layer made of a polycrystalline silicon layer on the gate insulating film,
A step of sequentially forming an insulating film and a polycrystalline silicon layer on the surface of the semiconductor substrate, and covering the portion of the insulating film and the polycrystalline silicon layer which is to be the gate electrode layer with an antioxidant film on the polycrystalline silicon layer; A method for manufacturing a MIS type semiconductor device, comprising a step of converting a polycrystalline silicon layer other than the portion to a silicon oxide film by thermal oxidation. 2. A method of manufacturing a MIS semiconductor device having a gate insulating film on one surface of a semiconductor substrate and a gate electrode layer made of a single crystal silicon layer on the gate insulating film, the method comprising the steps of: A method of manufacturing a MIS type semiconductor device, comprising: coating an antioxidant film on a portion of a single crystal silicon layer to be a gate electrode layer; and forming a silicon oxide film by thermal oxidation on the other portion of the single crystal silicon layer. . 3. The method according to claim 1, wherein the oxidation preventing film is a silicon nitride film.