JPH10207823A - Dma circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DMA circuit of particlable level which is made small- sized in circuit scale as far as possible and able to perform a high-speed process even if the data bus width increases. SOLUTION: Input data is inputted to a clock-synchronous input buffer 1 first. Then a single rotary barrel shifter 2 which holds data of the bus width makes a shift in byte units according to the difference between the read address of transfer source and the write address of a transfer destination and writes the result in succeeding-stage buffers 30 to 34 for successive transfer. The shift quantity is determined by a data position in the data bus width specified as the address of the transfer destination and in this case, the data transfer is burst transfer of up to four times, so the buffers 30 , and 34 among 30 to 34 are used to hold effective data in relation with the shift quantity; and these buffers are selected by selectors 4 and 5 to output the data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a DMA (Direct).
More specifically, the present invention relates to a DMA circuit having a shift function required when performing continuous data transfer with a data bus width such as image data transfer.

[0002]

2. Description of the Related Art Conventionally, for example, rectangular transfer of image data, etc.
In the case of using a transfer method determined by the bus width of the data bus, the transfer of data in which the addresses of the transfer source and the transfer destination are deviated from the boundary of a unit block of data according to the transfer method requires a plurality of transfers of data within the boundary. I went and responded. As a method to solve this, Japanese Patent Publication No. 7-6634
No. 9 has proposed a shifter circuit. As this shifter circuit shown in FIG. 25, two buffers A1 _'0, the buffer B1' reads alternately data to _1,
The output of each buffer is the data bus width (n bits)
Twice the rotational barrel shifter A2 of _'0, B2' ₁ had have valid data by selecting shifter A shift to the selector 4 'by (n bits each), the B. This situation is shown in FIGS. 26 and 27, where a state change from shifting of input data to output data is described. FIG. 26 shows the transition of the operation states of shifters A and B at the time of left shift, and FIG. For transferring continuous data, Japanese Patent Laid-Open No. 63-2444
No. 84 has proposed a circuit. As shown in FIG. 28 in this circuit it has been once read buffer 1 _{'0-1' 3} have enough for storing input data I (4 2 → example of the prior art) added.

[0003]

[Problems to be solved by the invention]
In the prior art disclosed in Japanese Patent No. 6349, the use of a 128-bit rotating barrel shift is required at present when the data bus width has become mainstream of 64 bits, which causes an increase in circuit scale. Japanese Patent Application Laid-Open No. 63-244484 is on a conceptual level and does not disclose a specific circuit configuration. SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems of the prior art, and has been developed to reduce the size of the circuit as much as possible and realize high-speed processing even if the data bus width is increased in the DMA circuit. It is an object of the present invention to provide a circuit of a generalization level.

[0004]

According to a first aspect of the present invention, there is provided a DMA circuit for continuously transmitting data transmitted at a predetermined data bus width to a destination of a predetermined address, wherein the input data is transmitted at a predetermined bus width. A single rotary barrel shifter that shifts the held data by a data unit whose transfer destination address can be specified, and the output data of the rotary barrel shifter is sequentially written, and the stored data of the bus width is transferred by a burst transfer method. , A predetermined number of transfer buffers prepared for continuous transfer, a transfer buffer selection circuit for outputting data of a buffer selected from the predetermined number of transfer buffers for storing transfer data, and data transfer by DMA A control circuit that performs the control of
The operation of the rotary barrel shifter, the transfer buffer, and the transfer buffer selection circuit is controlled according to the transfer destination data position specified by the address.

According to a second aspect of the present invention, in the first aspect of the present invention, the control circuit matches the data position after the shift by the rotary barrel shifter with the data position of the addressed transfer destination in a unit of a bus width. The operation control is performed as described above.

According to a third aspect of the present invention, in the first aspect of the present invention, the control circuit determines a data position of valid data in data input with a predetermined bus width in a leading buffer of the predetermined number of transfer buffers. The operation control is performed so as to store the data as transfer data.

According to a fourth aspect of the present invention, in the first aspect, a predetermined number of the transfer buffers are prepared for a plurality of burst transfers, and the control means reads one of the burst transfers. And the other burst transfer is operated as a write.

[0008]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing an example of an embodiment of a DMA circuit according to the present invention. FIGS. 4 and 5 show registers used in a DMA circuit according to an embodiment of the present invention and specifications related to the registers. In FIG. 1, input data is first taken into a clock synchronous input buffer 1. Thereafter, the shift in bytes by the difference between the write address source and destination of the read address by the rotation barrel shifter 2, and writes the result to the next stage of the continuous transfer buffers 3 _{0-3 4.}

[0009] indicates wiring between the rotating barrel shifter 2 and the continuous transfer buffer 3 _{0-3 4,} and an example of a detailed circuit configuration of the continuous transfer buffer 2, 3. In this example, the address bus width is 32 bits, the continuous transfer is a burst transfer method, the addresses of the transfer source and the transfer destination coincide with byte boundaries, and the maximum number of burst transfers is 4.
Times, the data bus width is 64 bits (double word: D
W) The transfer partner is a synchronous DRAM (hereinafter abbreviated as "SDRAM") type memory.

In the DMA circuit of this embodiment, the control registers used for realization are: 1. Source (read data) address (coincides with byte boundary) → Transfer source address register: ARrs 2. Transfer destination (write data) address (coincides with byte boundary) → transfer destination address register: ARws Transfer byte number (less than burst length) → Transfer byte number register: Consider a case where BNUM is provided. FIG. 4 (part 1) and FIG. 5 (part 2) summarize the creation method and specifications of the registers used in the present embodiment including the control registers under the above conditions.
Note that abbreviations used in timing charts and flow charts described later showing the operation of the circuit indicate the same as those in FIGS. 4 and 5.

4 and 5, a transfer source address register (ARrs): a register for setting an address (transfer source address) at which data to be transferred is stored a transfer destination address register (ARws): a destination address of the transfer data Register for setting address (transfer destination address) Transfer byte number register (BNUM): Register for setting data amount (byte number) of data to be transferred Read transfer start address register (ARrs0): Initial read transfer (DMA from transfer source) In this embodiment, since the data bus is 64 bits, the lower 3 bits of the start address are 000b. Read transfer continuation address register (ARrs1): register for displaying the address of the second and subsequent read transfers In this embodiment, the data transfer is a maximum of four burst transfers, and the second and subsequent addresses are the previous address + 3.
It is 2 bytes. Therefore, the lower 5 bits become 0.
Normally, the value of ARrs is loaded into a counter, and ARrs0 is loaded.
And ARrs1. A for the second and subsequent transfers
Rrs1 is obtained by incrementing the value of this counter. Read transfer count register (TrNUM): Register for indicating the remaining transfer count Since read transfer is performed in units of 64 bits (8 bytes), if the lower 3 bits of ARrs are not 000b, the transfer byte count must be adjusted Occurs. The value after the adjustment is TrNUM0. If the lower 3 bits of TrNUM0 are not 000b, one transfer for that is necessary. Therefore, the upper 14 bits obtained by rounding up the lower 3 bits of TrNUM0 become TrNUM. The number of transfers is checked by checking whether or not TrNUM0-1 is 0 each time the transfer is completed. Read continuous transfer count register (SrNUM): a register used to update the address of read transfer The read transfer address must be incremented for each 32 byte (four burst transfer length) boundary.
This register is used to check the timing of the increment. Therefore, at the time of the first transfer, ARrs [4: 3] is counter-loaded and incremented every transfer to measure the timing. Shift amount register (SIFT): Indicates the magnitude of the shift. The calculation method is as shown in FIG. By giving this value to the shifter in FIG. 2, the data is shifted as shown in FIGS. Buffer Position Register (BPOS): Register indicating the position of an effective continuous transfer buffer The present invention uses a plurality of 64-bit (8-byte) continuous transfer buffers as shown in FIGS. This register indicates which buffers should be enabled. The calculation method is as shown in FIG. Valid data position register (DPOS): indicates which byte of data in the continuous transfer buffer is valid.
This is an 8-bit register, which is set as shown in FIG. 5 by the value of SIFT. Write transfer buffer selector (BSEL): Designates a continuous transfer buffer used at the time of write transfer. Except in the case of Example 2 (described later) of the present invention, SwNUM is used instead. Write transfer start address register (ARws0): Register for displaying the address of the first write transfer (transfer from DMA to transfer destination) Write transfer continuation address register (ARws1): Register for displaying the address of the second and subsequent write transfers Transfer count register (TwNUM): a register for displaying the remaining transfer count of the write transfer Write continuous transfer count register (SwNUM): a register for measuring the timing of updating the address of the write transfer The registers related to the write transfer are read The function is the same as that of the register.

FIG. 6 is an operation timing chart of the circuit according to the embodiment of the present invention shown in FIGS. In FIG. 6, a control signal to the SDRAM and a method of creating an address and data will be described with reference to the registers of FIGS. 4 and 5. In FIG. 6, CLK is a clock signal for operating the SDRAM. / CS is a control of the SDRAM. Signals (chip select) / RAS: SDRAM control signal (row address strobe) / CAS: SDRAM control signal (column address strobe) / WE: SDRAM control signal (write enable) DQM: data mask signal A0-10 and A11: Address bus of SDRAM DQ: Data bus of SDRAM Others are the register values described with reference to FIGS.
These all change in synchronization with CLK. Also, “4
The "select signal of the to1 selector" and the "select signal of the 2to1 selector" refer to the selector of FIG.

After writing to the control register and obtaining the right to use the data bus, the control circuit executes a read instruction to the memory. At this time, the control as shown in the flowchart of FIG. 7 is performed in consideration of the transfer source address and the number of transfer bytes.
FIG. 7 is a flowchart of the data read unit of the circuit.
2 is a flowchart showing a control method for reading data from a DRAM to an input buffer 1 of FIG. FIG.
Medium, ARrs0, ARrs1, TrNUM, SrNUM
Is initialized, and their values are updated each time transfer is completed. In order to actually control the SDRAM, other control signals must be created, but these are omitted because they depart from the scope of the present invention. For the control signal, the timing charts of FIGS. 6, 23 and 24 may be referred to. Note that the change of the signal is synchronized with CLK. The data read from the memory by this control is sequentially taken into the input buffer 1 by the required number of double words.

On the other hand, the control circuit controls the inside of the DMA circuit as shown in the flowchart of FIG. Figure 8 is for Example 1, in the circuit of FIG. 1 is a flow chart illustrating a method for controlling the write signal due to the continuous transfer buffer controller to continuously transfer buffer 3 _{0-3 4.} Initial settings of SIFT, DPOS, and BPOS are performed, and the value of BPOS is updated each time data is input from the input buffer, and a write signal is created using these values. FIG. 9 shows a transition of the operation state at the time of right shift in the present embodiment, and FIG. 10 shows how to make a WE corresponding to the operation. FIG. 11 shows a transition of the operation state at the time of left shift, and W corresponding to the operation.
How to make E is shown in FIG. As shown in FIGS. 9 to 12, the write signal is a byte in which the DPOS is 1 in the continuous transfer buffer selected by decoding the BPOS and a DPOS is 0 in the continuous transfer buffer selected by decoding the BPOS + 1. Asserted for this byte. The write signal referred to here is the WE signal in FIGS. As a result of such control, the data fetched into the input buffer by the operation shown in FIGS. 9 to 12 is written into the continuous transfer buffer, and the data in the continuous transfer buffer shown in FIG. As can be seen, the transfer destination address (ARwr
(4: 0)), the input data is shifted.

FIG. 13 is a schematic diagram of a circuit according to this flowchart. In FIG. 13, the buffer position register BPOS and the valid data position register DPOS are initialized at the start of the DMA operation by the method shown in FIGS. Thus, the initial value of BPOS is calculated and loaded into the counter. The output of this counter is decoded by a decoder, and an AND with the DPOS calculated in advance is calculated to create a WE. The counter counts up with the EN signal every time data is written to the input buffer. At the start of operation, the initial value of BPOS is
When the decoder asserts 4 (BPOS [2: 0]
Is 100b), 000b is loaded. DPO
S is unchanged during operation. WE is asserted by a clock that detects data input to the input buffer, and the counter (FIG. 13) that creates BPOS also changes at this timing. Therefore, the change will be synchronous with CLK.

FIGS. 14 and 15 are flowcharts (parts 1 and 2) of the data write section of the DMA circuit according to the first embodiment of the present invention.
9 is a flowchart illustrating a control method for writing data in parallel with a write instruction to an AM memory. As a result, data is written to the memory at the target address. ARws0, ARws1, TwNUM, SwNU
M is initialized and their values are updated each time transfer is completed. In the first and last transfers, a write mask signal (DQM) is asserted as necessary. As shown in FIGS. 13 and 14, the mask signal is created by using ARws [2: 0] at the time of the first transfer so that the byte before the start position is masked. In the case of, a mask is created using BNUM and ARws [2: 0] so as to mask the last byte of data. The transfer is performed while checking TwNUM and SwNUM, the address is updated every time SwNUM becomes 3, and the transfer is performed until TwNUM becomes 0. Actually S
In order to control the DRAM, other control signals must be generated, but these are omitted because they are out of the scope of the present invention. The control signal is shown in FIG.
See timing chart. The 4to1 selector at the output stage is a double word selector in which the value of the continuous transfer buffer 0 (or 4) is selected when the select signal is “0” and the value of the buffer 3 is selected when the select signal is “3”.
4to1 which is the same as the maximum burst transfer number of 4 considering efficiency
Selector.

However, in this control method, if the transfer destination address is shifted from the transfer boundary determined by the bus width of the data bus, transfer of a sufficient number of bits may not be possible. That is, ARws (4: 3) is 11
In case of b, at most 2 double words (16 bytes)
The data can be stored in the continuous transfer buffer only up to this point.
To solve this, a method of increasing the number of stages of the continuous transfer buffer as in a circuit example to be described later and a method of changing the control method can be considered. Here, in order to avoid repetition of the description, an embodiment of the circuit when the control method is changed will be described.

After writing to the control register and obtaining the right to use the data bus, the control circuit executes a read command to the memory. At this time, in consideration of the transfer source address and the number of transfer bytes, the control as shown in the flowchart of FIG. FIG. 16 is a flowchart of the continuous transfer buffer control unit of the circuit of the second embodiment, and is a flowchart showing a method of controlling a write signal to the continuous transfer buffer of FIG. Initial settings of SIFT, DPOS, and BPOS are performed, the value of BPOS is updated each time data is input from the input buffer, and a write signal is created using these values. The difference from FIG. 8 which is the flowchart of the first embodiment is that from which position in the continuous transfer buffer data writing is started. In the case of FIG. 8,
The BPOS is determined from the value of ARrs [2: 0] and the value of ARws [4: 0] so that the byte position of valid data is aligned with the byte position of the transfer destination. Focusing on the effective use of the buffer, the BPOS is determined so that valid data is always written from the continuous transfer buffer 0. This is the difference in the BPOS setting method in the initial setting, and is the difference between FIG. 8 and this embodiment. As a result of the control circuit performing control as shown in the flowchart of FIG. 16 on the inside of the DMA circuit, valid data is written from the continuous transfer buffer 0 regardless of ARws (4: 3).

FIG. 17 is a flowchart (part 1) of the data write section of the circuit according to the second embodiment of the present invention, and FIG.
9 shows a flowchart (part 2) of the data write section of the circuit according to the second embodiment of the present invention. 17 and 18 are flowcharts showing a control method for writing data from the continuous transfer buffer of FIG. 1 to the SDRAM. ARws
Initial settings of 0, ARws1, TwNUM, SwNUM, and BSEL are performed, and the values are updated each time transfer is completed.
The difference from the flowcharts of FIGS. 14 and 15 of the first embodiment is that the data at which position in the continuous transfer buffer is selected and written to the memory. In the case of FIG. 14, since the transfer destination address ARws [4: 3] and the continuous transfer buffer in which valid data exists are present, the SwNUM using the value of ARws [4: 3] as an initial value.
Is used to generate the selector control signal and the address change timing. However, in this case, since the valid data is written from the continuous transfer buffer 0, the selector control signal BSEL starts from 00b. The output of the counter starting from ARws [4: 3] is used for the address change timing SwNUM as in FIGS. For others, see FIGS.
Is the same as Since the method of writing data to the continuous transfer buffer is different from that in the first embodiment, control is performed on the 4to1 selector as shown in the flowcharts of FIGS. As a result, data is written to the memory at the target address. By changing the control in this way, no matter where the forwarding address is,
Transfer of at least four double words (32 bytes) can be guaranteed.

However, the circuits of the above embodiments can transfer only 5 double words (40 bytes) at the maximum. In this case, in order to perform a rectangular transfer for a large area, the transfer must be performed a plurality of times. Therefore, as shown in FIG. 19, the number of continuous transfer buffers is increased to eight, and an output buffer is provided to cope with data reading and storing. In FIG. 19, the output buffer is one flip-flop for simplicity of description, but the amount of data that can be read and stored can be freely changed by introducing a FIFO type buffer here.

The actual control is performed according to the first embodiment.
Very close to the case. First, the reading of data from the memory to the input buffer is controlled in accordance with a flowchart as shown in FIG. 7, as in the first embodiment. FIG. 20 is a flowchart showing a method of controlling a write signal to the continuous transfer buffer of the continuous transfer buffer control unit of the circuit according to the third embodiment (FIG. 19) of the present invention. Initialize SIFT, DPOS, and BPOS. Each time data is input from the input buffer, the BPO
The value of S is updated, and a write signal is created using these values. The difference from FIG. 8 which is the flowchart of the first embodiment is that the continuous transfer buffer
9) is performed.

In FIG. 20, the BPOS is counted up every time data is written from the input buffer, and data is transferred to the output stage buffer under the following conditions. 1: When reading of data into the input buffer is completed. 2: Writing of valid data to the continuous transfer buffer is 6
When crossing 4 bit (8 byte) boundaries (BPOS
[1: 0] = 11b. However, as shown by the condition 1 in the drawing, the writing of only the first invalid data is excluded).
At this time, the select signal of the column selector (FIG. 19) is asserted using BPOS [2] so that the side on which writing has been completed is selected. Further, since the number of continuous transfer buffers is increased to eight, ARws [4: 0] <A
The value of BPOS in the case of Rrs2 [4: 0] is 111b. Writing of data to the continuous transfer buffer is performed according to this flowchart. That is, the data is stored in cooperation with the output buffer by using two continuous transfer buffers as four sets. When the writing of the data to the buffer 3 (or the buffer 7) is completed, the data for one of the continuous transfer buffers is moved to the output buffer.
Prepare for data transfer from the next input buffer.

FIG. 21 is a flowchart (part 1) of the data write section of the circuit of the present embodiment, and FIG. 22 is a flowchart (part 2) of the data write section of the circuit of the present embodiment. 19 is a flowchart showing a control method for writing data from the output buffer of FIG. 19 to the SDRAM. ARws0, ARws
1, TwNUM, and SwNUM are initialized, and their values are updated each time transfer is completed. The difference from the flowcharts of FIGS. 14 and 15 of the first embodiment is that
Since the to1 selector does not exist in FIG. 19, its control is simply lost. In order to actually control the SDRAM, other control signals must be created, but these are omitted from the scope of the present invention. For the control signal, see the timing charts of FIGS. FIG. 23 is an operation timing chart (part 1) of the circuit of this embodiment, and FIG. 24 is an operation timing chart (part 2) of the circuit of this embodiment. These figures are basically the same as FIG. is there. The difference from FIG. 6 is that the “2to1 selector select signal” is eliminated,
The point is that “selection signal of column selector”, “WE to output stage buffer”, and “data in output stage buffer” are increased. These are due to structural differences as shown in FIG. 1 and FIG.

As described above, writing to the memory is performed as shown in FIG.
This is performed as shown in the flowchart of FIG. The selection of the 4to1 selector at the output stage becomes the data stored in the buffer 3 (or the buffer 7), and at the same time when the transfer of the data to the memory is completed, the control unit updates the data in the output buffer. In the case of the circuit of FIG. 19, data is read from the continuous transfer buffer by switching the preceding column selector. In this case, when a FIFO type buffer is used, between the continuous transfer buffer and the output stage,
Although more complicated control is required, this control method is different from the main subject of the present invention, and the description is omitted. By using the circuit of the third embodiment and determining the size of the output buffer so as to correspond to the required data length, rectangular transfer for a large area can be completed in one transfer. .

[0025]

【The invention's effect】

According to the first aspect of the present invention, a single rotary barrel shifter for holding data of a data bus width, a number of buffers and buffer selection circuits corresponding to burst transfer, and control for controlling the circuit means by a data position of an addressed transfer destination. By providing a circuit, it is possible to reduce the increase in the number of circuits due to the effect of the bus width, which is becoming longer, and to reduce the size of the circuit corresponding to bit-by-bit shifts. When performing continuous data transfer such as burst transfer for data that deviates from the transfer boundary determined by the bus width of the bus, transfer by DMA can be performed efficiently. Effect of Claim 2: In addition to the effect of Claim 1, burst transfer to a transfer destination address outside the burst boundary is enabled. Effect of Claim 3: In addition to the effect of Claim 1, in addition to the address of the transfer destination, transfer with the minimum buffer capable of burst transfer is guaranteed regardless of the address of the transfer destination, and the continuous transfer buffer is effectively used. be able to. Effect of Claim 4: In addition to the effects of Claims 1 to 3, one of read and write can be performed continuously when transferring data longer than the burst length, and rectangular transfer of a large range is performed once. Can be performed with the transfer of
Processing speeds up.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of an embodiment of a DMA circuit according to the present invention.

FIG. 2 is a diagram showing a detailed circuit configuration of a shifter and a continuous transfer buffer of FIG. 1;

FIG. 3 is a diagram illustrating an example of a configuration of the continuous transfer buffer of FIG. 2 using a DFF with EN.

FIG. 4 is a diagram (part 1) showing a register used in an embodiment of the DMA circuit according to the present invention and specifications relating to the register;

FIG. 5 is a diagram (part 2) showing a register used in the embodiment of the DMA circuit according to the present invention and specifications relating to the register;

FIG. 6 is an operation timing chart of the circuit according to the embodiment of the present invention.

FIG. 7 is a flowchart showing a control operation for reading data from an SDRAM to an input buffer.

FIG. 8 is a flowchart illustrating a method for controlling a write signal to a continuous transfer buffer according to the first embodiment of the present invention.

FIG. 9 is a diagram illustrating a transition of an operation state at the time of a right shift according to the first embodiment of the present invention.

FIG. 10 is a diagram for explaining how to create a WE corresponding to the operation in FIG. 9;

FIG. 11 is a diagram illustrating a transition of an operation state at the time of a left shift according to the first embodiment of the present invention.

FIG. 12 is a diagram for explaining how to create a WE corresponding to the operation in FIG. 10;

FIG. 13 shows the WE of the continuous transfer buffer shown in FIGS. 10 and 12;
FIG. 3 is a diagram schematically showing a circuit for generating the data.

FIG. 14 is a flowchart (part 1) of a data write unit of the circuit according to the embodiment of the present invention.

FIG. 15 is a flowchart (part 2) of the data write section of the circuit according to the embodiment of the present invention.

FIG. 16 is a flowchart of a continuous transfer buffer control unit of the circuit according to the second embodiment of the present invention.

FIG. 17 is a flowchart (part 1) of the data write unit of the circuit according to the second embodiment of the present invention.

FIG. 18 is a flowchart (part 2) of the data write unit of the circuit according to the second embodiment of the present invention.

FIG. 19 is a diagram showing a third embodiment of the present invention in which the number of continuous transfer buffers is eight.

FIG. 20 is a flowchart of a continuous transfer buffer control unit of the circuit according to the third embodiment of the present invention.

FIG. 21 is a flowchart (part 1) of a data write unit of the circuit according to the third embodiment of the present invention.

FIG. 22 is a flowchart (part 2) of the data write unit of the circuit according to the third embodiment of the present invention.

FIG. 23 is an operation timing chart (part 1) of the circuit according to the third embodiment (FIG. 19) of the present invention;

FIG. 24 is an operation timing chart (2) of the circuit according to the third embodiment (FIG. 19) of the present invention.

FIG. 25 is a block diagram showing an example of a conventional shifter circuit.

26 is a state transition diagram illustrating a left shift operation by the shifter circuit of FIG. 25.

FIG. 27 is a state transition diagram illustrating a right shift operation by the shifter circuit of FIG. 25.

FIG. 28 is a block diagram showing another example of a conventional shifter circuit.

[Explanation of symbols]

1 ... input buffer, 2,2 _'0, 2' ₁ ... rotating barrel shifter, 1 _{'0-1' 3,} 3,7 ... buffer, 3 _{0-3 7} ... continuous transfer buffer, 4,4 _{0-4 3} , 4 ', 4 ", 5 ... selector, 6 _{0-6 3} ... output stage buffer.

Claims (4)

[Claims] 1. A DMA circuit for continuously transmitting data transmitted with a predetermined data bus width to a transfer destination of a predetermined address, holding input data with a predetermined bus width, and storing the held data in a transfer destination address. Is a single rotating barrel shifter that shifts by a data unit that can be specified, and a predetermined number prepared for sequentially writing output data of the rotating barrel shifter and continuously transferring the stored data of the bus width by a burst transfer method. Transfer buffer, a transfer buffer selecting circuit for outputting data of a buffer selected from the predetermined number of transfer buffers for storing transfer data, and a control circuit for controlling data transfer by DMA. A circuit includes: the rotary barrel shifter; the transfer buffer; and a transfer buffer according to an addressed transfer destination data position. A DMA circuit, wherein the operation of a selection circuit is controlled. 2. The control circuit according to claim 1, wherein the control circuit controls the operation such that a data position after the shift by the rotary barrel shifter and a data position of an addressed transfer destination coincide in a unit of a bus width. 2. The DMA circuit according to claim 1, wherein: 3. The operation control according to claim 1, wherein the control circuit stores the data position of valid data in the data input with a predetermined bus width as transfer data in a first buffer of the predetermined number of transfer buffers. 2. The DMA circuit according to claim 1, wherein the DMA circuit is configured to perform the operation. 4. A method according to claim 1, wherein a predetermined number of said transfer buffers are prepared for a plurality of burst transfers, and said control means operates one of the burst transfers as a read and the other as a write. 4. The DMA circuit according to claim 1, wherein