JPH10207771A5 - - Google Patents

Info

Publication number
JPH10207771A5
JPH10207771A5 JP1997289800A JP28980097A JPH10207771A5 JP H10207771 A5 JPH10207771 A5 JP H10207771A5 JP 1997289800 A JP1997289800 A JP 1997289800A JP 28980097 A JP28980097 A JP 28980097A JP H10207771 A5 JPH10207771 A5 JP H10207771A5
Authority
JP
Japan
Prior art keywords
memory
lines
read
remaining
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP1997289800A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10207771A (ja
Filing date
Publication date
Priority claimed from US08/747,320 external-priority patent/US5974514A/en
Application filed filed Critical
Publication of JPH10207771A publication Critical patent/JPH10207771A/ja
Publication of JPH10207771A5 publication Critical patent/JPH10207771A5/ja
Withdrawn legal-status Critical Current

Links

JP9289800A 1996-11-12 1997-10-22 メモリ動作短縮方法 Withdrawn JPH10207771A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/747,320 US5974514A (en) 1996-11-12 1996-11-12 Controlling SDRAM memory by using truncated burst read-modify-write memory operations
US747,320 1996-11-12

Publications (2)

Publication Number Publication Date
JPH10207771A JPH10207771A (ja) 1998-08-07
JPH10207771A5 true JPH10207771A5 (enExample) 2005-03-10

Family

ID=25004583

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9289800A Withdrawn JPH10207771A (ja) 1996-11-12 1997-10-22 メモリ動作短縮方法

Country Status (2)

Country Link
US (1) US5974514A (enExample)
JP (1) JPH10207771A (enExample)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5991850A (en) * 1996-08-15 1999-11-23 Micron Technology, Inc. Synchronous DRAM modules including multiple clock out signals for increasing processing speed
US6415364B1 (en) * 1997-12-31 2002-07-02 Unisys Corporation High-speed memory storage unit for a multiprocessor system having integrated directory and data storage subsystems
US6247101B1 (en) * 1998-07-01 2001-06-12 Lsi Logic Corporation Tagged access synchronous bus architecture
US6038693A (en) * 1998-09-23 2000-03-14 Intel Corporation Error correction scheme for an integrated L2 cache
WO2001045101A2 (en) * 1999-12-17 2001-06-21 Thomson Licensing S.A. USAGE OF AN SDRAM AS STORAGE FOR CORRECTION AND TRACK BUFFERING IN FRONTEND ICs OF OPTICAL RECORDING OR REPRODUCTION DEVICES
US6314049B1 (en) 2000-03-30 2001-11-06 Micron Technology, Inc. Elimination of precharge operation in synchronous flash memory
JP2001290696A (ja) * 2000-04-07 2001-10-19 Minolta Co Ltd メモリ基板
US6463506B1 (en) * 2000-04-29 2002-10-08 Hewlett-Packard Company Arrangement of data within cache lines so that tags are first data received
US6728798B1 (en) * 2000-07-28 2004-04-27 Micron Technology, Inc. Synchronous flash memory with status burst output
KR100644597B1 (ko) * 2000-08-05 2006-11-10 삼성전자주식회사 버스 시스템 및 그 커맨드 전달방법
US6580659B1 (en) * 2000-08-25 2003-06-17 Micron Technology, Inc. Burst read addressing in a non-volatile memory device
US6691204B1 (en) * 2000-08-25 2004-02-10 Micron Technology, Inc. Burst write in a non-volatile memory device
US6310809B1 (en) 2000-08-25 2001-10-30 Micron Technology, Inc. Adjustable pre-charge in a memory
US6327202B1 (en) 2000-08-25 2001-12-04 Micron Technology, Inc. Bit line pre-charge in a memory
US20020135817A1 (en) * 2001-03-22 2002-09-26 Kuo-Jeng Wang Data transmission scheme for scanner
US6708258B1 (en) * 2001-06-14 2004-03-16 Cisco Technology, Inc. Computer system for eliminating memory read-modify-write operations during packet transfers
US6826113B2 (en) * 2003-03-27 2004-11-30 International Business Machines Corporation Synchronous dynamic random access memory device having memory command cancel function
US7480774B2 (en) * 2003-04-01 2009-01-20 International Business Machines Corporation Method for performing a command cancel function in a DRAM
KR100532956B1 (ko) 2003-06-28 2005-12-01 주식회사 하이닉스반도체 Ｄｄｒ ｓｄｒａｍ에서의 링잉 현상 방지 방법
KR100548563B1 (ko) 2003-06-30 2006-02-02 주식회사 하이닉스반도체 Ｄｄｒ ｓｄｒａｍ 에서의 라이트 링잉 현상을 마스크하기위한 데이타 패스 제어 장치 및 방법
KR100720260B1 (ko) * 2004-11-15 2007-05-22 주식회사 하이닉스반도체 반도체 메모리 장치의 로컬 입출력 라인 프리차지 회로
US7945840B2 (en) * 2007-02-12 2011-05-17 Micron Technology, Inc. Memory array error correction apparatus, systems, and methods
US7617354B2 (en) * 2007-03-08 2009-11-10 Qimonda North America Corp. Abbreviated burst data transfers for semiconductor memory
US7684280B2 (en) * 2007-10-22 2010-03-23 Advantest Corporation Histogram generation with banks for improved memory access performance
US8452920B1 (en) 2007-12-31 2013-05-28 Synopsys Inc. System and method for controlling a dynamic random access memory
KR20100101449A (ko) * 2009-03-09 2010-09-17 삼성전자주식회사 메모리 장치, 그것의 마스크 데이터 전송 방법 및 입력 데이터 정렬 방법
JP5752686B2 (ja) 2009-08-20 2015-07-22 ラムバス・インコーポレーテッド 原子メモリ装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5450130A (en) * 1994-03-30 1995-09-12 Radius Inc. Method and system for cell based image data compression
US5668773A (en) * 1994-12-23 1997-09-16 Micron Technology, Inc. Synchronous burst extended data out DRAM
US5640364A (en) * 1994-12-23 1997-06-17 Micron Technology, Inc. Self-enabling pulse trapping circuit
US5587961A (en) * 1996-02-16 1996-12-24 Micron Technology, Inc. Synchronous memory allowing early read command in write to read transitions

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