JPH10207694A - Digital power arithmetic unit and graphics system using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To carry out power calculation at a high speed by providing a logarithmic calculation part which outputs a logarithmic value for an input value by using a logarithm table, a multiplier which multiplies its output by a value to be raised to some power, and an exponent calculation part which outputs an exponential value for the output of the multiplier by using an exponent table. SOLUTION: The logarithmic calculation part 10 is provided with a logarithmic shift part 11 which shifts K bits to the left until they enter the input range of the logarithm table 12 obtained by reducing the input valve and outputs a 2-bit shift quantity K and a 11-bit shift result. Further, this part is provided with the reduced logarithm table 12 which outputs a value of the logarithmic function for the shift result as a 12-bit fixed decimal number and a logarithmic addition part 13 which adds K to the output of the logarithm table 12 and outputs a 15-bit fixed decimal point number. The exponent calculation part 30 is provided with an exponent subtraction part 31 which subtracts M from the input value and outputs a 3-bit subtraction quantity and a 7-bit substation result, an exponent table 32 which outputs a 6-bit fixed decimal point, and an exponent shift part 33 which shifts it to the right.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus for executing a process including a power in an operation.

[0002]

2. Description of the Related Art Conventionally, two digital numerical data X,
For the exponentiation calculation to obtain X N for ^N , see Haruhiko Okumura, published on February 25, 1991 by Technical Review,
P105-1 of "Latest encyclopedia of algorithms in C language"
06, p162-163, and p304, a logarithmic function and an exponential function are exponential series expanded or continued fraction expanded to obtain a logarithm and an exponent by a loop calculation. A method of calculating the logarithm of X, multiplying the result by N, and finally calculating the exponent of the multiplication result has been adopted.

As another method, a method has been adopted in which an address is directly generated from the two digital numerical data X and N and a power table (ROM, RAM) is referred to.

[0004]

As described above, in the prior art, in the former case, a loop calculation occurs and it is difficult to speed up the processing. In the latter case, the table input is X and N. Therefore, the gradation number of the input value of the table is the gradation number of X and N
And the capacity of the table becomes large.

It is an object of the present invention to provide a power operation device capable of performing a power calculation at high speed by referring to a table having a small capacity without using a loop calculation, and a graphics system using the same.

[0006]

A feature of the present invention is that a logarithmic calculation unit for outputting a logarithmic value for an input value X using a logarithmic table, a multiplier for multiplying the output of the logarithmic calculation unit by a value N raised to a power are provided. An exponent calculator for outputting an exponent value for the output of the multiplier using an exponent table to form a digital exponentiation device, wherein the base of the logarithm calculated by the logarithmic calculator and the index calculated by the exponent calculator are The base of the exponent is the same value.

Further, in order to further reduce the capacity of the table, according to the present invention, when the input value is not included in the input value range of the log table, an integer suitable for the input value of the logarithmic calculation unit is provided. A logarithmic shift unit for multiplying ^L by 2 ^L, and a logarithmic addition unit for inputting the multiplication result to the logarithmic table, referring to the logarithmic table, and adding L to a reference value to output the logarithmic calculation unit. Things.

An exponent subtraction section for subtracting an appropriate integer M from the input of the exponent calculation section when the input value is not included in the input value range of the exponent table, An exponent shift unit is provided as an input of the exponent table, after referencing the exponent table, multiplying the reference value by 2- ^M and outputting the result of the exponent calculating unit.

Here, the logarithmic and exponential tables refer to not only the RAM and ROM but also general circuits for calculating the values of logarithmic and exponential functions with respect to input values within a fixed time.

In the present invention, when a power of X ^N is calculated for the input values X and N, a logarithm logaX with base a is obtained by referring to a logarithmic table, and a logaX × N is obtained by a multiplier.
Is calculated, and log X of a is obtained by referring to the index table.
Calculating the N should alogaX × ^N = X N. Since the present invention does not perform loop calculation, high-speed calculation is possible. Also, by dividing the table into two tables, a logarithmic table and an exponent table, each table can have one input, and the capacity of the table can be reduced.

Further, in order to further reduce the capacity of the table, when the input value of the logarithmic calculation unit is not included in the input value range of the logarithmic table, the input value is multiplied by 2 ^L to an appropriate integer L, The multiplication result is input to the logarithmic table, and after referring to the logarithmic table, L is added to the reference value to obtain an output of the logarithmic calculator, and the input value of the exponent calculator is not included in the input value range of the exponent table. In this case, an appropriate integer M is subtracted from the input value, the result of the subtraction is used as an input to the exponent table, and after referring to the exponent table, the reference value is multiplied by 2- ^M to obtain an output of the exponent calculating unit. Accordingly, even when the input values of the logarithmic calculation unit and the exponent calculation unit are not included in the input range of the logarithmic and exponent table, the exponentiation can be performed.
Accordingly, the input value range of the logarithmic and exponential table can be limited, and the capacity of the table can be reduced.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.
This will be described with reference to FIG. FIG. 8 shows an example of a graphics / power generation apparatus using a digital power operation device according to the present invention.
1 shows a system configuration. This system has a CPU (1000) for executing application software, etc., and a main memory MM.
Memory controller MC for controlling (3000) etc.
(2000), a system bus controller (4000) for controlling the system bus, and data received from the system bus controller are sent to a geometry processor (5000) for performing coordinate transformation and the like. GPIF (0000), GPIF that performs processing such as FI conversion, pack, and light source calculation
(0000), a rendering processor (6000) that develops pixel information into pixel information, a frame memory (7000) that stores pixel information generated by the rendering processor (6000), and a frame memory (700).
CRT (8000) for displaying the contents of 0).

Next, the operation of the entire system will be described. The CPU (1000) executes the application and issues graphics commands and data such as vertex coordinates, normal vectors, texture data, reflection coefficients of materials, colors for each reflected light of the light source, etc. of the figure to be drawn. And MC
(2000) and system bus controller (4000)
And output it to GPIF (0000). GPIF
(0000) is the system bus controller (400
The command and data sent from (0) are held in the GPIF input means (100).

The geometry processor (5000) is a GP
The command and data held in the IF input means (100) are read, and geometric calculations such as coordinate conversion are performed according to the command and data, and vertex coordinates, normal vectors, texture
Data and the like are calculated and sent to GPIF (0000).

The GPIF (0000) performs FI conversion and packing, if necessary, on the data sent from the geometry processor (5000) in accordance with the command and the data, performs light source calculation for calculating a color for each vertex, and performs a continuous triangle. The drawing command, vertex coordinates, color, and texture data are output to the rendering processor (6000).

A rendering processor (6000) generates pixels inside the figure by interpolation from the command and data, writes the contents to be displayed on a CRT (8000) in a bitmap format to a frame memory (7000), and Display on CRT (8000).

Further, the internal configuration of the GPIF (0000) will be described in detail.

GPIF (0000) is a GPIF input means (10) which is a buffer for holding commands and data sent from the system bus controller (4000).
0), LBuf (200) which is a buffer for holding data sent from a geometry processor (5000) for reading the command and data and performing geometric calculation, and command interpreting means (LBuf (200) for converting the command and data from LBuf (200). BufSW (300), which is a register for outputting the data to the FI converter (400) and the FI converter (400), a command interpreter (600) for interpreting the command, and an FI converter for performing FI conversion of data according to the command if necessary. (400) and F if necessary according to the command.
Packing means (50) for performing packing processing of data after I conversion
0), a light source table (700) holding light source data necessary for the light source calculation after the FI conversion and the pack processing, and a light source calculation based on the light source data held in the light source table (700) to calculate a color. A light source calculation means (000); a control means (800) for controlling the order of commands and data sent from the geometry processor (5000), the packing means (500) and the light source calculation means (000); CBuf (90
0) and Buf which is a register for outputting the command and data to the rendering processor (6000).
FL (950).

FIG. 9 shows details of the light source table (700) and the light source calculating means (000).

The light source table (700) holds parameters required for light source calculation in fixed point numbers. This parameter includes a parameter independent of the light source and a parameter whose value changes depending on the light source. The light source table (700) holds one parameter value independent of the light source and eight parameter values (eight light sources) whose values change depending on the light source. If the number of light sources is nine or more, the values of the light sources are updated one by one from the values already used in the calculation.

In order to perform such a write control on a parameter independent of the light source, a read pointer indicating which value is currently being calculated out of eight values,
An RPNT register is provided, the value after RPNT is locked and the update is postponed.

A light source calculation means (000) calculates an inner product of an HN inner product which calculates an inner product of a normal vector and a halfway vector.
(010), a power calculator (00) for calculating the SM product of the inner product, an LN inner product calculator (020) for calculating the inner product of the normal vector and the light source vector, and a power calculator (0
0) and an output of the LN inner product calculation unit (020), and a color calculation unit (030) for calculating a color for each vertex.

The HN inner product calculation unit (010) calculates a normal vector (Nx, Ny, Nz) and a halfway vector (Hx,
Hy, Hz) and outputs the 13 bits of the result to the exponentiation calculation unit (00).

The exponentiation calculation unit (00) outputs the output of the HN inner product calculation unit (010) to the mirror index SM (1 to 128) of the material.
And outputs the resulting 8 bits to the color calculation unit (030).

The LN inner product calculation unit (020) calculates the normal vector (Nx, Ny, Nz) and the light source vector (Lx, Ly, L
z), and outputs the result to the color calculation unit (030). The color calculation unit (030) has three sets of similar resources for independently calculating three colors of RGB.
For example, for R, the R component LcaR of the environment reflection light, the R component LcdR of the diffuse reflection light, and the R component Lcs of the specular reflection light
R, R component of environmental reflection coefficient KaR, R component of diffuse reflection coefficient KdR, R component of specular reflection coefficient KsR, sum KR of radiation reflection light and R component of entire environment reflection light, product of attenuation coefficient and spot light source effect AtSp, the output of the exponentiation calculation unit (00) and the output of the LN inner product calculation unit (020) are input,
Outputs the 8 bit R component of the vertex color.

FIG. 1 shows the configuration of the power calculator (00). For convenience of explanation, the inputs are X and N, and the output is X ^N
And That is, X and N are HN in the above description.
Output of inner product calculating unit (010) and mirror index SM of material
Corresponding to X is a 13-bit fixed-point number in the range 0 to
1, N is an 8-bit fixed point number in the range 0 to 128, X
^N is an 8-bit fixed-point number in the range of 0 to 1.

This circuit calculates a logarithmic function value for an input X as a fixed-point number of 15 bits using a logarithmic calculation unit (1).
0), the output of the logarithmic calculation unit (10) is multiplied by N, and
A multiplier (20) for outputting a fixed-point number of bits, and an exponent calculating unit (30) for calculating the value of an exponential function for the output of the multiplier (20) using an 8-bit fixed-point number.

If the logarithmic calculation unit (10) and the exponent calculation unit (30) are directly used as tables, the logarithmic table has an input range of 0 to 1 and 13 bits, and an output range of 0 to 8 (strictly 8 Is not included), the exponent table is 10 bits when the input range is 0 to 8 (strictly, 8 is not included), and the output range is 8 bits when the output range is 0 to 1, which are 122, 880 bits, 8, and 8 respectively in terms of memory capacity. 192bi
t and huge capacity.

However, the log and exponent tables are degenerated,
That is, by limiting the input / output range and configuring the logarithmic calculation unit (10) and the exponent calculation unit (30) as described below, the capacity of each table is significantly reduced (24,576 bits, 768 bits in terms of memory capacity). ), And can be calculated with the same accuracy as before the degeneration.

That is, the logarithmic calculation unit (10) keeps K until the input value falls within the input range of the logarithmic table (12).
And bit left shift (multiply 2 ^K), the shift amount of 3bit K
And a logarithmic shift unit (1) that outputs a shift result of 11 bits
1) and the value of the logarithmic function for the shift result is 12 bits
And a logarithmic addition unit (13) for adding K to the output of the logarithmic table (12) and outputting a 15-bit fixed-point number.

The exponent calculating section (30) subtracts M from the input value until the input range of the degenerated exponent table (32) is entered, and outputs a 3-bit subtraction amount and a 7-bit subtraction result. ), A reduced exponent table (32) for outputting the value of the exponential function for the subtraction result as a 6-bit fixed-point number, and an exponential shift unit (33) for shifting the output of the exponent table (32) right by M bits. Be composed.

The operation when the logarithmic calculation unit (10) calculates the output Py with respect to the input Px (this operation is indicated by a white arrow) will be described with reference to FIG. The graph of FIG. 2 is a part of a logarithmic function in a domain 0 to 1 (strictly does not include 0) and a range of 0 to 8 (strictly does not include 8) where the base is 2 ⁻¹ = 0.5. Is expressed. Here, the domain means the domain of the input value x, and the value domain is the output value y accompanying the variation of x.
Means the domain.

The area 0 is a domain 0.5 to 1 (strictly speaking, 0.5
Is not included), and the range of 0 to 1 (strictly does not include 1). The logarithmic table (12) holds logarithmic functions in this range. In other words, the domain of the entire graph is 0 to
In contrast to 1, the domain of the range held by the logarithmic table (12) is 0.5 to 1 and 1/2, and the range of the entire graph is 0 to 8, The range of values held by the logarithmic table (12) is reduced to 0 to 1 and 1/8.

The area 1 is a part of a domain 0.25 to 0.5 (strictly not including 0.25) and a range of 1 to 2 (strictly not including 2). The area 1 is obtained by multiplying the area 0 by x by 2 ^-1 and adding 1 to y. Generally, the domain K (K is an integer from 0 to 7) is defined as domain 2
^{-K-1 to} 2 ^-K (strictly 2 ^-K-1 is not included), range ^{K to K}
+1 (strictly does not include K + 1). Due to the nature of the logarithmic function, region K multiplies x by 2 ^−K with respect to region 0, and y
To which K is added. Logarithmic shift part (11) is Px
Depends on which domain K is included in the domain,
Is shifted 2 ^K times (K left shift) to shift to the domain 0 domain. Px for simplicity is assumed to be included in the domain region 1, and Qx 2 ¹ times (1 shift) result of Px (represents this operation by an arrow (1)). Since Qx is included in the input value range of the logarithmic table (12), Qy is obtained by referring to the logarithmic table (12) (this operation is represented by an arrow (2)). Finally, the logarithmic addition unit (13)
Calculates Py by adding 1 of the shift amount to Qy (this operation is indicated by an arrow (3)).

The operation of the logarithmic shift unit (11) will be described with reference to FIG. The logarithmic shift unit (11) shifts the input value in the domain of the area K to the left until it enters the domain of the area 0, and outputs the shift amount and the shift result at that time.

For example, the domain of the area 2 is 2 ⁻³ to ^{2 −2} and 1
When expressed as a 3-bit fixed-point number, 0.001000000001 to 0.01
0000000000, but the value in this domain is 0.0010100111
The shift amount when shifting 01 to the left to the definition area of area 0 from 0.100000000001 to 1.000000000000 is this value 0.00101001
The uppermost 1 of 0.001010011100, which is obtained by subtracting 0.000000000001 from 1101, coincides with the shift amount when left-shifted until the second digit from the high order comes to the second digit. In this case, the shift amount is 2. Where 0.000000000001 is subtracted from 0.010000000000
This is because the maximum value in the area is handled without exception as in In such a case, without subtracting 0.000000000001 and shifting until the top 1 comes to the second digit from the top, 0.100000
It becomes 000000 and is not included in the domain 0.

The domain of the area 0 is 13 bits from 0.5 to 1 (strictly, not including 0.5).
By subtracting the 3-bit fixed-point number 0.100000000001 and setting the domain to be 0 to 0.5 (strictly excluding 0.5), the upper 2 bits always become 00. Taking advantage of this, the input of the logarithmic table (12) is converted from 13 bits into
By removing the upper 2 bits that are always 00 and setting the lower 11 bits, the number of input bits can be reduced by 2 bits. Therefore, from the shift result, a 13-bit fixed-point number 0.10000000
The value of 11 bits obtained by subtracting 0001 and removing the upper 2 bits is output to the logarithmic table (12).

However, the shift amount is 7 at the maximum. The reason is that even if the value is shifted to the left by 7 bits, the value that is not included in the domain of the area 0 is smaller than 2 ⁻⁸ and does not appear in the power result of 8-bit precision. In such a case, since subtracting the fixed-point number 0.100000000001 of 13 bits results in a value smaller than 0, the output value is clamped to 0 and the output value is set to 0.000000000000.

In the case of (a), the input value is 0.001001110100
The value obtained by subtracting 0.000000000001 is 0.001001110011. If the most significant 1 of this value is shifted left by 2 bits, it comes to the second digit from the most significant, so the shift amount is 2. Therefore, input value 0.001001110100 is shifted left by 2 bits.
Is the shift result. The output value is the shift result 0.1001110100
It is 0.000111001111 which is obtained by subtracting 0.100000000001 from 00.

In the case of (b), the input value is 0.000000100000
The value obtained by subtracting 0.000000000001 is 0.000000011111. Since the most significant 1 of this value is shifted to the second digit from the most significant bit by shifting 7 bits to the left, the shift amount is 7. Therefore, the input value 0.000000100000 is shifted to the left by 7 bits to 1.00000000.
0000 is the shift result. The output value is the shift result 1.000000
It is 0.011111111111 obtained by subtracting 0.100000000001 from 000000.

In the case of (c), the input value is 0.000000000101.
The value obtained by subtracting 0.000000000001 is 0.000000000100. Since the most significant 1 of this value does not come to the second digit from the most significant bit even if it is shifted 7 bits to the left, the shift amount is 7 at the maximum. Therefore, 0.001010000000 obtained by shifting the input value 0.000000000101 to the left by 7 bits is the shift result. Shift result
If 0.100000000001 is subtracted from 1.000000000000, it will be less than 0. Therefore, 0 is clamped and the output value becomes 0.000000000000.

The logarithmic shift unit (1) operating as described above
FIG. 4 shows a circuit diagram of 1).

As described above, the logarithmic shift unit (11) performs this subtraction immediately after the input to determine the shift amount using the value obtained by subtracting the fixed value of 13 bits 0.000000000001 from the input value. At the top of FIG. 4, the upper 8 bits of the subtraction result
And input values are listed. Logic about shift is 3
It is divided into columns. First, in the first stage, NOR1 takes the NOR of the upper 5 bits out of the upper 8 bits of the subtraction result, and determines whether the upper 8 bits of the subtraction result and the input value are shifted left by 4 bits in accordance with 0 and 1 of this value. decide.

If the output of NOR1 is 1, it means that the upper 5 bits of the subtraction result are all 0 and there is room for left shift by 4 bits, so that the upper 8 bits of the subtraction result and the input value are Shift left by 4 bits. In addition, the highest order of the shift amount is set to 1. This indicates that the data has been shifted left by 4 bits.

If the output of NOR1 is 0, 1 is included in the upper 5 bits of the subtraction result, which means that the left shift cannot be performed by 4 bits. The value does not shift left. Also, the highest order of the shift amount is set to 0. This indicates that 4 bits could not be shifted left.

Next, in the second stage, NOR2 takes the NOR of the upper 3 bits of the shift result in the first stage of the subtraction result, and according to 0 and 1 of this value, NOR2 takes the result of the subtraction and the input value in the first stage. It is determined whether the shift result is further shifted left by 2 bits.

If the output of NOR2 is 1, this means that the upper 3 bits of the shift result in the first stage of the subtraction result are all 0 and that there is room to shift left by 2 bits. And the result of shifting the input value in the first stage is shifted left by 2 bits. Also, the second digit of the shift amount is 1. This indicates that the data has been shifted left by 2 bits.

If the output of NOR2 is 0, it means that 1 is included in the upper 3 bits of the shift result in the first stage of the subtraction result, and 2 bits left shift cannot be performed. The result of subtraction and the result of shifting the input value in the first stage are not shifted left. Also, the second digit of the shift amount is set to 0. This indicates that 2 bits could not be shifted left.

Next, in the third stage, NOR3 takes NOR of the upper 2 bits of the shift result in the second stage of the subtraction result, and according to 0 and 1 of this value, NOR3 takes the result of the subtraction and the input value in the second stage. It is determined whether or not the shift result is further shifted left by one bit.

If the output of NOR3 is 1, it means that the upper 2 bits of the shift result in the second stage of the subtraction result are all 0 and there is room to shift left by 1 bit. And the result of shifting the input value in the second stage is shifted left by 1 bit. Also, the lowest order of the shift amount is 1. This indicates that the data has been shifted left by 1 bit.

If the output of NOR3 is 0, it means that the upper 2 bits of the shift result in the second stage of the subtraction result contain 1 and cannot shift left by 1 bit. The result of subtraction and the result of shifting the input value in the second stage are not shifted left. The lowest order of the shift amount is set to 0. This indicates that 1 bit left shift could not be performed.

At this stage, the shift amount of 3 bits is determined, but the output value to the logarithmic table is a 13-bit fixed-point number 0.100000000001 based on the shift result of the input value at the third stage.
Is subtracted and further clamped to 0.

Next, the logarithmic table (12) will be described. As described above, the input of the logarithmic table (12) is an 11-bit fixed-point number in the input value range 0 to 0.5 (strictly excluding 0.5). The output of the logarithmic table (12) is a value obtained by adding a 13-bit fixed-point number 0.100000000001 to the input value and expressing the value of the logarithmic function as a 12-bit fixed-point number. The output value range is 0 to 1 ( Strictly, 1 is not included).

The logarithmic table (12) can be made up of a RAM or a ROM so that the input value is converted into an address and referred to. However, here, the output logical value is expressed by the logical expression of the input logical value. Thus, a logarithmic table (12) is constituted by circuits corresponding to the logical expressions.

Let each bit of the input of the logarithmic table (12) be a
.., A10 and each bit of the output of the logarithmic table (12) is b0, b1,.
, B11 can be represented by a logical expression of the sum of products of a0, a1, ..., a10. Furthermore, the Queen's method and the consensus method are well known as methods using each term of the sum of products as the main term. The Queen's method and the consensus method are described in Munehiro Goto, published by Maruzen Co., Ltd. on June 30, 1982, in Computer Engineering for Electrical and Electronic Students, pp. 40-45.

The logarithmic table (12) can be constituted by a circuit corresponding to the logical expression generated by such a method.

As a result of actual logical synthesis, 0.35 μm was obtained.
Approximately 4k gates were required for CMOS of m 2.

Finally, the logarithmic adder (13) will be described. The input of the logarithmic addition unit (13) is a logarithmic shift unit (11)
And the output of the logarithmic table (12). The logarithmic addition unit (13) adds the shift amount to the output value of the logarithmic table (12) and outputs the result.

The output value range of the table is 0 to 1 (strictly 1
Is not included), and the shift amount is an integer. Therefore, the output of the logarithmic addition unit (13) is a fixed-point number of 15 bits obtained by adding 3 bits of the shift amount to the higher order of 12 bits of the output value of the table.

Next, the multiplier (20) will be described. The input of the multiplier (20) is the logarithmic calculator (10)
And N.

The multiplier (20) is connected to the logarithmic calculation unit (1).
0) is multiplied by 15 bits of output and N8 bits, and the output value range is 0 to
It is output as a 10-bit fixed-point number of 8 (strictly 8 is not included).

However, when the result of the multiplication becomes 8 or more, the output is clamped to the maximum output value. The reason is that a power of 2 ^-1 of 8 or more is smaller than 2 ^-8 and does not appear in a power result of 8 bit precision.

FIG. 5 shows the operation when the index calculating section (30) calculates the output Py with respect to the input Px (this operation is indicated by a white arrow). The graph of FIG. 5 shows a part of the exponential function in the domain 0 to 8 (strictly does not include 8) and the range of 0 to 1 (strictly does not include 0) where the base is 2 ⁻¹ = 0.5. Is expressed. Area 0 is domain 0-1
(Strictly, 1 is not included), a range of 0.5 to 1 (strictly does not include 0.5), and an exponent table (3
2) holds an exponential function in this range. That is, the domain of the entire graph is 0 to 8, whereas the domain of the range held by the exponent table (32) is 0 to 1 and 1
/ 8, and the value range of the entire graph is 0 to 1, whereas the value range of the range held by the exponent table (32) is reduced to 0.5 to 1/2.

The area 1 is a part of a domain 1 to 2 (strictly not including 2) and a range of 0.25 to 0.5 (strictly not including 0.25). regions 1 to 1 x added to area 0 is obtained by 2 ^-1 times y.

[0065] Generally, the area M (M is an integer from 0 to 7) is domain m to m + 1 (strictly speaking M + 1 is not included), range 2 ^-M-1 ~2 ^-M (strictly 2 ^{- (Excluding M-1} )
The area M is obtained by adding M to x and multiplying y by 2 ^−M with respect to the area 0 due to the nature of the exponential function.

The exponent subtraction unit (31) subtracts M from Px and slides to the domain 0 according to the domain of domain M in which Px is included. Px for simplicity
Is assumed to be included in the domain of area 1, and 1 from Px
The result of the subtraction is defined as Qx (this operation is indicated by an arrow (1)). Since Qx is included in the input value range of the exponent table (32), Qx is referred to by referring to the exponent table (32).
y is obtained (this operation is represented by arrow (2)). Finally, the exponent shift unit (33) calculates Py by right-shifting (multiplying by 2 ^-1 ) the Qy by a subtraction amount of 1 (this operation is represented by an arrow (3)).

The exponent subtraction unit will be described. Exponential subtraction unit (3
Input of 1) is an input value range of 0 to 8 (strictly 8 is not included)
Is a 10-bit fixed-point number. As described above, the exponent subtraction unit (31) subtracts M from Px and slides to the domain 0 in accordance with the domain of the area M in which the input value is included. , And the value obtained by subtracting M from the input value is the lower 7 bits of the input value.

Next, the index table (32) will be described. The input of the exponent table (32) is an exponent subtraction unit (31)
And is a 7-bit fixed-point number in the input value range 0 to 1 (strictly not including 1). Also, the value range of the area 0 is 0.5 to 1 (strictly excluding 0.5),
By performing a -0.5 parallel movement in the y direction to obtain a value range of 0 to 0.5 (strictly excluding 0.5), the exponent table (3
The upper 2 bits of the output of 2) are 00, and the number of output bits is 2
bit can be reduced.

Therefore, the output of the exponent table (32) is obtained by converting the value of the exponential function in the input value into an 8-bit fixed-point number of 0.5, that is, an 8-bit fixed-point number of 0.100000.
A 6-bit fixed point number is obtained by subtracting 1, and the output range is 0 to 0.5 (strictly, 0.5 is not included).

Similarly to the logarithmic table (12), the exponent table (32) can be made of a RAM or a ROM so that the input value is converted into an address and referred to. The exponent table (32) is constituted by a circuit which is expressed by a logical expression of the input logical value and corresponds to the logical expression. As a result of actually performing logical synthesis, about 1 k gate was required for 0.35 μm CMOS.

Finally, using FIG. 6, the exponent shift unit (33)
Will be described. The inputs of the exponent shift unit (33) are the subtraction number output from the subtraction unit and the output of the exponent table (32). As described above, the output of the exponent table (32) is obtained by converting the value of the exponential function in the input value into an 8-bit fixed-point number of 0.5, that is, an 8-bit fixed-point number of 0.10.
Since it is a 6-bit fixed-point number obtained by subtracting 00001, the exponent shift unit (33) conversely adds 0.5, that is, an 8-bit fixed-point number 0.1000001 to the output of the exponent table (32), and sets the value range to 0.5 to 0.5. It is necessary to return to 1 (strictly 0.5 is not included). Next, the value is right-shifted by the subtraction amount and output.

In the case of (a), an output value of 0.0010011 is obtained by adding an 8-bit fixed-point number 0.1000001 to the output 0.01011 of the exponent table (32) and right-shifting by the subtraction amount 2. However, where the upper bits are vacated by right shift, 0
Enters.

In the case of (b), an output value of 0.0000011 is obtained by adding an 8-bit fixed-point number 0.1000001 to the output 1.01101 of the exponent table (32) and right-shifting by a subtraction amount of 5 to obtain 0.0000011.

The exponential shift unit (3
FIG. 7 shows a circuit diagram of 3). The input of the exponent shift unit is a subtraction amount 3 bits output from the exponent subtraction unit and 6 bits output from the exponent table (32). Index table (3
For the output from 2), an 8-bit fixed-point number 0.1000001 is added immediately after the input. The addition result is 8bit
Is a fixed-point number.

The logic related to shift is roughly divided into three stages. First, in the first stage, when the least significant of the subtraction number is 1, the addition result is shifted right by 1 bit, and when the least significant value of the subtraction number is 0, the addition result is not right shifted.

Next, in the second stage, when the second digit of the subtraction number is 1, the shift result in the first stage of the addition result is represented by 2 bits.
If the second digit of the subtraction number is 0 when right-shifting, the shift result in the first stage of the addition result is not right-shifted.

Finally, in the third stage, when the highest order of the subtraction number is 1, the shift result of the second stage of the addition result is 4bi.
t Shift right, and when the highest order of the subtraction number is 0, do not right-shift the shift result in the second stage of the addition result.

In this embodiment, all the exponentiation calculation units are 0.35.
When mounted on a μm CMOS, about 7.5 k gates are required, and the operation is completed in about 35 nsec. This makes it possible to embed the light source calculation in the GPIF (0000) chip, and reduce the processing of the bottleneck geometry processor (5000), thereby improving the performance of the system by about 2 times. We were able to.

[0079]

As described in detail above, the digital exponentiation device of the present invention performs an operation by referring to a table, so that an operation result can be obtained faster than a loop calculation.

The logarithmic table and the exponent table
By dividing the table into two, the input of each table
One can reduce the capacity of the table.

If the input value of the logarithmic calculation unit is not included in the input value range of the logarithmic table, the input value is multiplied by 2 ^L for an appropriate integer L, and the result of the multiplication is input to the logarithmic table. After referring to the logarithmic table, the capacity of the logarithmic table can be further reduced by adding L to the reference value, and when the input value of the exponent calculation unit is not included in the input value range of the exponent table, the input value Then, after subtracting an appropriate integer M from the above and using the result of the subtraction as an input to the exponent table, referencing the exponent table, and multiplying the reference value by 2- ^M , the capacity of the exponent table can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a digital power operation device.

FIG. 2 is a diagram illustrating an operation of a logarithmic calculation unit.

FIG. 3 is a diagram illustrating an operation of a logarithmic shift unit.

FIG. 4 is a diagram showing a circuit configuration of a logarithmic shift unit.

FIG. 5 is a diagram showing the operation of an index calculation unit.

FIG. 6 is a diagram illustrating an operation of an exponential shift unit.

FIG. 7 is a diagram illustrating a circuit configuration of an exponent shift unit.

FIG. 8 is a diagram showing a configuration of a graphics system.

FIG. 9 is a diagram showing a configuration of a light source table and a light source calculation unit.

[Explanation of symbols]

00: power calculator, 10: log calculator, 11: log shift unit, 12: log table, 13: log adder, 20
... Multiplier, 30 ... Exponent calculation unit, 31 ... Exponent subtraction unit, 32
... Exponent table, 33 ... Exponential shift section, 000 ... Light source calculating means, 010 ... HN inner product calculating section, 020 ... LN inner product calculating section, 030 ... Color calculating section, 100 ... GPIF input means, 20
0: LBuf, 300: BufSW, 400: FI conversion means, 500: packing means, 600: command interpretation means, 700: light source table, 800: control means, 900:
CBuf, 950 ... BufFL, 0000 ... GPIF,
1000 CPU, 2000 MC, 3000 MM,
4000 system bus controller, 5000 geometry processor, 6000 rendering processor, 7000 frame memory, 8000 CRT.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Kazuhisa Takami 7-1-1, Omikacho, Hitachi City, Ibaraki Prefecture Inside the Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Kazunori Oniki 5-chome, Omikamachi, Hitachi City, Ibaraki Prefecture No. 1 Inside the Omika Plant of Hitachi, Ltd.

Claims (9)

[Claims] 1. A logarithmic calculation unit for outputting a logarithmic value of X with respect to an input value X, a multiplier for multiplying an output of the logarithmic calculation unit by a value N raised to a power, and an exponent for an output of the multiplier. consists of a index calculation unit for outputting a value, a digital exponentiation device for calculating the X ^N, the logarithm calculation unit calculates log using log table, the index calculating unit using an exponential table index Wherein the base of the logarithm calculated by the logarithmic calculation unit and the base of the exponent calculated by the exponent calculation unit have the same value. 2. The method according to claim 1, wherein the base of the logarithmic function and the base of the exponential function are 2 ^K (K is 0
The logarithmic calculation unit includes: a logarithmic table in which an input value range is normalized; and 2 ^{L of the} input value such that an input value to the logarithmic calculation unit falls within an input value range of the logarithmic table. (L is an integer) and a logarithmic shift unit that outputs the result to the logarithmic table, and a logarithmic adder that adds L to the output of the logarithmic table and outputs the result to the logarithmic calculation unit. Digital power computing unit. 3. The logarithmic shift unit according to claim 2, wherein:
A digital exponentiation device for shifting the input value to the left by L bits. 4. The method according to claim 1, wherein the base of the logarithmic function and the base of the exponential function are 2 ^K (K is 0
And the exponent calculation unit calculates the exponent table from which the input value range is normalized and the input value so that the output value from the multiplier falls into the input value range of the exponent table. Is an integer)
An exponential subtraction unit that outputs the exponent table, and an exponential shift unit that multiplies the output value of the exponent table by 2- ^M and outputs the result of the exponent calculation unit. 5. An exponential shifter according to claim 4, wherein:
A digital exponentiation device, wherein the output value of the exponent table is shifted right by M bits. 6. A light source calculating unit for calculating a light source, a rendering processor for expanding graphic data to be displayed into pixel information based on a result of the light source calculation, a memory, and a display device for displaying the pixel information stored in the memory. In the graphics system, the light source calculation unit includes at least a logarithmic calculation unit that outputs a logarithmic value for the input value X using a logarithmic table, and a multiplier that multiplies the output of the logarithmic calculation unit by a power N. A graphics system comprising: an exponent calculator for outputting an exponent value for the output of the multiplier using an exponent table. 7. The graphics system according to claim 6, wherein the base of the logarithm calculated by the logarithmic calculator and the base of the exponent calculated by the exponent calculator are the same value. 8. The method according to claim 6, wherein the base of the logarithmic function and the base of the exponential function are 2 ^K (K is 0
The logarithmic calculation unit includes: a logarithmic table in which an input value range is normalized; and 2 ^{L of the} input value such that an input value to the logarithmic calculation unit falls within an input value range of the logarithmic table. (L is an integer) and a logarithmic shift unit that outputs the result to the logarithmic table, and a logarithmic adder that adds L to the output of the logarithmic table and outputs the result to the logarithmic calculation unit. Graphics system. 9. The method according to claim 6, wherein the base of the logarithmic function and the base of the exponential function are 2 ^K (K is 0
And the exponent calculation unit calculates the exponent table from which the input value range is normalized and the input value so that the output value from the multiplier enters the input value range of the exponent table. Is an integer)
A graphics system, comprising: an exponent subtraction unit that outputs the exponent table; and an exponent shift unit that multiplies the output value of the exponent table by 2- ^M to output the exponent calculation unit.