GB2351577A - Apparatus and method for performing data computations - Google Patents

Abstract

In a computer processing apparatus (2, fig. 1), the value of a first number raised to the power of a second number is calculated. This has particular application in the calculation of specular lighting values in 3D computer graphics, such as the Phong method. Initially the first and second numbers are in floating point form. A logarithm value of the first number is calculated in fixed point form, such as by use of a look-up table. The second number is converted to fixed point form and multiplied by this logarithm value. An antilogarithm is found, such as by using a look-up table, of this to give a floating point number.

Description

2351577 APPARATUS AND METHOD FOR PERFORMING DATA COMPUTATIONS The present

invention relates to a data signal processing apparatus and method for processing first and second numbers to generate a signal defining the result of raising the first number to the power of the second number.

The calculation of the value of one number raised to the power of another number is required in many processing applications.

For example, in the field of three-dimensional (3D) computer graphics, it is necessary to perform such a calculation to calculate lighting values for partially specularly reflective surfaces.

More particularly, it is well known that light incident on a perfect specular reflector (such as a mirror) in a particular direction will be reflected only in another particular direction. The angle between the direction of the incident light and the direction of the reflected light is bisected by the surface normal at the point of incidence on the reflecting surface.

2 However, for non-perfect reflectors, such as smooth plastic materials or the like, it is necessary to modify the theoretical model for specular reflection to account for the fact that some light reflected from a surface on which light is incident in a single direction will be reflected in directions other than the predetermined direction of reflection. The intensity of reflected light at angles "a" away from the theoretical direction of reflection will fall off as "a" increases. For almost perfect reflectors, this fall off is sharp, and for less effective specular reflectors, the fall off becomes shallow. This fall off can be approximated by COSNQ, where N is the specular reflection exponent of the ref lecting material. This approximation was made by Phong and is discussed in Foley, van Dam, Feiner and Hughes, 2nd Edition, Addison-Wesley Publishing Company, ISBN 0-201-12110-7 on page 729. Values of N can vary f rom one to several hundred, depending on the surface material being simulated. If N = 1, a broad gentle fall off is provided, whereas higher values of N produce a sharp, focussed highlight.

Accordingly, in order to calculate the illumination of a non-perfect specular reflector, it is necessary to compute the term COSNa, and, if a Phong shading technique 3 is being used, this computation must be performed for each pixel in the polygon for every frame of the graphical image to be generated. This can become computationally expensive, especially for high values of N. This is because, in the past, the term cos" cx has been calculated by repeated multiplication of cos a.

Therefore, it can be difficult to generate a visually realistic image in real time.

The present invention has been made with the above problems in mind.

According to the invention, there is provided a signal processing apparatus and method for calculating the value of a first number raised to the power of a second number, in which a logarithm of the first number is calculated and multiplied by the second number, and an antilogarithm of the multiplication result is calculated. The format of the numbers in either floating point or fixed point format is selected to optimise the calculation operations.

Embodiments of the invention will now be described by way of example, in conjunction with the accompanying drawings, in which:

4 Figure 1 illustrates a block diagram showing the general arrangement of a data processing apparatus according to an embodiment of the invention; Figure 2 schematically illustrates notional functional components of the processing apparatus in Figure 1 in an embodiment of the invention; Figure 3 schematically illustrates an object including a 10 partially specularly reflecting polygon to be rendered; Figure 4 illustrates a vector diagram to represent the specular reflection of light at a surface; Figure 5a illustrates a graph demonstrating the distribution of reflected light at a weakly specular surface; Figure 5b illustrates a graph similar to that shown in 20 Figure 5a for a moderately specular surface; Figure 5c illustrates a graph similar to that shown in Figure 5a for a strongly specular surface; Figure 6 illustrates processing elements within the renderer of Figure 2 which are operable to process data in an embodiment of the invention; Figures 7a, 7b, 7c nd 7d illustrate the storage of fixed point and floating point numbers within registers in an embodiment of the invention; Figure 8 illustrates a flow diagram showing processing operations in an embodiment of the invention; Figures 9 and 10 illustrate flow diagrams showing details of the processing operations illustrated in Figure 8 at steps S10 and S16 respectively; and Figures 11 to 13 illustrate set-up procedures in an embodiment for the processing operations illustrated in Figures 8 to 10.

An embodiment of the invention will now be described which is concerned with 3D computer graphics. However, the present invention is not limited to 3D computer graphics, but is also applicable to other applications.

Figure I is a block diagram showing the general arrangement of a data processing apparatus according to 6 an embodiment.

In the apparatus, there is provided a computer 2, which comprises a central processing unit (CPU) 4 connected to a memory 6 operable to store a program defining the sequence of operations of the CPU 4, and to store object and image data used in calculations by the CPU 4.

Computer 2 also contains, in a conventional manner, hardware registers, a sound card and a graphics card, etc.

Coupled to an input port of the CPU 4 are input devices 8, which, in this embodiment, comprise a keyboard and a position sensitive input device such as a mouse, tracker ball, or a digitizer tablet and stylus etc.

Also coupled to the CPU 4 is a frame buffer 10 which comprises a memory unit arranged to store image data relating to at least one image, for example by providing one (or several) memory location(s) per pixel of the image. The value stored in the frame buffer for each pixel defines the colour or intensity of that pixel in the image.

Coupled to the frame buffer 10 is a display unit 12 for 7 displaying the image stored in the frame buffer 10 in a conventional manner. Also coupled to the frame buffer 10 is a video tape recorder (VTR) 14 or other image recording device, such as a paper printer or 35 mm film recorder.

coupled to the memory 6 (typically via the CPU 4), and possibly also to the frame buffer 10, is a mass storage device 16, such as a hard disc drive, having a high data storage capacity for storing data generated by computer 2.

Also coupled to the memory 6 is a disc drive 18 which is operable to accept removable data storage media, such as a floppy disc 20, and to transfer data stored thereon to the memory 6. A CD-ROM drive 22 is further coupled to the memory 6, operable to accept a CD-ROM 24, and to transfer data stored thereon to the memory 6.

A modem 26 is coupled to the CPU 4, in order to allow the CPU 4 to establish a data link with one or more other devices, such as via the Internet.

Computer 2 is programmed to operate in accordance with programming instructions input for example as data stored 8 on a data storage medium, such as disc 20 or CD-ROM 24, and/or as a signal input to computer 2 via modem 26, and/or entered by a user by a keyboard 8. Thus embodiments of the invention can be supplied commercially in the form of programs stored on a floppy disc 20, CD ROM 24 or other medium, or signals transmitted over a data link for instance via the modem 26, so that the receiving hardware becomes re-configured into an apparatus embodying the invention. As will be seen, the invention allows technically better performance to be achieved than was hitherto possible with a given type of computer hardware.

The overall operation of the apparatus will now be described.

With reference to Figure 2, the computer 2 performs a number of different operations at different times, executing one or more corresponding stored programs within the memory 6, and therefore comprises (together with the memory 6) means 44, 48 and 52 for performing such operations. These means are illustratively shown in Figure 2 as separate, although in the embodiment, all are performed by the CPU 4 in cooperation with the memory 6.

It will be understood, however, that separate processors 9 or dedicated logic circuits, operatively connected, could be provided to execute one or more of the functions.

The arrangement may thus be considered as comprising, firstly, a definer or editor 44 arranged to define in a conventional manner the shape of two or more three dimensional objects, one or more light sources to illuminate the object(s) and a camera to view the object(s). In the present embodiment, the data defining an object is data representing control points or vertices of a plurality of surfaces making up the object, which in the embodiment are polygons. A texture image may be applied to the object using the definer/editor 44 to assign a texture coordinate pair within the pre-stored texture image to each vertex of each polygon in the object.

The definer/editor 44 is connected to the mass storage device 16 to enable data defining an object, light source and/or camera once defined, to be stored for subsequent use.

The definer/editor 44 is also connected to the input device 8 to enable an operator to input and/or amend an object, light source and/or camera.

Controller 48 is provided for enabling an operator to control the position and orientation of any object, light source and/or camera defined by editor 44. In particular, controller 48 may be operated by input means 8 to define a view position and view direction for a camera to view the 3D object(s).

Renderer 52 is arranged to perform calculations for the 3D object(s), light source(s) and camera defined and controlled by definer 44 and controller 48 to generate pixel data defining an image of the object(s) as seen by the camera.

The processing operations performed by renderer 52 include calculating specular lighting values for the polygons making up the 3D model(s) and, in this embodiment, using the calculated values to perform Phong shading. Renderer 52 performs processing operations in a conventional manner, for example as described in "Computer Graphics Principles and Practice" by Foley, van Dam, Feiner and Hughes, Addison-Wesley Publishing Company, second edition, 1990, ISBN 0-201-12110-7, with the exception of the specular lighting value calculations.

The way in which specular lighting values are calculated by renderer 52 in this embodiment will now be described.

Figure 3 illustrates an example of an object 110 defined in terms of polygons (triangles in this embodiment) of which five 112 to 120 are visible in Figure 3, to be rendered. one of the polygons 112, shown in grey, is def ined to be an imperf ect specularly ref lecting surf ace.

With reference to Figure 4, the principles underlying the Phong illumination model will now be described. The diagram shown in Figure 4 is a side view of the polygon 112 shown Figure 3. The surface normal N of the polygon 112 is also illustrated. The direction of light incident on the polygon from a previously mentioned point light source is represented by vector I at an angle 6 to the normal. A vector R is also marked on the diagram, at a direction opposite the direction of vector I from the normal, and this vector R represents the theoretical direction of reflection of light incident on the polygon surface from the light source. A vector V, at a further angle a from the reflected vector R represents the direction at which a viewer views the polygon illustrated in Figure 3.

12 As mentioned above, for a perfect specular reflector, all light incident on the surface in the direction of vector I would be reflected in the direction of vector R.

However, polygon 112 has a surface which is not a perfect reflector. Therefore, in the Phong illumination model, the intensity of light reflected in the direction of vector V is governed by an equation including the term COSNa.

N is a property of the material known as the specular reflection exponent, and Figures 5a, 5b and Sc illustrate examples of different values of cosla used in a model where N takes values of 1, 5 and 100 respectively. In Figure 5a, where N = 1, it can be seen that cos c( ranges is from a value of 1 where cx = 0 (i.e. V is coincident with R) to zero where a = n/2 (i.e. V is perpendicular to the theoretical reflective direction R). The transition between 1 and 0 is very gradual, representing reflection from the polygon which is not highly view dependent. 20 With reference to Figure 5b and Figure 5c, as N increases it can be seen that the transition of the value of the term COSNQ from 1 to 0 becomes steeper, and so the amount of illumination observed by a viewer becomes more dependent on the angle between the view direction V and 13 the theoretical reflection direction R. In Figure 5c, it can be seen that a polygon would appear very dark except in a very narrow range of angles around the theoretical reflection direction (the direction of vector R).

Figure 6 shows an arrangement of components in renderer 52 for performing the above described calculation involved in the Phong illumination model. This schematic arrangement can be implemented readily by the skilled person by dedicated hardware, or by programming a general purpose or specialised microprocessor.

Referring to Figure 6, block 200 evaluates the logarithm in base 2 of a received binary number A, which, in this embodiment, is the value cosa. In this block 200, register 202 stores the value of A (that is, cosa) in floating point format as shown in Figure 7a, function block 204 rounds the number stored in register 202 to ten significant figures, function block 206 looks up in a look up table 208 for the value of the logarithm in base 2 of the mantissa of the rounded value of A (as explained in further detail below), and the resultant value of 1092A is stored in fixed point form in register 210 as shown in Figure 7b.

14 Block 212 processes a received binary value of the power N to which A is to be raised. That is, in this embodiment, N is the specular reflection exponent for the polygon 112. N is received and stored in register 214 in floating point form as shown in Figure 7a, and function block 216 converts that floating point form into fixed point form, which is then stored in register 218 as shown in Figure 7b.

As noted above, in this embodiment, binary values defining cosa and the specular reflection exponent, N, are received and stored in registers 202 and 214 in floating point form (Figure 7a). The log look-up performed by block 206 results in a fixed point number is being stored in register 210 (Figure 7b) representing the value of 1092A, and the value of N is converted by block 216 from floating point to fixed point format and stored in register 218 (Figure 7b). In this way, as will be described below, a fixed point multiplication can be carried out.

More particularly, the contents of the registers 210 and 218, which are both in fixed point format, are multiplied in function block 220. The result of that integer multiplication is a fixed point number, which is placed in a 64 bit register 222 detailed in Figure 7c. The 42 least significant bits in that register are devoted to the fraction part of the product and the 22 most significant bits are devoted to the integer part of the product. The contents of register 222 are further processed in function block 224 by reference to a look up table 226 to find the antilog of the contents of register 222 in base 2. The result of the antilog computation is a floating point number, which is placed in register 228 as set out in Figure 7d.

Further details of the processing apparatus performed by renderer 52 to calculate cos"a will now be described with reference to Figures 8 to 13.

Referring to Figure 8, in step S10, the logarithm in base 2 of the f irst number A (that is cosa) is computed. A is initially in floating point form (Figure 7a), and the logarithm thereof is in fixed point form (Figure 7b).

In step S12, the second number (the power) N is converted f rom its initial f loating point f orm (Figure 7a) to f ixed point form. More particularly, N is converted from floating point to standard 14.18 fixed point notation (Figure 7b).That is, 14 bits are assigned to an integer 16 part of the number N and 18 bits are assigned to a fraction part of the number N.

In step S14, N (in fixed point form) is multiplied with 1092A (also in fixed point form). More particularly the contents of register 218 (which represents N) is multiplied by the contents of register 210 (which represents 1092A), and the result thereof is stored in fixed point notation in 22.42 format in register 222 (Figure 7c). Conveniently, this 64 bit word is stored in two 32 bit registers, with one of the registers set up as a 22.10 fixed point number and the other is set up as 32 bits representative of the least significant bits of the 64 bit word. That latter register is then discarded (as described in more detail later), since only the ten most significant bits of the mantissa of the number Nlo92A are required for the next stage.

In step S16, N1092A, which is presented in fixed point form, is processed to find the antilog thereof in base 2.

The result of that operation is output in step S18 and the method reaches a conclusion.

The processing operations performed at step S10 to calculate 1092A will now be described in more detail.

17 By way of background explanation, the floating point form of the value A can be written as:

A=mx2e.... (1) where "m" is the mantissa and "e" is the exponent of the number to base 2.

Accordingly, the logarithm of A is given by:

1092A=e+1092M.... (2) The way in which the above equations are used to calculate the value Of 1092A will now be described with reference to Figure 9.

In step S22, the value of A is received in floating point form and is placed in the register 202 (Figure 7a). The mantissa of A, which is 23 bits long, is identified in step S24, and the ten most significant bits thereof are selected. This is carried out by passing the contents of register 202 through a shift register which shifts the number by thirteen bits to the right, and the result thereof is masked by means of the performance of an AND operation with number 1023 (211-1). This selects the ten most significant bits of the mantissa, and sets all bits corresponding to the exponent part of the number to zero.

In step S26, the ten most significant bits selected at step S24 are mapped to an entry in the look up table 208, and the entry is read as the logarithm in base 2 of the rounded mantissa. In step S28, the result consisting of the entry in the look up table is placed in the fraction part of the fixed point register 210 (Figure 7b).

At step S30, the exponent part of the number A held in the floating point register 202 (Figure 7a) is transferred across to the integer part of the fixed point register 210 (Figure 7b). More particularly, the exponent part of the number A held in the floating point register 202 is unbiased by subtracting 127 therefrom.

This number is identified in hexadecimal notation as 3F800000. Thereafter, the exponent is shifted left by one bit, so as to move the exponent into the most significant eight bits of the word. The exponent constitutes the integer part of the logarithm of A, and so can be placed directly in the fixed point register 210 by step 30. Register 210 then contains a fixed point binary number representative of the logarithm in base 2 of the input number A rounded to ten significant bits.

The processing operations performed at step S16 in Figure 8 to calculate the antilog of N1092A will now be 19 described in more detail with reference to Figure 10.

By way of background explanation f irst, N1092A has the form of a f ixed point number, and accordingly can be written as follows:

N 1092 A = int + frac.... (3) Where "int" and "frac" represent the integer and fraction parts of the number, respectively.

Taking antilogs to base 2 therefore gives:

ANTILOG (N 1092 A). 2('t+frac) =2 int x2 frac.... (4) Referring to Figure 10, in step S40, the fraction part of N1092A stored in register 222 (Figure 7c) is identified and the 10 most significant bits thereof are identified.

More particularly, as described above, the 64 bit word representing the fixed point format of N1092A is stored in two 32 bit registers, with one of the registers set up as a 22.10 fixed point number and the other register set up as a 32 bit register to store the least significant bits of the 64 bit word. At step S40, the register containing the 32 least significant bits of the 64 bit word is discarded, and the ten most significant bits in the remaining register are isolated by applying a mask by means of an AND operation with the number 3FF (hexadecimal).

In step S42, the ten most significant bits identified at step S40 are applied to the look up table 226 to find the antilog thereof in base 2. The result of that antilog look up is placed in the 23 least significant bits of the register 228 illustrated in Figure 7d (step 44).

At step S46, the integer part of the value N1092A is identified from register 222 and placed in the exponent part of register 228. In practice, the integer part of the value N1092A will never occupy more than the 8 least significant bits allocated to the integer part in register 222 (Figure 7c). Accordingly, the exponent is isolated by shifting the most significant 32 bit word of the register 222 left to place the 8 bits of the integer part at the most significant end of the register. The integer is then re-biassed into 2's complement notation by the addition of number 127 thereto and the consequent exponent part of the result of the overall calculation is mixed with the mantissa in register 228 by mean of an OR operation.

In this embodiment, it is necessary to set up look-up 21 tables 208 and 226 to find logarithms and anti logarithms. Figure 11 shows a procedure for carrying out that preparatory step. Firstly, in step S50, a log look up table 208 is set up. Secondly, in step S60, an antilog look-up table 226 is set up. Then, the preparatory procedure is completed.

Figure 12 illustrates step S50 in more detail. Firstly, in step S52, 1024 table entries are allocated with numbers 0 to 1023. Then, in step S54, those table entries are assigned to a series of 1024 numbers equispaced in the range 1 to 2. At step S56, for each of those values, a standard accurate but slow base 2 logarithm function is applied and the result thereof is stored in the corresponding entry in the table 208.

Step S60 is described in more detail in Figure 14. In step S62, 1024 table entries are allocated with numbers 0 to 1023. Each entry is identified in step S64 with one of 1024 equispaced sub-divisions in the range 0 to 1.

For each sub-division, at step S66 a standard accurate but slow base-2 power function is performed and the result thereof is stored in the corresponding entry in the look up table 226.

22 In the embodiment above, binary values defining A (that is, cosa) and N are received and stored in registers 202 and 214 in floating point form. However, one or both of these values may be received in fixed point form, and processing operations carried out to determine whether the value of N is in floating point form and, if it is, to convert it from floating point form to fixed point form.

It has been observed in preliminary trials that the above described method and apparatus for calculating powers of numbers can operate up to seven times faster than conventional slow and accurate functions. Since, on two occasions in the procedure, numbers are rounded to ten significant figures, it will be appreciated that some error is likely to be encountered. However, it has also been observed that this error is unlikely to exceed 0.5%.

This is usually sufficiently accurate for most applications. in particular, in graphics applications, representation of specular reflection need not be calculated to that degree of accuracy, since the most important consideration is processing speed.

Accordingly, the present invention has specific application to the representation of visually realistic images, potentially in real time.

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Claims (23)

1 Apparatus for processing signals defining first and second numbers to generate a signal defining the value of the f irst number raised to the power of the second number, comprising:

means for receiving signals defining the first and second numbers in floating point form; logarithm computation means for computing a logarithm of the first number to give a f ixed point logarithm value; means for converting the second number from floating point f orm to f ixed point f orm; means for multiplying the fixed point logarithm is value with the fixed point value of the second number to give a fixed point multiplication result; and antilogarithm computation means for computing an antilogarithm in floating point form of the fixed point multiplication result.

2. Apparatus in accordance with claim 1, wherein the logarithm computation means is arranged to calculate the logarithm of the floating point form of the first number by assembling an exponent part of the first number as the integer part of the logarithm and identifying a logarithm 24 of a mantissa part of the floating point number as a fraction part of the logarithm.

3. Apparatus in accordance with claim 2, comprising first look up table means for reference by the logarithm computation means in the identification of a logarithm of the mantissa part.

4. Apparatus in accordance with claim 3, comprising means for rounding the mantissa before reference to the first look up table means.

5. Apparatus in accordance with any preceding claim, wh(---eir rie antilogarithm computation means is arranged to generate the antilogarithm of the fixed point multiplication result by assembling an integer part of the multiplication result as the exponent part of the antilogarithm and identifying an antilogarithm of a fraction part of the multiplication result as a mantissa part of the antilogarithm.

6. Apparatus in accordance with claim 5, comprising second look up table means for reference by the second computation means in the identification of an antilogarithm.

7. Apparatus in accordance with claim 6, comprising means for rounding the fraction part before reference to the second look up table means.

8. A method of processing signals defining first and second numbers to generate a signal defining the value of the first number raised to the power of the second number, comprising:

receiving signals defining the first and second numbers in floating point form; computing a logarithm of the first number to give a fixed point logarithm value; converting the second number from floating point form to fixed point form; multiplying the fixed point logarithm value with the f ixed point value of the second number to give a f ixed point multiplication result; and computing an antilogarithm in floating point form of the fixed point multiplication result.

9. A method in accordance with claim 8, wherein the step of computing the logarithm comprises:

selecting the exponent part of the f irst number as the integer part of the logarithm; and computing a logarithm of the mantissa part of the 26 first number as the f raction part of the logarithm.

10. A method in accordance with claim 9, wherein the step of computing the logarithm of the mantissa part comprises computing the value with reference to a look up table containing values representative of logarithms of numbers.

11. A method in accordance with claim 10, wherein the step of computing the logarithm further includes the step of rounding the mantissa part before referring to the look up table.

12. A method in accordance with any of claims 8 to 11, wherein the step of computing the antilogarithm comprises the steps of:

selecting the integer part of the multiplication result as the exponent part of the antilogarithm; and computing an antilogarithm of the fraction part of the multiplication result as the mantissa part of the antilogarithm.

13. A method in accordanc.- with claim 12, wherein the step of computing the antilogarithm of the fraction part computing the value with reference to a look up table 27 containing values representative of antilogarithms of numbers.

14. A method in accordance with claim 13, wherein the step of computing the antilogarithm includes the step of rounding the fraction part before referring to the look up table.

15. Apparatus for processing signals defining first and second numbers to generate a signal defining the value of the first number raised to the power of the second number, comprising:

logarithm computation means for computing a logarithm of the first number to give a fixed point logarithm value; means for converting the second number from floating point form to fixed point form if the second number is not already in fixed part form; means for multiplying the fixed point logarithm value with the fixed point value of the second number to give a multiplication result; and antilogarithm computation means for computing an antilogarithm of the multiplication result.

16. A method of processing signals defining first and 28 second numbers to generate a signal defining the value of the f irst number raised to the power of the second number, comprising:

computing a logarithm of the first number to give a fixed point logarithm value; converting the second number from floating point form to fixed point form if the second number is not already in fixed part form; multiplying the fixed point logarithm value with the fixed point value of the second number to give a multiplication result; and computing an antilogarithm of the multiplication result.

17. A method of generating pixel data by rendering an image of a three-dimensional computer model, in which specular lighting values are calculated using a method according to any of claims 8 to 14 and 16 and the pixel data is generated in dependence upon the calculated specular lighting values.

18. A storage medium storing instructions for causing a programmable processing apparatus to become configured as an apparatus in accordance with at least one of claims 1 to 7 and 15.

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19. A storage medium storing instructions for causing a programmable apparatus to become operable to perform a method in accordance with at least one of claims 8 to 14, 16 and 17.

20. A signal conveying instructions for causing a programmable processing apparatus to become conf igured as an apparatus in accordance with at least one of claims 1 to 7 and 15.

21. A signal conveying instructions for causing a programmable apparatus to become operable to perform a method in accordance with at least one of claims 8 to 14, 16 and 17.

22. Apparatus for calculating the value of a first number raised to the power of a second number substantially as described herein with reference to, or as shown in, the accompanying drawings.

23. A method of calculating the value of a first number raised to the power of a second number substantially as described herein with reference to, or as shown in, the accompanying drawings.