JPH10200393A - Signal monitor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the signal monitor circuit that operates accurately a receiver side system which receives and processes an input signal with a rebound. SOLUTION: The signal monitor that detects an initial point of time in the operating state of a 2nd system when an input signal with a rapid rebound enters a 2nd system from a 1st system, is made up of a 1st logic gate section 20 attenuating the rebound of the input signal and up of 2nd logic gate sections 30-48 that detect a time when logic transition of the input signal first takes place from an output of the 1st logic gate section 20 and informs of the detection of the point of initial time of the operating state to the 2nd system. Then a low level produced on the occurrence of the rebound in the input signal is kept and when high level transition takes place on the occurrence of 2nd rebound, a sampling rate by a clock is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal monitoring circuit, and more particularly to a signal monitoring circuit for preventing a system from malfunctioning due to rebound of an input signal.

[0002]

2. Description of the Related Art In general, in a technique for transmitting a signal between systems without performing signal modulation, a signal is directly input to an input signal processing block in a receiving-side system.

FIG. 1 is a block diagram showing signal transmission between conventional systems. As shown in FIG. 1, when a signal is transmitted from the transmission side system A2 through the transmission line 3, an input signal received without performing signal sampling or the like is received by the reception side system B4. It is applied directly to the signal processing block 6.

As shown in an input waveform of FIG. 4, a signal transmission line 3 is connected to a non-operating section t where no input signal is applied.
The logic "H (high)" state is maintained at 1 and t3. On the other hand, in the operation period t2 in which an input is applied from the system A2 to the transmission line 3, the transmission line 3 transitions from logic “H” to logic “L (low)”. The input signal processing block 6 of the system B4 starts operation in synchronization with this transition point, and performs signal processing by regarding the rest as an input signal from A2.

[0005]

In the above-mentioned conventional signal transmission, rebounding immediately after signal input causes a malfunction of a receiving system. Here, rebound means a state in which an extremely high frequency component in a signal changes its center frequency value as needed. For example, in the system of FIG. 1, when a signal having a rebound is directly applied to the input signal processing block 6 as described above, the input signal processing block 6, which should start operating in synchronization with the transition of the input, malfunctions. In some cases, the system B4 on the receiving side cannot be correctly linked with the system A2 on the transmitting side.

As shown in the input waveform of FIG. 4, in the initial period of the input signal in the operation period t2, the period t4 in which the signal transitions between logic "H" and "L" is usually several μsec.
There is only about c, but this is the rebound occurrence section. The operating speed in these systems is several nsec.
And the inputs to the receiving system are logic "H" and "L".
The rebound in the t4 interval that transitions between the above causes the system malfunction as described above.

SUMMARY OF THE INVENTION The present invention provides a signal monitoring circuit for accurately operating a receiving system that receives and processes a rebounded input signal.

[0008]

According to the present invention, there is provided:
When the input signal retains a low level value generated after rebound and transitions to high while rebounding again, the sampling rate by the clock is reduced, thereby providing a more accurate input signal value to the input signal processing block.

That is, according to the present invention, when an input signal having a strong rebound enters the second system from the first system, the signal monitor circuit for detecting the first point of the operating state of the second system attenuates the rebound of the input signal. A first logic gate section for causing a first logic gate section to detect when a logic transition of an input signal first occurs from an output of the first logic gate section, and notify a second system of detecting a first point in time of an operation state; And a signal monitoring circuit including a gate unit.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing signal transmission between the systems of the present invention. The receiving-side system B4 includes a signal monitoring circuit 10 for detecting a point in time when the input signal first transitions to the logic “L”. This signal monitoring circuit 1
0 provides the input signal processing block 6 by providing the row transition detection signal LTDS to the input signal processing block 6.
However, the input signal is processed after the rebound period to prevent the malfunction of B4.

FIG. 3 is a circuit diagram of the signal monitoring circuit 10, which comprises a plurality of logic gates 22 to 34 and 38 to 46 and two flip-flops 36 and 48. Among these logic gates, the logic gate unit including the two NAND gates 24 and 26 is the rebound attenuation circuit unit 20 that attenuates rebound. The NAND gate 24 has one input terminal connected to the output terminal of the inverter 22 receiving the input signal, the other input terminal connected to the output terminal of the NAND gate 26, and the output terminal connected to the NAND gate 26.
The gate 26 is connected to one input terminal. An input signal is applied to the other input terminal of the NAND gate 26, and the output terminal is connected to the other input terminal of the NAND gate 24 and to the input terminal of the inverter 28. Attenuation of the rebound by the rebound attenuation circuit 20 means that a state in which the frequency is different instantaneously is made maximum and constant, and that the rebound state is shaped into logic "H" and "L". The input signal is subjected to primary rebound attenuation in the rebound attenuation circuit unit 20, and then to the rear end logic gates 28 to
34, 38 to 46 and two flip-flops 36, 48
(Sampling by a clock) is performed, and the row transition detection signal LTD of the output signal is
Generate S.

FIG. 4 shows an input signal (INPUT) with rebound.
SIGNAL) and various signals used in the circuit of this example, that is, a clock signal CLK, a row transition detection signal LTDS, and a control signal CTS. The signals applied to the signal monitoring circuit 10 are an input signal, CLK, and CTS provided by the system A2, and the signal output from the signal monitoring circuit 10 is LTDS. In the non-operation period t1, the input signal is at logic “H”, and the CTS is also at logic “H”. The signal output from the inverter 38 and fed back is also at the logic "H". On the other hand, in the operation period t2, each of the input signal, CLK, LTDS, and CTS transitions from the logic state in the non-operation period t1.

Referring to FIGS. 3 and 4, signal monitoring circuit 10
Will be described. The logic state of each gate in the non-operation interval t1 is as follows. CTS is “H”, N
The output of the OR gate 42 is "L", the output of the OR gate 44 is "L", the output of the AND gate 46 is "L", and the output of the D-type flip-flop 48 is "L". Since the input signal is “H” and the output of the inverter 22 is “L”,
The output of the NAND gate 24 is “H”, and the NAND gate 2
6 is "L", the output of inverter 28 is "H", N
The output of the OR gate 32 is "L", the output of the inverter 40 is "L", and the output of the AND gate 34 is also "L". Since the D-type flip-flop 36 that performs a latch operation in response to the clock signal CLK is also “L”, the inverter 38
The LTDS obtained as the output of is “H”.

On the other hand, when the operation shifts from the non-operation period t1 to the operation period t2, the input signal includes several μs as shown in the period t4 in FIG.
During "ec", "H" changes to "L", and "L" changes to "H".
Rebound occurs. At this time, the rebound attenuation circuit unit 20 attenuates the rebound of the input signal to a first order. Attenuation of the rebound by the rebound attenuation circuit 20 means that a state in which the frequency is different instantaneously is made maximum and constant, and that the rebound state is shaped into logic "H" and "L". The rebound attenuating circuit unit 20 makes the instantaneous frequency different from each other to the maximum level, because the rebound signal component of the applied input signal
Propagation delay (pr) inherent to NAND gates 24 and 26
This is performed by eliminating signal components having a signal rate faster than the operation delay by the propagation delay. The rebound attenuating circuit unit 20 shapes the rebound state to the logic “H” and “L” by shaping a signal component having a signal rate slower than the propagation delay of the NAND gates 24 and 26 itself. .

During the operation period t2, the input signal is several μsec.
After (t4), when the state changes to the “L” state, the output of the NAND gate 26 changes to “H” and the output of the inverter 22 also changes to “H”. The output of the inverter 28 receiving the output "H" becomes "L". The output of the NOR gate 32 is "H" and the output of the inverter 40 is "H".
Therefore, the output of the AND gate 34 is "H".

After time t5 from the start of operation section t2, C
LK first transitions from “L” to “H”, whereby the D-type flip-flop 36 latches the input output signal “H” of the AND gate 34. Therefore, the output of the D-type flip-flop 36 is "H" and the inverter 38
Becomes "L", so that the LTDS
Changes to the "L" state.

When CTS changes from "H" to "L" at a timing t6 after t5 in the operation section t2, and when CLK changes from "L" to "H" for the second time, the latch operation is performed. The outputs of the D-type flip-flop 48 are "L", N
The output of the OR gate 32 changes to "H" and the output of the AND gate 34 changes to "L".

Thereafter, when CLK transitions from the logic "L" to "H" for the third time, the output of the D-type flip-flop 36 which performs a latch operation thereby becomes the logic "L" and the output of the inverter 38 becomes the logic "H". ", The row transition detection signal LTDS changes to the logical" H "state.

By the above operation, the operation interval t2
In the first t4 section, the rebound of the input signal is ignored, and the signal is changed by transitioning the LTDS to “L” in the operation section t2 based on the stable logic state of the input signal and the logic states of CLK and CTS. Start the processing operation. That is, since the first low signal is detected only once from an input signal with a sharp rebound, a signal indicating the operation state is accurately detected, and a system malfunction is prevented.

[0021]

According to the present invention, there is provided a signal monitoring circuit for detecting an initial time point of an operation state when an input signal having a rebound is severely received, so that a signal can be detected accurately. No malfunction occurs in a system that receives and processes signals.

[Brief description of the drawings]

FIG. 1 is a block diagram showing signal transmission between conventional systems.

FIG. 2 is a block diagram showing signal transmission between systems of the present invention.

FIG. 3 is a circuit diagram of the signal monitoring circuit 10;

FIG. 4 shows a rebound input signal, a clock signal CL.
9 is a time chart showing K, a row transition detection signal LTDS, and a control signal CTS.

[Description of Signs] 6 Input signal processing block 10 Signal monitoring circuit 20 Rebound attenuating circuit section 22, 28, 38, 40 inverter 24, 26 NAND gate 32, 42 NOR gate 44 OR gate 30, 34, 46 AND gate 36, 48 D-type flip-flop

Claims (1)

[Claims] 1. A signal monitoring circuit for detecting an initial state of an operation state of a second system when an intense rebound input signal is input from a first system to a second system, wherein the first circuit attenuates the rebound of the input signal. A logic gate unit, and a second logic gate unit that detects when a logic transition of an input signal first occurs from an output of the first logic gate unit, and notifies a second system that the first point in time of the operating state has been detected. , A signal monitoring circuit.