JPH10199921A - Semiconductor device having position-recognition mark - Google Patents
Semiconductor device having position-recognition markInfo
- Publication number
- JPH10199921A JPH10199921A JP9001834A JP183497A JPH10199921A JP H10199921 A JPH10199921 A JP H10199921A JP 9001834 A JP9001834 A JP 9001834A JP 183497 A JP183497 A JP 183497A JP H10199921 A JPH10199921 A JP H10199921A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- bonding pad
- bonding
- recognition
- position recognition
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【０００１】[0001]
【発明が属する技術分野】本発明は、半導体装置に関
し、特に、半導体チップの素子形成面（主面）上に、ワ
イヤーボンディング時にボンディングパッドの位置を認
識するための位置認識用マークが設けられた導体装置に
適用して有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor chip provided with a position recognition mark for recognizing a position of a bonding pad during wire bonding on an element formation surface (main surface) of the semiconductor chip. The present invention relates to a technology effective when applied to a conductor device.
【０００２】[0002]
【従来の技術】従来、半導体チップの主面上に、ワイヤ
ーボンディング時にボンディングパッドの位置を認識す
るために所定のボンディングパッドを基準として位置認
識を行うか又は位置認識用マークを設けてボンディング
パッドの位置の認識を行っていた。2. Description of the Related Art Conventionally, on a main surface of a semiconductor chip, position recognition is performed with reference to a predetermined bonding pad in order to recognize the position of the bonding pad at the time of wire bonding, or a position recognition mark is provided to provide a position recognition mark. The position was recognized.
【０００３】[0003]
【発明が解決しようとする課題】本発明者は、前記従来
の技術を検討した結果、以下の問題点を見いだした。SUMMARY OF THE INVENTION The present inventor has found the following problems as a result of studying the above conventional technology.
【０００４】絶縁性保護膜（例えば、ポリイミド イソ
インドロ キナゾリンジオン:ＰＩＱ）の膜厚が１０μｍ
と厚い場合、前記絶縁性保護膜（以下、単にＰＩＱと称
する）の開口部の影によりその縁が黒く見え、これが前
記位置認識用マークの認識の邪魔をして認識できない場
合が生じるため、ワイヤーボンディング装置が頻繁に停
止するという問題があった。The thickness of an insulating protective film (for example, polyimide isoindoloquinazolinedione: PIQ) is 10 μm.
When the thickness is too thick, the edge looks black due to the shadow of the opening of the insulating protective film (hereinafter simply referred to as PIQ), and this may interfere with the recognition of the position recognition mark and may not be recognized. There is a problem that the bonding apparatus frequently stops.
【０００５】そこで、開口寸法を大きくとれば、ＰＩＱ
の開口部の縁がカメラの認識エリアからはずれてしまう
ため、認識の阻害とはならないが、保護膜としての役割
が阻害されるため、最適な寸法を出す必要があった。Therefore, if the size of the opening is increased, the PIQ
Since the edge of the opening is not in the recognition area of the camera, it does not hinder the recognition. However, the role of the protective film is hindered, so that it is necessary to provide an optimum dimension.
【０００６】本発明の目的は、位置認識用マークの認識
を確実にしてワイヤーボンディング装置が頻繁に停止す
るのを防止することが可能な技術を提供することにあ
る。An object of the present invention is to provide a technique capable of reliably recognizing a position recognition mark and preventing the wire bonding apparatus from frequently stopping.
【０００７】本発明の前記ならびにその他の目的と新規
な特徴は、本明細書の記述及び添付図面から明らかにな
るであろう。[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
【０００８】[0008]
【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば下
記のとおりである。SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones will be briefly described as follows.
【０００９】（１）半導体チップの主面上に、ワイヤー
ボンディング時にボンディングパッドの位置を認識する
ための位置認識用マークを設けた半導体装置であって、
前記ボンディングパッドの通常の規定寸法の大きさのパ
ターンに突起パターンを付加し、この突起付きパターン
のボンディングパッドを位置認識用マーク兼用のボンデ
ィングパッドとしたものである。(1) A semiconductor device having a position recognition mark for recognizing a position of a bonding pad at the time of wire bonding on a main surface of a semiconductor chip,
A projection pattern is added to a pattern having a normal specified size of the bonding pad, and the bonding pad of the pattern with the projection is used as a bonding pad also serving as a position recognition mark.
【００１０】（２）半導体チップの主面上に、ワイヤー
ボンディング時にボンディングパッドの位置を認識する
ための位置認識用マークを設けた半導体装置であって、
前記ボンディングパッドの通常の規定寸法の大きさのパ
ターンに突起パターンを付加し、この突起付きパターン
のボンディングパッドを位置認識用マーク兼用のボンデ
ィングパッドとし、該ボンディングパッドを所定の距離
だけ離れた位置にペアで設置したものである。(2) A semiconductor device having a position recognition mark for recognizing a position of a bonding pad at the time of wire bonding on a main surface of a semiconductor chip,
A projection pattern is added to a pattern having a normal specified size of the bonding pad, the bonding pad of the pattern with the projection is used as a bonding pad also serving as a position recognition mark, and the bonding pad is placed at a position separated by a predetermined distance. It is installed in pairs.
【００１１】（３）前記突起パターンの突出の方向を同
じにしたものである。(3) The direction of projection of the projection pattern is the same.
【００１２】（４）前記突起付きパターンのボンディン
グパッド部のＰＩＱの開口寸法をほぼ２００μｍ×３５
０μｍとしたものである。(4) The opening dimension of the PIQ in the bonding pad portion of the pattern with protrusions is set to approximately 200 μm × 35.
It was set to 0 μm.
【００１３】前記の手段によれば、ボンディングパッド
の通常の規定寸法の大きさのパターンに突起パターンを
付加し、この突起付きパターンのボンディングパッドを
位置認識用マーク兼用のボンディングパッドとし、該ボ
ンディングパッド部の保護膜の開口寸法を、ほぼ２００
μｍ×３５０μｍとしたことにより、ＰＩＱの開口部の
縁の影が、位置認識用マークの認識の邪魔をしないの
で、製品の品質を低下させることなく、位置認識用マー
クの認識を確実にでき、ワイヤーボンディング装置が頻
繁に停止するのを防止することができる。According to the above-mentioned means, a projection pattern is added to a pattern having a normal prescribed size of the bonding pad, and the bonding pad of the pattern with the projection is used as a bonding pad also serving as a position recognition mark. The opening size of the protective film of the
By setting μm × 350 μm, the shadow of the edge of the opening of the PIQ does not hinder the recognition of the position recognition mark, so that the position recognition mark can be reliably recognized without lowering the quality of the product. Frequent stoppage of the wire bonding apparatus can be prevented.
【００１４】また、半導体チップのコーナーのＰＩＱを
残している。これは封止樹脂（レジン）と半導体チップ
との剥離の防止、及び外部より内部への水分の侵入を防
止するためである。Further, the PIQ at the corner of the semiconductor chip is left. This is to prevent the sealing resin (resin) from peeling off from the semiconductor chip and to prevent moisture from entering the inside from the outside.
【００１５】また、突起付きパターンのボンディングパ
ッドは、ボンディングだけでなく半導体チップを切断す
るとき、その切断位置の認識にも使用するが、その場
合、全く同じ形状のものを用いると、２個のうちどちら
の突起付きパターンのボンディングパッドかわからな
い。そこで、全く同形状とならないように突起を辺の別
方向に付けるようにする。The bonding pads of the pattern with projections are used not only for bonding but also for recognizing the cutting position when cutting a semiconductor chip. I do not know which of the bonding pads has the projection pattern. Therefore, the projections are provided in different directions of the sides so as not to have the same shape.
【００１６】以下、本発明について、図面を参照して実
施の形態とともに詳細に説明する。Hereinafter, the present invention will be described in detail along with embodiments with reference to the drawings.
【００１７】なお、実施の形態を説明するための全図に
おいて、同一機能を有するものは同一符号を付け、その
繰り返しの説明は省略する。In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.
【００１８】[0018]
（実施形態１）図１は本発明の実施形態１による周辺パ
ッド型半導体集積回路装置の概略構成を示す平面図、図
２は図１の突起付きパターンのボンディングパッドの詳
細な構成を示す平面図、図３は実施形態１による周辺パ
ッド型半導体集積回路装置の全体概略構成を示す断面図
である。図１乃至図３において、１は半導体チップ、２
は絶縁性保護膜（例えば、ＰＩＱ等を用いる）、３は通
常のボンディングパッド、４，５は突起付きパターンの
ボンディングパッド（位置認識用マーク兼用のボンディ
ングパッド）、６はＰＩＱ２の開口部、７はリード、７
Ａはタブ、８はボンディングワイヤ、９は封止樹脂であ
る。(Embodiment 1) FIG. 1 is a plan view showing a schematic configuration of a peripheral pad type semiconductor integrated circuit device according to Embodiment 1 of the present invention, and FIG. 2 is a plan view showing a detailed configuration of a bonding pad of a pattern with projections in FIG. FIG. 3 is a sectional view showing the overall schematic configuration of the peripheral pad type semiconductor integrated circuit device according to the first embodiment. 1 to 3, reference numeral 1 denotes a semiconductor chip;
Is an insulating protective film (for example, using a PIQ or the like), 3 is a normal bonding pad, 4 and 5 are bonding pads of a pattern with projections (bonding pads also serving as position recognition marks), 6 is an opening of PIQ2, 7 Is the lead, 7
A is a tab, 8 is a bonding wire, and 9 is a sealing resin.
【００１９】図１に示すように、本実施形態１による周
辺パッド型半導体集積回路装置は、半導体チップ１の主
面上に、ワイヤーボンディング時にボンディングパッド
の位置を認識するための突起付きパターンのボンディン
グパッド４，５を所定の距離だけ離れた位置にペアで設
けられている。そして、前記突起付きパターンのボンデ
ィングパッド４，５の部分のＰＩＱ２の開口部６のそれ
ぞれの寸法は、ほぼ２００μｍ×３５０μｍとしてあ
る。この開口部６の寸法の２００μｍ×３５０μｍは、
ＰＩＱ２の開口部６の膜の厚さが１０μｍの場合におけ
るＰＩＱ２の開口部６の縁の影が、突起付きボンディン
グパッド４の位置認識用マークの認識の邪魔をしない最
小限の寸法である。また、前記突起付きパターンのボン
ディングパッド４，５は、ＰＩＱ２の開口部６の縁から
５０μｍ以上離れた位置に配設されている。As shown in FIG. 1, in the peripheral pad type semiconductor integrated circuit device according to the first embodiment, a pattern with a projection for recognizing the position of a bonding pad at the time of wire bonding is formed on a main surface of a semiconductor chip 1. The pads 4 and 5 are provided as a pair at positions separated by a predetermined distance. The dimensions of the openings 6 of the PIQ 2 at the bonding pads 4 and 5 of the pattern with projections are approximately 200 μm × 350 μm. The size of the opening 6 of 200 μm × 350 μm is
When the thickness of the film of the opening 6 of the PIQ 2 is 10 μm, the shadow of the edge of the opening 6 of the PIQ 2 is the minimum dimension that does not hinder the recognition of the position recognition mark of the bonding pad 4 with projections. Further, the bonding pads 4 and 5 of the pattern with protrusions are arranged at positions at least 50 μm away from the edge of the opening 6 of the PIQ 2.
【００２０】前記突起付きパターンのボンディングパッ
ド４，５は、例えば、図２（ａ），（ｂ）に示すよう
に、前記通常のボンディングパッド３の通常の規定寸法
（例えば、９０μｍ×９０μｍ）の大きさのパターンに
突起パターン４Ａ（例えば６０μｍ×４０μｍ），５Ａ
（例えば４０μｍ×６０μｍ）を付加したものである。
この突起付きパターンのボンディングパッド４，５は、
通常のボンディングパッド３を形成する工程で同時に作
製する。As shown in FIGS. 2A and 2B, for example, the bonding pads 4 and 5 of the pattern with protrusions have a normal specified dimension (for example, 90 μm × 90 μm) of the normal bonding pad 3. Protrusion patterns 4A (for example, 60 μm × 40 μm), 5A
(For example, 40 μm × 60 μm).
The bonding pads 4 and 5 of the pattern with protrusions
It is manufactured at the same time as the step of forming a normal bonding pad 3.
【００２１】前記突起付きパターンのボンディングパッ
ド４，５の突起の方向を同じにする。図１では突起パタ
ーン４Ａもしくは５Ａはそれぞれ下向きになっている。
また、前記突起付きパターンのボンディングパッド４，
５の部分のＰＩＱ２の開口部６の寸法は、ほぼ２００μ
ｍ×３５０μｍとしてある。The directions of the protrusions of the bonding pads 4 and 5 of the pattern with protrusions are made the same. In FIG. 1, each of the protrusion patterns 4A and 5A is directed downward.
Also, the bonding pads 4 of the pattern with projections
The size of the opening 6 of the PIQ 2 in the portion 5 is approximately 200 μm.
m × 350 μm.
【００２２】また、半導体チップ１のコーナーのＰＩＱ
２は少し残す。これは、封止樹脂（レジン）と半導体チ
ップ１の剥離防止、及び外部より内部への水分の侵入を
防止するためである。The PIQ at the corner of the semiconductor chip 1
Leave 2 a little. This is to prevent the peeling of the sealing resin (resin) from the semiconductor chip 1 and to prevent moisture from entering the inside from the outside.
【００２３】また、突起付きパターンのボンディングパ
ッド４，５は、ボンディングだけでなく半導体チップを
切断するとき、その切断位置の認識にも使用するが、そ
の場合、全く同じ形状のものを用いると、２個のうちど
ちらの突起付きパターンのボンディングパッドかわから
ない。そこで、全く同一形状とならないように、突起４
Ａもしくは５Ａを辺の別方向に付けるようにする。The bonding pads 4 and 5 of the pattern with projections are used not only for bonding but also for recognizing the cutting position when cutting a semiconductor chip. It is not known which of the two bonding pads has the projected pattern. Therefore, the projection 4
A or 5A is attached in another direction of the side.
【００２４】前述の説明からわかるように、本実施形態
１によれば、突起付きパターンのボンディングパッド
４，５を位置認識用マーク兼用のボンディングパッドと
し、該ボンディングパッド４，５の部分のＰＩＱ２の開
口部６の寸法を、ほぼ２００μｍ×３５０μｍにするこ
とにより、ＰＩＱ２の開口部６の縁の影が、突起パター
ン（位置認識用マーク）の認識の邪魔をしないので、製
品の品質を低下させることなく、位置認識用マークの認
識を確実にでき、ワイヤーボンディング装置が頻繁に停
止するのを防止することができる。As can be seen from the above description, according to the first embodiment, the bonding pads 4 and 5 of the pattern with projections are used as the bonding pads also serving as position recognition marks, and the PIQ 2 By setting the size of the opening 6 to approximately 200 μm × 350 μm, the shadow of the edge of the opening 6 of the PIQ 2 does not disturb the recognition of the projection pattern (the mark for position recognition). Therefore, it is possible to reliably recognize the position recognition mark and prevent the wire bonding apparatus from frequently stopping.
【００２５】なお、前記ＰＩＱ２の開口部６の大きさは
製品の品質を低下させない面積であれば、２００μｍ以
上×３５０μｍ以上のものであってもよい。The size of the opening 6 of the PIQ 2 may be 200 μm or more × 350 μm or more as long as the area does not deteriorate the quality of the product.
【００２６】（実施形態２）図４は本発明の実施形態２
によるセンターパッド型半導体集積回路装置の概略構成
を示す平面図であり、７はリード、８はボンディングワ
イヤである。(Embodiment 2) FIG. 4 shows Embodiment 2 of the present invention.
1 is a plan view showing a schematic configuration of a center pad type semiconductor integrated circuit device according to the present invention, wherein 7 is a lead, and 8 is a bonding wire.
【００２７】本実施形態２のセンターパッド型半導体集
積回路装置は、図４に示すように、突起付きパターンの
ボンディングパッド４，５を配設するためのＰＩＱ２の
開口部６を半導体チップ１のセンターに所定の距離だけ
離した位置に２個所設けたものである。この開口部６の
寸法は、ほぼ２００μｍ×３５０μｍとしてある。この
開口部６の寸法は、製品の品質を低下させない面積であ
れば、２００μｍ以上×３５０μｍ以上のものであって
もよい。又、突起付きパターンのボンディングパッド
４，５周辺のＰＩＱ１０を残し、チップ内部への水分の
侵入を防ぐようにする。In the center pad type semiconductor integrated circuit device according to the second embodiment, as shown in FIG. 4, the opening 6 of the PIQ 2 for arranging the bonding pads 4 and 5 of the pattern with projections is formed in the center of the semiconductor chip 1. Are provided at two positions separated by a predetermined distance from each other. The dimensions of the opening 6 are approximately 200 μm × 350 μm. The size of the opening 6 may be 200 μm or more × 350 μm or more as long as the area does not deteriorate the quality of the product. Also, the PIQ 10 around the bonding pads 4 and 5 of the pattern with projections is left to prevent the intrusion of moisture into the chip.
【００２８】前記以外の構成及び作用効果は前記実施形
態１と同様のものである。The configuration, operation and effect other than the above are the same as those of the first embodiment.
【００２９】以上、本発明者によってなされた発明を前
記実施形態に基づき具体的に説明したが、本発明は、前
記実施例に限定されるものではなく、その要旨を逸脱し
ない範囲において種々変更可能であることは勿論であ
る。Although the invention made by the inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the invention. Of course, it is.
【００３０】例えば、前記位置認識用マーク兼用のボン
ディングパッドの形状、スペース、ＰＩＱ２の開口部の
大きさ、その設置位置等は、本発明の技術思想を逸脱し
ない範囲で種々変更し得ることはいうまでもない。For example, it can be said that the shape and space of the bonding pad also serving as the position recognition mark, the size of the opening of the PIQ 2, the installation position thereof, and the like can be variously changed without departing from the technical idea of the present invention. Not even.
【００３１】[0031]
【発明の効果】本願において開示される発明のうち代表
的なものによって得られる効果を簡単に説明すれば、下
記のとおりである。The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
【００３２】（１）突起付きパターンのボンディングパ
ッドを位置認識用マーク兼用のボンディングパッドと
し、この突起付きパターンのボンディングパッド部の絶
縁性保護膜の開口寸法を、ほぼ２００μｍ×３５０μｍ
とすることにより、絶縁性保護膜の開口部の縁の影が、
位置認識用マークの認識の邪魔をしないので、製品の品
質を低下させることなく、位置認識用マークの認識を確
実にでき、ワイヤーボンディング装置が頻繁に停止する
のを防止することができる。(1) The bonding pad of the pattern with projections is used as a bonding pad also serving as a mark for position recognition, and the opening dimension of the insulating protective film at the bonding pad portion of the pattern with projections is approximately 200 μm × 350 μm.
By doing, the shadow of the edge of the opening of the insulating protective film,
Since it does not hinder the recognition of the position recognition mark, the position recognition mark can be reliably recognized without deteriorating the quality of the product, and the wire bonding apparatus can be prevented from frequently stopping.
【００３３】（２）突起付きボンディングパッド所定の
距離だけ離れた位置にペアで設置したことにより、半導
体チップの向き等の認識を確実に行うことができる。(2) The bonding pads with projections are installed in pairs at predetermined positions apart from each other, so that the orientation of the semiconductor chip can be reliably recognized.
【００３４】（３）半導体チップコーナーの保護膜（Ｐ
ＩＱ）を残し、封止樹脂（レジン）と半導体チップの剥
離を防止するとともに、外部から内部への水分の侵入を
防止することができる。(3) Protective film (P
IQ) can be left to prevent peeling of the sealing resin (resin) and the semiconductor chip, and also prevent intrusion of moisture from the outside to the inside.
【図１】本発明の実施形態１による周辺パッド型半導体
集積回路装置の概略構成を示す平面図である。FIG. 1 is a plan view showing a schematic configuration of a peripheral pad type semiconductor integrated circuit device according to a first embodiment of the present invention.
【図２】本実施形態１の突起付きボンディングパッドの
詳細な構成を示す平面図である。FIG. 2 is a plan view illustrating a detailed configuration of a bonding pad with projections according to the first embodiment.
【図３】本実施形態１による周辺パッド型半導体集積回
路装置の概略構成を示す断面図である。FIG. 3 is a sectional view showing a schematic configuration of a peripheral pad type semiconductor integrated circuit device according to the first embodiment.
【図４】本発明の実施形態２によるセンターパッド型半
導体集積回路装置の概略構成を示す平面図である。FIG. 4 is a plan view showing a schematic configuration of a center pad type semiconductor integrated circuit device according to a second embodiment of the present invention.
１…半導体チップ、２…ＰＩＱ、３…通常のボンディン
グパッド、４，５…突起付きパターンのボンディングパ
ッド、６…ＰＩＱの開口部、７…リード、７Ａ…タブ、
８…ボンディングワイヤ、９…封止樹脂、１０…周辺Ｐ
ＩＱ。DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 2 ... PIQ, 3 ... Normal bonding pad, 4, 5 ... Bonding pad of a pattern with a protrusion, 6 ... Opening of PIQ, 7 ... Lead, 7A ... Tab,
8 bonding wire, 9 sealing resin, 10 peripheral P
IQ.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 渡辺 宏 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 紺野 順平 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体事業部内 (72)発明者 石井 康 東京都青梅市藤橋３丁目３番地２ 日立東 京エレクトロニクス株式会社内 (72)発明者 鈴木 一成 東京都小平市上水本町５丁目22番１号 株 式会社日立マイコンシステム内 (72)発明者 増田 正親 東京都小平市上水本町五丁目20番１号 株 式会社日立製作所半導体事業部内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Watanabe 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. No. 20-1, Hitachi Semiconductor Co., Ltd. Semiconductor Division (72) Inventor Yasushi Ishii 3-3-2 Fujibashi, Ome-shi, Tokyo Within Hitachi Tokyo Electronics Co., Ltd. (72) Inventor Kazunari Suzuki, Kodaira-shi, Tokyo 5-22-1, Mizumoto-cho, Hitachi Microcomputer System Co., Ltd. (72) Inventor Masachika Masuda 5-2-1, Kamimizu-Honcho, Kodaira-shi, Tokyo Semiconductor Company, Hitachi, Ltd.
Claims (4)
ーボンディング時にボンディングパッドの位置を認識す
るための位置認識用マークを設けた半導体装置であっ
て、前記ボンディングパッドの通常の規定寸法の大きさ
のパターンに突起パターンを付加し、この突起付きパタ
ーンのボンディングパッドを位置認識用マーク兼用のボ
ンディングパッドとしたことを特徴とする位置認識用マ
ーク付半導体装置。1. A semiconductor device having a position recognition mark for recognizing a position of a bonding pad at the time of wire bonding on an element forming surface of a semiconductor chip, wherein the bonding pad has a size of a normal specified dimension. A semiconductor device with a mark for position recognition, characterized in that a protrusion pattern is added to the pattern of (1), and the bonding pad of the pattern with protrusion is used as a bonding pad that also serves as a mark for position recognition.
ーボンディング時にボンディングパッドの位置を認識す
るための位置認識用マークを設けた半導体装置であっ
て、前記ボンディングパッドの通常の規定寸法の大きさ
のパターンに突起パターンを付加し、この突起付きパタ
ーンのボンディングパッドを位置認識用マーク兼用のボ
ンディングパッドとし、該ボンディングパッドを所定の
距離だけ離れた位置にペアで設置したことを特徴とする
位置認識用マーク付半導体装置。2. A semiconductor device having a position recognition mark for recognizing a position of a bonding pad at the time of wire bonding on an element formation surface of a semiconductor chip, the bonding pad having a size of a normal specified dimension. A position recognition method characterized in that a protrusion pattern is added to the pattern of (1), the bonding pad of the pattern with the protrusion is used as a bonding pad also serving as a mark for position recognition, and the bonding pads are installed in pairs at a predetermined distance from each other. Semiconductor device with marking for use.
たことを特徴とする請求項２に記載の位置認識用マーク
付半導体装置。3. The semiconductor device with a mark for position recognition according to claim 2, wherein the projecting patterns have the same projecting direction.
ッド部の絶縁性保護膜の開口寸法をほぼ２００μｍ×３
５０μｍとしたことを特徴とする請求項１乃至３のうち
いずれか１項に記載の位置認識用マーク付半導体装置。4. The size of the opening of the insulating protective film in the bonding pad portion of the pattern with protrusions is approximately 200 μm × 3.
The position-recognition-marked semiconductor device according to any one of claims 1 to 3, wherein the thickness is set to 50 µm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP00183497A JP3535683B2 (en) | 1997-01-09 | 1997-01-09 | Semiconductor device with position recognition mark |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP00183497A JP3535683B2 (en) | 1997-01-09 | 1997-01-09 | Semiconductor device with position recognition mark |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10199921A true JPH10199921A (en) | 1998-07-31 |
| JP3535683B2 JP3535683B2 (en) | 2004-06-07 |
Family
ID=11512597
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP00183497A Expired - Fee Related JP3535683B2 (en) | 1997-01-09 | 1997-01-09 | Semiconductor device with position recognition mark |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3535683B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1269540A1 (en) * | 2000-03-09 | 2003-01-02 | Silverbrook Research Pty. Limited | Modular printhead alignment system |
| JP2006502557A (en) * | 2001-10-30 | 2006-01-19 | クゥアルコム・インコーポレイテッド | Ball-shaped grid array X-ray orientation mark |
| JP2008147472A (en) * | 2006-12-12 | 2008-06-26 | Shinko Electric Ind Co Ltd | Semiconductor device and manufacturing method therefor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0212847A (en) * | 1988-06-30 | 1990-01-17 | Nec Corp | Integrated circuit device |
| JPH0290634A (en) * | 1988-09-28 | 1990-03-30 | Nec Corp | Bonding pad of semiconductor device |
| JPH0590325A (en) * | 1991-09-27 | 1993-04-09 | Toshiba Corp | Bonding of semiconductor device |
-
1997
- 1997-01-09 JP JP00183497A patent/JP3535683B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0212847A (en) * | 1988-06-30 | 1990-01-17 | Nec Corp | Integrated circuit device |
| JPH0290634A (en) * | 1988-09-28 | 1990-03-30 | Nec Corp | Bonding pad of semiconductor device |
| JPH0590325A (en) * | 1991-09-27 | 1993-04-09 | Toshiba Corp | Bonding of semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1269540A1 (en) * | 2000-03-09 | 2003-01-02 | Silverbrook Research Pty. Limited | Modular printhead alignment system |
| EP1269540A4 (en) * | 2000-03-09 | 2005-03-30 | Silverbrook Res Pty Ltd | Modular printhead alignment system |
| JP2006502557A (en) * | 2001-10-30 | 2006-01-19 | クゥアルコム・インコーポレイテッド | Ball-shaped grid array X-ray orientation mark |
| JP2008147472A (en) * | 2006-12-12 | 2008-06-26 | Shinko Electric Ind Co Ltd | Semiconductor device and manufacturing method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3535683B2 (en) | 2004-06-07 |
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