JPH10199806A - Manufacture of crystalline silicon film - Google Patents

Abstract

PROBLEM TO BE SOLVED: To laterally grow a crystal suppress the deposition of a catalytic element, without natural crystallization by limiting the annealing time for crystallizing in the lateral growth within a specified range of the crystallizing time at temp. To , when an amorphous Si film uses no catalytic element. SOLUTION: In a lateral growth, the relation x=g(T, t) between the annealing time and growth distance x is obtd. From a target growth distance xo , critical annealing time to and critical annealing temp. To are obtd. By annealing below this temp. To , crystalline Si film 12 having little deposition of a catalytic element is obtd. up to a target lateral growth distance. If the annealing is continued, this causes natural crystallization and deposit 15 of the catalytic element outside it. Hence by setting over 90% and below 100% of the critical annealing time to and temp. To , the lateral growth is obtd., while suppressing the catalytic element deposition up to the target distance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a crystalline silicon film formed on an insulating substrate such as glass, a semiconductor substrate such as a single crystal silicon substrate, or the like. Particularly, in the present invention, in a method of crystallizing an amorphous silicon film by annealing, a crystalline silicon film in a preferable crystalline state is obtained by performing lateral growth using a catalytic element (nickel or the like) that promotes crystallization. About the method.

[0002]

2. Description of the Related Art Crystalline silicon films are indispensable materials for semiconductor devices such as thin film transistors. In recent years, a metal element (catalytic element) having a function to promote crystallization of an amorphous silicon film
It is known that a silicon film having good crystallinity can be obtained at a lower temperature and in a shorter time by using. Nickel (Ni), platinum (Pt), palladium (P
d), copper (Cu), silver (Ag), iron (Fe) and the like are effective.

In particular, there is known a technique in which the direction of crystal growth is controlled by non-selectively introducing a catalytic element to obtain a silicon film having a crystal structure preferable for an element (for example, Japanese Patent Application Laid-Open No. 7-45519). , Pp. 8-21634). This technique is called a lateral growth method. In the lateral growth method, crystal grain boundaries are present in parallel with the growth direction, and the effect of the grain boundaries can be reduced to the utmost by making the current direction of the element parallel to the growth direction. As a result, characteristics equivalent to those of a single crystal material can be obtained while being polycrystalline.

[0004]

The lateral growth method will be briefly described. In the lateral growth method, a mask film of silicon oxide or the like is formed on an amorphous silicon film, and windows are selectively formed in the mask film. A catalytic element is introduced through the window. In FIG. 1A, the window is 1
Indicated by 1. Then, a film of the catalyst element alone or a compound thereof is formed by a sputtering method (JP-A-7-45519 or 7-66).
425), a vapor deposition method (JP-A-7-335548), and a coating method (JP-A-7-130652).

[0005] When crystallization is performed by annealing, a crystalline silicon region (lateral growth region) 13 is expanded around the window. This is because the amorphous silicon film is crystallized while the catalytic element diffuses into the silicon film. In general, the higher the temperature and the longer the time, the further the crystallization proceeds. (FIG. 1A, details are described in the above-mentioned patent publication)

The direction of lateral growth and the thin film transistor (TF)
By arranging the direction in which the current flows in the semiconductor element as in T), the characteristics of the semiconductor element can be improved. That is, there are some variations regarding the arrangement of TFTs. One of them is shown in FIG. FIG.
Reference numeral 301 denotes a window portion to which a catalytic element is added, and a region 302 crystallized by lateral growth expands around this portion.

In this case, if the window 301 is rectangular, an elliptical lateral growth region is formed as shown in the figure. In such a case, the gate electrode 304 may be substantially parallel to the region 301 as in the case of the TFT 1 in the drawing, and the crystal may be grown in the direction from the drain 305 to the source 303 or in the opposite direction.

Further, as shown in the TFT 2 in FIG.
And the gate electrode 307 are arranged substantially vertically,
6. In some cases, the crystal is grown almost simultaneously with the drain 308. As the characteristics of the TFT, the former method has a large on-current because the direction of the current is parallel to the crystal grain boundary, and the latter method has a large off-current because the direction of the current is perpendicular to the crystal grain boundary. Has features. (Fig. 3)

Further, the window may be linear, and the catalytic element may be linearly added. FIG. 4 shows an example in which catalyst element addition regions 401 and 406 are provided in parallel with gate lines 402 and 407 in a circuit provided with a large number of TFTs. FIG.
(A) corresponds to TFT2 in FIG.
This is a case where a catalyst element is added substantially vertically to the gate electrodes 3 to 405. FIG. 4B corresponds to the TFT 1 of FIG. 3 and shows a case where a catalytic element is added substantially in parallel to the gate electrodes of the TFTs 408 to 410. (FIG. 4)

[0010] Such control of the crystal growth direction by the lateral growth method is effective in an advanced semiconductor integrated circuit in which elements requiring mutually contradictory functions are formed on the same substrate. FIG. 5 shows a block diagram of a monolithic active matrix circuit used for a liquid crystal display. Source driver (column driver), gate driver (row driver) as peripheral driver circuit
Is provided.

An active matrix circuit (pixel)
Many pixel circuits including switching transistors and capacitors are formed in the region, and the pixel transistors and the peripheral driver circuits of the matrix circuit are connected by the same number of source lines and gate lines as the number of rows and columns.
High-speed operation is required for a TFT used for a peripheral circuit, particularly a peripheral logic circuit such as a shift register, and therefore, a current (on-current) at the time of selection and a variation thereof are required to be large.

On the other hand, the TFT used for the pixel circuit is not selected so that the electric charge accumulated in the capacitor is retained for a long time, that is, the leakage current (both the off-current and the off-current) when a reverse bias voltage is applied to the gate electrode. ) Is required to be sufficiently low and the variation is small. Specifically, the off current is required to be 1 pA or less, and the variation is required to be within one digit. Conversely, a large ON current is not required.

As described above, it is required to simultaneously form TFTs having physically inconsistent characteristics such as a high on-current and a low leakage current and small variations thereof on the same substrate. However, it can be easily understood that this is technically very difficult with a normal crystallization method. On the other hand, if the crystal direction is controlled by the lateral growth method, these problems can be solved (Japanese Patent Laid-Open No. Hei 8-21634). Thus, the effectiveness of the lateral growth method using a catalytic element is shown.

[0014]

Ideally, if annealing is performed at a higher temperature for a longer time, an infinitely large lateral growth can be obtained, but in reality, the lateral growth region is expanded. However, a large number of catalyst element deposition portions are formed inside the inside. The catalytic elements are conductive, and when they are etched, vacancies remain in the silicon film,
It is easy to cause circuit failure.

As described above, when an attempt is made to obtain a large lateral growth region, the quality of the crystal deteriorates as a whole due to the precipitation of the catalytic element. This is shown in FIG. FIG.
This shows a state in which lateral growth is further continued from the state shown in (A), and the lateral growth region 13 is expanded to a portion indicated by a practice ellipse 14 in the figure (in the case of FIG. (A portion indicated by a dotted ellipse 12). However, a catalytic element deposition region (indicated by a black dot 15 in the figure) appears particularly in a portion away from the window. (FIG. 1 (B))

Generally, in the window 11 and its vicinity, the concentration of the catalytic element is high, and it is desirable to avoid that this region overlaps with the main part of the device. In the current technology, in the lateral growth method using nickel as a catalytic element, the width of lateral growth without precipitation of nickel is 50 to 60 μm at the maximum. However, as the device becomes larger, the lateral growth region may become larger. is necessary. An object of the present invention is to provide annealing conditions for obtaining a larger lateral growth region while reducing such precipitation of a catalytic element.

[0017]

According to the invention disclosed in the present invention, when performing crystallization by the lateral growth method by annealing the amorphous silicon film at a temperature T ₀ using a catalytic element, the annealing time is as follows: the amorphous silicon film, in a condition without using a catalyst element, and less than 90% to 100% of the time to crystallize t ₀ at a temperature T _0.

According to the observations made by the present inventors, the lateral growth is interrupted by the spontaneous crystallization of the amorphous silicon film (generation of crystal nuclei, crystal growth without the action of the catalytic element). It turned out to happen. Therefore,
By performing the lateral growth under conditions where spontaneous crystallization does not occur, precipitation of the catalytic element can be suppressed.

The time at which spontaneous crystallization starts at a specific annealing temperature can be specified. If the annealing is performed for a time longer than this, a catalytic element is deposited by natural crystallization. Further, if the annealing is performed for a short time, the lateral growth is insufficient. Limiting the time for spontaneous crystallization to occur is 90
% Or more and less than 100%. However, there is a possibility that a lateral growth region having a target area cannot be obtained.

In order to solve the problem, the annealing temperature may be treated as a variable, and the annealing temperature and the annealing time may be determined from the required lateral growth width. That is, first, a relational expression between the annealing temperature and the annealing time under the critical condition for natural crystallization, t = f (T) (T: annealing temperature, t: annealing time) is obtained.

For example, when an amorphous silicon film is annealed at 600 ° C. by a plasma CVD method, it is naturally crystallized in 4 hours. Other temperatures are checked in the same manner, and for example, as shown in FIG. In general, the same amorphous silicon film has different curves depending on the manufacturing method. For example, decompression CV
The amorphous silicon film (Si film a) by the D method is plasma CVD
The curve is on the upper right, which is harder to crystallize than the amorphous silicon film (Si film b) by the method.

Further, in the lateral growth, a relational expression relating to the annealing temperature and the growth distance, x = g (T, t) (x: growth distance) is obtained. When the target growth distance is x ₀ , a critical annealing time t ₀ and a critical annealing temperature T ₀ satisfying the above two relationships are obtained.

Actually, by performing annealing at a temperature equal to or lower than the limit annealing temperature T ₀ , a crystalline silicon film having almost no catalyst element deposition up to the target lateral growth distance can be obtained. Further, if the annealing is continued, spontaneous crystallization occurs and precipitation of the catalytic element occurs outside the crystallization. However, it does not matter how much precipitation occurs unless the portion is important on the circuit. In this manner, lateral growth with little precipitation of the catalytic element can be performed up to the target distance. More preferably, the critical annealing time and the critical annealing temperature of 9
It is good to be 0% or more and less than 100%.

In the present invention, as a criticality measurement method (determination method) for natural crystallization, observation using an optical microscope, observation using an electron microscope, observation using a spectroscopic method (for example, Raman spectroscopy), and the like are effective. It should be noted that the relational expressions determined by the respective methods do not always match. Therefore, the limit annealing time and the limit annealing temperature also differ depending on the method of determining the natural crystallization to be used.

In addition, in the case of natural crystallization or lateral growth, the relationship between the temperature and time changes when the thickness of the substrate, the base, the amorphous silicon film, the method of forming the film, the cap film (mask film), and the like change. Therefore, when obtaining the relational expression g, it is necessary to set the same conditions as the target amorphous silicon film.
In determining f, it is effective to cover the amorphous silicon film with a mask film used for lateral growth.

[0026]

2 and 6 show a manufacturing process of this embodiment. FIGS. 2 and 6 show N-channel type TFs constituting peripheral circuits.
This is an outline of a manufacturing process of a circuit having a circuit in which a T-type and a P-channel type TFT are configured to be complementary and a circuit including an N-channel type TFT to be used for a pixel transistor. FIG. 2 is a sectional view, and FIG. 6 is a top view. Although FIG. 2A to FIG. 2F do not correspond to FIG. 6A to FIG. 6C, the individual numbers correspond to each other.

First, a 2000-nm-thick silicon oxide base film 202 was formed on a polished quartz substrate 201 by plasma CVD. Further, an amorphous silicon film 203 having a thickness of 500 ° was formed by a plasma CVD method. Then, a mask film 204 of silicon oxide having a thickness of 1000 to 3000 Å, for example, 2000 Å is formed, and a portion for introducing a catalytic element (nickel) is etched to form windows 205 and 20.
6 was formed, and the amorphous silicon film in this portion was exposed.

At the time of moving to the next step, a number of amorphous silicon films obtained up to the above steps are prepared. At that time, the manufacturing method of the substrate, the base film, the amorphous silicon film, and the mask film is all the same. Then, using these, the relationship between the temperature at which spontaneous crystallization starts and the time was measured, and the relational expression t = f
(T) is obtained. In this example, spontaneous crystallization was determined by observation with an optical microscope. The atmosphere at that time was a nitrogen atmosphere as in the subsequent crystallization step.

Next, an extremely thin oxide film (several tens of Å in thickness, not shown) was formed on the surface of the amorphous silicon film 203 exposed in the above process. This is to prevent the solution from being repelled on the surface of the amorphous silicon film 203 in the subsequent solution coating step. This oxide film may be formed by a thermal oxidation method, irradiation of ultraviolet light in an oxygen atmosphere, or treatment with a highly oxidizing solution such as aqueous hydrogen peroxide.

Thereafter, a nickel acetate solution containing a nickel element which is a catalyst element for promoting crystallization is applied, and a very thin nickel acetate film 2 is formed on the surface of the amorphous silicon film 203.
07 is formed. This film 207 is extremely thin, and therefore may not be a complete film. This step was performed using a spin coating method or a spin dry method. An appropriate concentration (in terms of weight) of nickel in the acetic acid solution was 1 to 100 ppm. In this embodiment, the concentration is set to 10 ppm. (Fig. 2 (A))

Next, before proceeding to the annealing step, a large number of amorphous silicon films (including a mask film, a window for introducing nickel, and a nickel acetate film) are prepared under the same conditions as in the above steps.
Were prepared, and the relationship between the lateral growth rate and the annealing temperature was examined using these. The atmosphere at this time was also the same as the atmosphere in the subsequent crystallization step, which was a nitrogen atmosphere. Thus, the relational expression x = g (T, t) is obtained. The lateral growth distance required in this embodiment is 100 μm.

Then, the equation g (T, f (T)) = 100 [μm] is solved to obtain a limit annealing temperature T and a limit annealing time t. In this embodiment, T = 680 ° C. and t = 30 minutes. As a result, in this example, the annealing temperature was determined to be 645 ° C., which is 95% of the critical annealing temperature, and the annealing time was determined to be 29 minutes, which is 97% of the critical annealing time.

Thereafter, heat annealing was performed at 645 ° C. for 29 minutes in a nitrogen atmosphere to crystallize the silicon film 203.
Crystallization progressed in a direction parallel to the substrate, starting from a region where the nickel and silicon films were in contact.
In FIG. 2B, regions 208 and 209 are regions crystallized in this step, and regions 210 and 2
Reference numeral 11 denotes a region which remains amorphous silicon. FIG. 6A shows this state viewed from above. (Figure 2
(B) and FIG. 6 (A))

When annealing was performed for a longer time than the annealing time determined above, precipitation of nickel was observed in a portion separated from the window by 100 μm or more. Next, the silicon film 203 is etched to form an island-shaped active layer region 212.
(Complementary circuit region) and 213 (pixel transistor region). At this time, the region immediately below the windows 205 and 206 located at the center of the ellipse in FIG. 6A is a region where nickel is directly introduced and a region where nickel is present at a high concentration. Nickel also exists at a high concentration at the tip of the crystal growth in the regions 208 and 209. It has been found that these regions have a nickel concentration that is nearly an order of magnitude higher than the crystallized regions between them.

Although the nickel concentration in the silicon film is reduced in a later gettering step, it is necessary to avoid using these regions as main parts of the device. Therefore, in the present embodiment, the active layer regions 212, 213,
In particular, it is necessary to arrange the channel formation region so as to avoid these regions where the nickel concentration is high. The etching of the active layer was performed by the RIE method having anisotropy in the vertical direction. The typical nickel concentration in the lateral growth region at this stage was about 10 ¹⁷ to 10 ¹⁹ cm ⁻³ .

Next, 950 to 1150 in an oxidizing atmosphere.
By heating to a temperature of ° C., a thin (about 200 ° thick) silicon oxide film 214 was formed on the surfaces of the active layers 212 and 213. The atmosphere was mixed with 0.1-10% hydrogen chloride.
By the action of the hydrogen chloride, a part of nickel present in the silicon film was gettered. (Fig. 2 (C))

After that, a thickness of 1
A silicon oxide film 215 of 2,000 Å was formed as a gate insulating film. For the film formation, nitrous oxide and tetraethoxysilane (TEOS) were used as source gases, and the substrate temperature was 200 to 400 ° C., for example, 350 ° C. (Figure 2
(D))

Subsequently, a silicon film (containing 0.1 to 2% of phosphorus) having a thickness of 3000 to 8000 °, for example, 6000 ° was formed by a low pressure CVD method. Note that it is desirable that the silicon oxide film 215 and the step of forming the silicon film be continuously performed. Then, the silicon film was etched to form gate electrodes 216 to 218. FIG. 6B shows this state viewed from above. The ellipses indicated by the dotted lines in the figure correspond to the regions 208 and 209 in FIG. (FIG. 6
(B))

Next, impurities (phosphorus and boron) were implanted into the active layer using the gate electrodes 216 to 218 as a mask by ion doping. Phosphine (PH ₃ ) and diborane (B ₂ H)
₆ ), and in the former case, the accelerating voltage is 60 to 90 k
V, for example 80 kV, in the latter case 40-80 kV,
For example, it is set to 65 kV, and the dose is 1 × 10 ¹⁵ to 8 × 10
¹⁵ cm ^-2 , for example, 2 × 10 ¹⁵ cm ^{-2 of} phosphorus and 5 of boron
× 10 ¹⁵ cm ^-2 .

At the time of doping, each element was selectively doped by covering a region not requiring doping with a photoresist. As a result, N-type impurity regions 220 and 221 and a P-type impurity region 219 were formed. After that, annealing was performed by laser light irradiation to activate the ion-implanted impurities.
KrF excimer laser (wavelength 2
Although 48 nm and a pulse width of 20 nsec are used, other lasers may be used.

The irradiation condition of the laser beam is such that the energy density is 200 to 400 mJ / cm ² , for example, 250 mJ / c.
m ^2, and ² to 10 shots per location, for example, 2 shots. When the substrate is irradiated with laser light,
When heated to about 50 ° C., activation can be performed more stably. (FIG. 2E) Subsequently, a silicon oxide film 222 having a thickness of 6000 ° was formed as an interlayer insulator by a plasma CVD method. further,
An ITO film having a thickness of 500 mm is formed by a sputtering method,
This was patterned to form a pixel electrode 223.

Then, a contact hole (the opening position of the contact hole is shown in FIG. 6C) is formed in the interlayer insulator 222, and a metal material, for example, a multilayer film of titanium nitride and aluminum is used to form an electrode of the TFT. Wiring 224 ~
228 were formed. Finally, in a hydrogen atmosphere of 1 atm.
Annealing was performed at 0 ° C. for 30 minutes to complete a TFT circuit. (FIG. 2 (F))

As is clear from FIG. 6B, in the active layer 212, the source / drain direction is parallel to the crystallization direction, while in the active layer 213, the source / drain direction is the crystallization direction. And perpendicular. As a result,
The TFT formed in the active layer 212 has a feature that the ON current is large, while the TFT formed in the active layer 213 has a feature that the OFF current is small. In this embodiment, two types of TFTs having different characteristics are shown at relatively close positions for the sake of simplicity. However, they may be manufactured at very distant places like an active matrix circuit. Needless to say.

[0044]

According to the present invention, it is possible to obtain a crystalline silicon film in which the crystal quality does not deteriorate (no deposition of catalytic elements is observed) even when the lateral growth distance is increased. As described above, such a silicon film is extremely advantageous in forming a semiconductor element and a semiconductor integrated circuit. As described above, the present invention is industrially useful.

[Brief description of the drawings]

FIG. 1 shows an outline of an annealing condition determination method of the present invention.

FIG. 2 shows a manufacturing process of a TFT according to an embodiment. (Cross section)

FIG. 3 shows an example of arrangement of TFTs and lateral growth regions.

FIG. 4 shows an arrangement example of a TFT and a catalytic element addition region.

FIG. 5 shows an outline of a monolithic type active matrix circuit.

FIG. 6 illustrates a manufacturing process of a TFT according to an example. (Top view)

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Window for catalyst element introduction 12 ... Boundary of lateral growth area 13 ... Horizontal growth area 14 ... Boundary of lateral growth area 15 ... Deposition part of catalyst element 201 ... Quartz substrate 202: Underlayer (silicon oxide film) 203: Silicon film 204: Silicon oxide film (mask film) 205, 206: Window for introducing nickel 207: Nickel acetate film 208, 209 ..Lateral growth regions 210, 211 ... ungrown (amorphous) regions 212, 213 ... island-shaped silicon regions (active layers) 214 ... thermal oxide films 215 ... gate insulating films 216 to 218 ... Gate electrode 219 ... P-type impurity region 220, 221 ... N-type impurity region 222 ... Interlayer insulator 223 ... Pixel electrode 224 to 228 ... Wiring / electrode

Claims (3)

[Claims] An amorphous silicon film formed on a substrate is subjected to a temperature T by a lateral growth method using a catalytic element for promoting crystallization.
Regarding the method of performing crystallization by annealing of ₀ , the annealing time is 90% or more and less than 100% of the time t _{0 at which} the amorphous silicon film starts crystallization at the temperature T _{0 under the} condition that no catalytic element is used. A method for manufacturing a crystalline silicon film, comprising: 2. A method for crystallizing an amorphous silicon film formed on a substrate, comprising: forming the amorphous silicon film on the substrate by the same method;
Obtaining a relational expression between the annealing temperature and the annealing time when the amorphous silicon film starts to crystallize spontaneously, t = f (T) (T: annealing temperature, t: annealing time); In the lateral growth using a catalyst element for promoting crystallization of the formed amorphous silicon film, a relational expression regarding an annealing temperature and a growth distance, x = g (T, t) (x: growth distance) Obtaining an annealing time t ₀ and an annealing temperature T ₀ satisfying the above two relations, where the target growth distance is x _0, and the annealing temperature T _0.
A process of laterally growing an amorphous silicon film using a catalytic element by annealing at the following temperature: a method for producing a crystalline silicon film. 3. The crystalline silicon film according to claim 1, wherein the catalyst element is one or more elements selected from Ni, Pd, Pt, Cu, Ag, and Fe. Method of manufacturing.