JPH10197900A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to change the width of high-resistance regions according to the required characteristics and reliability of thin-film transistors(TFTs) and circuits, to improve the degrees of freedom and to constitute highly integrated circuits by changing anodic oxidation time according to the TFTs in an anodic oxidation stage of gate electrodes. SOLUTION: After a silicon oxide film 102 is deposited on a substrate 101, island-shaped silicon regions 103, 104 are formed and only the silicon region 103 is crystallized by irradiation with an excimer laser and thereafter, the gate electrodes 106, 107, 109 are formed. This substrate is then immersed into an ethylene glycol soln. of tartaric acid and is anodically oxidized, by which porous anode oxides 110, 111 are formed at the gate electrodes 106, 107 and barrier type anode oxides 112, 113 at the gate electrode 109, respectively. Next, impurities are added with the gate electrodes 106, 107, 109, the porous anode oxides and barrier type anode oxides 110 to 113 as masks to form offset regions of different widths in the island-shaped silicon regions 103, 104.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for improving the reliability and characteristics of an integrated circuit in which a large number of thin-film insulating gate type semiconductor devices (thin film transistors or TFTs) are formed on an insulating surface. The semiconductor device according to the present invention is used for a driving circuit such as an active matrix such as a liquid crystal display or an image sensor, or an SOI integrated circuit or a conventional semiconductor integrated circuit (a microprocessor, a microcontroller, a microcomputer, a semiconductor memory, or the like). Things. In particular, the present invention relates to a monolithic thin film integrated circuit in which an active matrix circuit for driving an electro-optical device and a driver circuit for driving the same or a memory circuit and a central processing circuit (CPU) are formed on the same substrate. It relates to a manufacturing method thereof.

[0002]

2. Description of the Related Art In recent years, an insulating gate type semiconductor device (MI) has been formed on an insulating substrate or on a surface (insulating surface) separated from the semiconductor substrate by a thick insulating film even on a semiconductor substrate.
Research on forming SFETs has been actively conducted. In particular, a semiconductor device in which a semiconductor layer (active layer) is a thin film is called a thin film transistor (TFT). In such a semiconductor device, it is difficult to obtain an element having good crystallinity, such as a single-crystal semiconductor, and a non-single-crystal semiconductor that usually has crystallinity but is not single-crystal is used.

Such a non-single-crystal semiconductor has poorer characteristics than a single-crystal semiconductor. In particular, a reverse voltage is applied to the gate electrode (that is, a negative voltage is applied to an N-channel TFT, and a negative voltage is applied to a P-channel TFT). When a positive voltage is applied, there is a problem that the leak current between the source and the drain increases. There is also a problem of deterioration such that the mobility of the TFT is reduced by application of a voltage. It is known that in order to solve such a problem, it is necessary to provide an intrinsic or weak N-type or P-type high resistance region between the source / drain region and the gate electrode. In particular, when fabricating a high-resistance region, the gate electrode is anodized, or at least oxidized on at least the side surface by other methods, and is doped in a self-aligned manner using this oxide or the trace of the oxide. Thus, a high-resistance region having a uniform width could be obtained.

[0004]

However, such a high-resistance region also functions as a resistor inserted in series between the source and the drain, so that, for example, when a high-speed operation is required, it is unnecessary. Met. In particular, this is a problem when forming TFTs requiring different characteristics on the same insulating surface. For example, considering a monolithic circuit having an active matrix circuit for driving an electro-optical element and a driver circuit for driving the circuit on the same substrate, it is preferable that the active matrix circuit has a low leak current. Therefore, a TFT having a wide high resistance region is desired.

However, in a decoder circuit, a driver circuit, a CPU, a memory circuit, and the like, a high-speed operation is required, and therefore, it is desired that the width of the high-resistance region is small. However, in a TFT formed on the same substrate by the same process, the width of the high-resistance region is the same, and it is difficult to change the width of the high-resistance region according to the above-described circuit and purpose. Was. Therefore, it has been difficult to manufacture a monolithic active matrix circuit or a monolithic integrated circuit that further develops the active matrix circuit. The present invention solves such difficulties and provides a TFT
The present invention relates to a semiconductor integrated circuit in which the width of a high-resistance region is changed in accordance with characteristics and reliability required of a circuit and a method of manufacturing the same.

[0006]

A first object of the present invention is to change the width of the high resistance region obtained by changing the anodizing time according to the TFT in the anodizing step of the gate electrode. . A second aspect of the present invention is a monolithic active matrix circuit having a low off-state current,
The width of the high resistance region of the TFT in the active matrix circuit for low frequency operation is larger than that of the TFT in the decoder circuit for high current drive, high frequency operation, low power consumption and high frequency operation. It is. A third aspect of the present invention is to make the width of the high resistance region of the N-channel TFT larger than that of the P-channel TFT.

For example, in a monolithic active matrix circuit, the width of a high resistance region of a TFT in the active matrix circuit is 0.4 to 1 μm, and in a driver circuit, an N-channel TFT (hereinafter, NTFT) is used.
0.2-0.3 μm, P-channel TFT
(Hereinafter referred to as PTFT) is 0 to 0.2 μm. Further, in a decoder used for a central processing circuit (CPU) and other logical operation elements / circuits, the thickness is 0.3 to 0.4 μm for an N-channel TFT and 0 to 0.2 μm for a P-channel TFT. in this way,
According to the present invention, the width of the high-resistance region of the TFT of the active matrix circuit is larger than that of the driver and decoder TFTs, and the width of the high-resistance region of the N-channel TFT is larger than that of the P-channel TFT. And

As described above, the width of the high resistance region of the TFT of the active matrix circuit is larger than the width of the TFT of the driver or the decoder because of the required characteristics of the TFT, the former being a low leakage current, and the latter being a high speed operation. This is because they are different from each other. On the other hand, the reason why the width of the high resistance region is changed between the N-channel TFT and the P-channel TFT in the same driver or decoder is as follows.

Particularly, in an N-channel TFT, a weak N
By providing the high resistance region of the mold, the electric field in the vicinity of the drain can be reduced, and deterioration due to the hot carrier effect can be suppressed. Therefore, in this case, the N-channel TFT
It is desired that the high-resistance region is weak N-type. on the other hand,
In a P-channel type TFT, since deterioration due to hot carriers is small, it is not particularly necessary to provide such a high resistance region. Conversely, the presence of the high resistance region causes a decrease in the operation speed of the TFT. The mobility of a P-channel TFT is N
Since it is inferior to the channel type TFT, it is preferable that the width of the high resistance region is as small as possible. As a result, as described above, the width of the high-resistance region of the N-channel TFT is
It is larger than that of FT.

[0010]

【Example】

Embodiment 1 FIGS. 1 and 2 show an example of manufacturing an integrated circuit having different kinds of TFTs according to the present invention. 2A, 2B, and 2C are FIGS. 1A, 1C, and 1C.
(E) and plan views almost corresponding to each other. FIG. 1 is a cross section of a portion shown by a dashed dotted line in FIG. First, a substrate (Corning 7059, 300 mm
X 300mm or 100mm x 100mm) 101
On top of this, a silicon oxide film 102 having a thickness of 1000 to 3000 ° was deposited by a sputtering method. This is plasma CVD
It may be formed by a method.

After that, an amorphous silicon film is formed in a thickness of 300 to 150 by plasma CVD or LPCVD.
0 [deg.], Preferably 500-1000 [deg.], And patterning to deposit island silicon regions 103 and 104.
Was formed. Then, silicon oxide having a thickness of 200 to 1500 °, preferably 500 to 1000 ° was formed by a sputtering method or a plasma CVD method. Since this silicon oxide film also functions as a gate insulating film, sufficient care must be taken in its manufacture. For example, when using the plasma CVD method, TEOS is used as a raw material, and the substrate temperature is 150 to 400 ° C., preferably 200 to 250 ° C. together with oxygen.
Then, RF discharge was performed to decompose and deposit the source gas. TE
The pressure ratio between OS and oxygen is 1: 1 to 1: 3, the pressure is 0.05 to 0.5 torr, and the RF power is 100 to 25.
0 W. Alternatively, TEOS is used as a raw material together with ozone gas by a low pressure CVD method or a normal pressure CVD method.
The substrate temperature is 150 to 400 ° C., preferably 200 to 25
It may be formed at 0 ° C.

Then, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was irradiated to crystallize only the silicon region 103. The energy density of the laser is 200 to 400 mJ / cm ² , preferably 2
The substrate was heated to 300 to 500 ° C. during laser irradiation at 50 to 300 mJ / cm ² . XeCl excimer laser (wavelength 308n)
m) and others may be used. Silicon region 104 remained amorphous.

Thereafter, an aluminum film having a thickness of 2,000 to 5 μm, for example, 6000 ° is formed by an electron beam evaporation method, and is patterned to form a gate electrode 1.
06, 107, 109 and the wiring 108 were formed. Scandium (Sc) is added to aluminum in an amount of 0.05 to 0.1%.
By doping at 3% by weight, generation of hillocks due to heating was suppressed. This state is shown in FIGS.
It is shown in (A). As is clear from FIG. 2A, the gate electrode 109 and the wiring 108 are electrically connected, and the gate electrodes 106 and 107 are electrically independent of the gate electrode 109 and the wiring 108. . Hereinafter, the former is A
The series and the latter are called the B series. Next, the substrate was adjusted to pH 7, 7, 1
Immersed in a solution of ~ 3% tartaric acid in ethylene glycol, using platinum as the cathode and the aluminum gate electrode as the anode
Anodization was performed. An anodic oxide obtained using such a neutral solution is called a barrier type anodic oxide, and is dense and has high withstand voltage.

At the time of anodic oxidation, two types of power supply terminals for the anode which can be independently controlled were prepared and connected to terminals different from those of the A-series and B-series. In the anodization, initially, a constant current was continuously applied to both the A series and the B series, the voltage was increased to the _first voltage, V1, and the state was maintained for 1 hour.
Thereafter, a constant current was continuously applied to the B series while maintaining the voltage V _{1 in the} A series, and the voltage was increased to the second voltage V ₂ . Since the two-stage anodic oxidation is performed as described above, the thickness of the anodic oxide formed on the side surface and the upper surface of the gate electrode differs between the A series and the B series, and the latter is thicker. V ₁ is preferably 50 to 150 V,
Here, it was set to 100V. As V2, 100 to ₂
50V is preferable, and here, it was 200V. In the present embodiment, in the constant current state, the voltage rising speed is suitably 2 to 5 V / min. Naturally, V ₁ <V ₂ .
As a result, the anodic oxides 110 and 111 having a thickness of about 1200 ° are applied to the gate electrodes 106 and 107 of the A series, and the thickness of 2400 ° is applied to the gate electrode 109 and the wiring 108.
Are formed, respectively.
(FIG. 1 (B))

After that, impurity ions (phosphorus, boron) are implanted into the island-like silicon film of each TFT by ion doping (also called plasma doping) using a known CMOS technique and a self-aligned impurity implantation technique. did.
Phosphine (PH ₃ ) and diborane (B ₂ H ₆ ) were used as doping gases. Dose amount is 2-8 ×
It was 10 ¹⁵ cm ^-2 . As a result, N-type impurity (phosphorus) regions 114 and 116 and P-type impurity (boron) region 115
Was formed. It is NTFT 126, 12 in the drawing.
8, for forming the PTFT 127.

Further, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was irradiated to improve the crystallinity of the portion where the crystallinity was deteriorated by the introduction of the impurity region. Laser energy density is 150 ~
400 mJ / cm ² , preferably 200 to 250 mJ /
cm ² . Thus, the N-type impurity regions 114, 1
16 and the P-type impurity region 115 were activated. The sheet resistance in these regions was 200 to 800 Ω / □. This step may be performed by RTA (rapid thermal annealing). (FIG. 1 (C), FIG. 2 (B))

Through the above steps, the width of the offset region (high resistance region) of each TFT is determined. That is, the two TFTs on the left side of FIG.
Since the thicknesses of 0 and 111 are about 1200 °, the offset widths x ₁ and x ₃ are about 1000 ° in consideration of the rounding during ion doping. In the TFT on the right, the thickness of the anodic oxide 113 is about 2400 ° Therefore, offset width x ₂
Was about 2000Å. (See FIG. 1D) Offset width x of TFTs 126 and 127 for high frequency operation
_1, x ₃ is required to be smaller than the offset width x ₂ of NTFT128 to be low off current demand. However, since the NTFT is likely to be frequently deteriorated by hot carriers due to the reverse bias of the drain, it is preferable that the offset width is larger than that of the PTFT. That is,
x _3> is x _1. Also, small off-current, and, NTFT128 high drain current is applied is x _2> x ₃ to have a large offset width.

Thereafter, the gate electrode and wiring (FIG. 2)
(C) 130) was cut to obtain a length required for the circuit. Then, TEOS is used as an interlayer insulator 117 on the entire surface.
Was used as a raw material to form a silicon oxide film having a thickness of 3000-10000 °, for example, 6000 ° by a plasma CVD method with oxygen, a reduced pressure CVD method with ozone, or a normal pressure CVD method. At this time, if fluorine is reacted with dicarbon hexafluoride (C ₂ F ₆ ) and added to silicon oxide, the step coverage can be improved. Substrate temperature is 1
The temperature was 50 to 400 ° C, preferably 200 to 300 ° C. Further, an ITO film is deposited by a sputtering method,
This was patterned to form a pixel electrode 118. Then, the interlayer insulator 117 and the anodic oxide 112 of the wiring 108 were etched to form a contact hole 119. (Fig. 1 (D))

Thereafter, an interlayer insulator and a gate insulating film 105 are formed.
Was etched to form contact holes in the source / drain of the TFT. Although not shown in FIG. 1, the anodic oxide 11
0, 111 are also etched to form the gate electrodes 106, 1
Also, a contact hole is formed at 07. (Figure 2
(See (C).) Then, a wiring 12 of a multilayer film of titanium nitride and aluminum is formed.
0-125 were formed. The wiring 124 was connected to the pixel electrode 118. In addition, a wiring 125 was connected to the gate electrodes 106 and 107 via the contact holes previously formed. Finally, in hydrogen at 200-300 ° C for 0.1-
Annealing for 2 hours completed hydrogenation of silicon. Thus, an integrated circuit was completed. (FIG. 1 (E), FIG. 2 (C))

In this embodiment, the step of forming a contact hole by etching the thick anodic oxide 113 and the step of forming other contact holes are separately performed. Of course, they may be performed at the same time. However, in the present embodiment, the reason for this is that the former is thicker than the latter because the difference in the thickness of the anodic oxide is 1200 mm. This is because the etching rate of the barrier type anodic oxide obtained in this example is extremely small compared to silicon oxide or the like. This is because the contact holes to the exposed source and drain are largely etched, and holes are formed in the source and drain.

Thus, different types of TFTs were formed on the same substrate. That is, 2 on the left side of FIGS.
One of the TFTs 126 and 127 is a TFT whose active layer is crystalline silicon and has a small width in a high-resistance region (offset region) and is suitable for high-speed operation. The right TFT 129 has an active layer of amorphous silicon and a high-resistance region (offset region). It is characterized by a wide TFT and low leakage current. T
The same effect can be obtained even when the active layer of the FT128 is made of crystalline silicon having a lower degree of crystallization than the TFTs 127 and 128. When manufacturing a monolithic active matrix using the same process, it goes without saying that the former may be used for the driver circuit and the latter may be used for the active matrix circuit.

Deterioration due to hot carriers is often seen in NTFT, but driver TFTs with large channel widths
In (the offset width and x _4), not so much observed. Further, the decoder circuit which requires high frequency operation, especially (for the offset width x ₃₎ shift register, CPU, memory, NTFT other correction circuit
Is required to have a small channel width and a small channel width.
T128 is small (the offset width is x ₂₎ deterioration due drain voltage is lower than. Therefore, x ₄ <
It is required that x ₃ <x ₂ . And PTFT
Since the offset width x ₁ of the driver TFT and the auxiliary circuit outside the driver TFT hardly deteriorate, it is allowed that x ₁ ≦ x ₄ .

Embodiment 2 FIGS. 3 and 4 show this embodiment. FIG. 3 is a cross section of a portion shown by a dashed dotted line in FIG. First, the substrate (Corning 7059, 300
mm × 400mm or 100mm × 100mm) 2
01 as a base oxide film 202 having a thickness of 1000 to 300
A silicon oxide film of 0 °, for example, 2000 ° was formed. As a method for forming this oxide film, a sputtering method in an oxygen atmosphere was used. However, in order to increase mass productivity, T
A film in which EOS is decomposed and deposited by a plasma CVD method may be used.

Thereafter, the amorphous silicon film is formed into a thickness of 300 to 5000 by a plasma CVD method or an LPCVD method.
{Preferably 500-1000} and deposit 5
It was left in a reducing atmosphere at 50 to 600 ° C. for 24 hours to be crystallized. This step may be performed by laser irradiation. Then, the silicon film thus crystallized is patterned to form island-like active layer regions 203 and 2.
04 was formed. Further, a silicon oxide film 205 having a thickness of 700 to 1500 ° was formed thereon by sputtering.

Thereafter, an aluminum film (containing 1 wt% of Si or 0.1 to 0.3 wt% of Sc) having a thickness of 1000 to 3 μm, for example, 6000 °, was formed by electron beam evaporation or sputtering. Then, a photoresist (for example, OFPR8 manufactured by Tokyo Ohka)
00/30 cp) by spin coating.
If an aluminum oxide film having a thickness of 100 to 1000 ° is formed on the entire surface of the aluminum film by anodic oxidation before forming the photoresist, adhesion to the photoresist is good, and By suppressing the current leakage, it was effective in forming the porous anodic oxide only on the side surfaces in the subsequent anodic oxidation step. Thereafter, the photoresist and the aluminum film are patterned and etched together with the aluminum film to form wiring portions 206 and 209 and gate electrode portions 207 and 20.
8, 210 were formed. (FIG. 3 (A))

The photoresist is left on these wirings and gate electrodes, and functions as a mask for preventing anodic oxidation in a subsequent anodic oxidation step. FIG. 4 shows this state viewed from above. Also in this case, similarly to the first embodiment, the gate electrodes 207 and 208 and the wiring 2
09, the wiring 206 and the gate electrode 210 are electrically independent, and the former is referred to as an A-series and the latter is referred to as a B-series.
(FIG. 4 (A))

Then, of the above wirings and gate electrodes,
Anodization was performed by passing an electric current in an electrolytic solution only for the B series, and anodic oxides 211 and 212 having a thickness of 3000 to 25 μm, for example, 0.5 μm, were formed on the side surfaces of the wiring and the gate electrode. The anodic oxidation was performed using a 3 to 20% aqueous solution of citric acid or an acidic aqueous solution of oxalic acid, phosphoric acid, chromic acid, sulfuric acid or the like, and a constant current of 5 to 30 V, for example, 8 V was applied to the gate electrode. The anodic oxide thus formed was porous. In this embodiment, the voltage is set to 8 V in an oxalic acid solution (30 to 80 ° C.),
Anodized for ~ 240 minutes. The thickness of the anodized oxide was controlled by the anodizing time and temperature. At this time, since no current flows through the A series, the gate electrodes 207, 20
8. No anodic oxide was formed on the wiring 209.
(FIG. 3 (B), FIG. 4 (B))

Next, the mask was removed, and a current was again applied to the gate electrode and wiring in the electrolytic solution. This time,
Both series A and series B were energized using a PH ％ 7 ethylene glycol solution containing 3-10% tartaric acid, boric acid and nitric acid. A better oxide film was obtained when the temperature of the solution was lower than room temperature around 10 ° C. For this reason, barrier type anodic oxides 213 to 217 were formed on the upper surfaces and side surfaces of the gate electrodes / wirings 206 to 210. Anodic oxides 213-2
The thickness of 17 is proportional to the applied voltage.
At 00V, 1200 ° of anodic oxide was formed. In this example, since the voltage was increased to 100 V, the thickness of the obtained anodic oxide was 1200 °. The thickness of the barrier type anodic oxide is arbitrary, but if it is too thin, there is a risk that aluminum will be eluted when the porous anodic oxide is etched later, so that 500 mm or more was preferred. .

It should be noted that although barrier-type anodic oxide is obtained in a later step, a barrier-type anodic oxide is not formed outside the porous anodic oxide, but a porous anodic oxide is formed. A barrier-type anodic oxide is formed between the oxide and the gate electrode. (FIG. 3 (C)) Then, impurities are self-aligned in the active layers 203 and 204 of the TFT by ion doping using the gate electrode portion (that is, the gate electrode and the surrounding anodic oxide film) and the gate insulating film as a mask. Is implanted and impurities (source /
Drain) regions 218, 219 and 220 were formed. Phosphine (PH ₃ ) and diborane (B ₂ H ₆ ) were used as doping gases. The dose is 5 × 10 ¹⁴ or more
5 × 10 ¹⁵ cm ^-2 , acceleration energy 50-90 keV
And Impurities are introduced so that the regions 218 and 220 become N-type and the region 219 becomes P-type. The region 218 makes the NTFT 228, and the region 219 makes the PTFT 22
9. NTFT 230 is formed by the region 220.

As a result, in the two TFTs 228 and 229 on the left side of the figure (these are complementary TFTs), the thickness of the anodic oxides 214 and 215 on the side surfaces of the gate electrode is about 12
Since it is 00 °, the widths x ₁ and x ₃ of the region (offset region) where the gate electrode and the impurity region do not overlap are about 1000 ° in consideration of the rounding during ion doping. On the other hand, in the right TFT 230, the anodic oxide 212
The offset width x ₂ was about 6000 ° because the thicknesses of and 217 totaled about 6200 °.

Thereafter, the porous anodic oxides 211 and 213 were etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. In this etching, only the anodic oxides 211 and 213 were etched, and the etching rate was about 600 ° / min. Barrier type anodic oxides 213 to 217 and silicon oxide film 2
05 remained as it was. Thereafter, irradiation with a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was performed to activate the impurity ions introduced into the active layer. (FIG. 3 (E))

Then, the gate electrode and the wiring were divided to have the required size and shape. (FIG. 4 (C).
A silicon oxide film having a thickness of 6000 mm was formed as an interlayer insulator 221 on the entire surface by a CVD method. Next, thickness 800
The ITO film of Å was formed by a sputtering method, and this was patterned to form a pixel electrode 222. Then, the interlayer insulator 221 and the gate insulating film 205 are etched to form contact holes in the source / drain of the TFT, and at the same time, the interlayer insulator 221 and the anodic oxide 2 are formed.
13 to 217 were etched to form contact holes in the gate electrode and wiring. In the present embodiment, unlike the first embodiment, since the anodic oxide has substantially the same thickness in both the A-series and the B-series, they can be simultaneously etched. One less than in the case of Finally, aluminum wiring / electrodes 223 to 226 were formed, and hydrogen annealing was performed at 200 to 400 ° C.

The wiring 223 is complementary to the wiring 206
The source of the N-channel TFT of the FT is connected, and the wiring 22 is connected.
5 connects the source of the P-channel TFT of the complementary TFT and the wiring 209. The wiring 224 (that is, 226) connects the output terminal of the complementary TFT (that is, the drain of the N-channel TFT and the drain of the P-channel TFT) to the drain of the right TFT. Further, the wiring 227
Connects the drain of the right TFT to the pixel electrode 222. Thus, an integrated circuit having a TFT is completed. (FIG. 3 (F))

Further, especially in the A series, as shown in the embodiment, since the driver is driven by a large current, the PTF
T (the width of the high resistance region is x ₁ ), The NTFT (high resistance region width x ₄₎ with little degradation. Further, a decoder, a CPU, a shift register, a memory, and other driving circuits consume low power and operate at high frequency, so that both channel width and channel length are small, and deterioration due to hot carriers easily occurs. NT used in these circuits
The width of the high resistance region of the FT x _3, it is necessary to become larger than the width x ₁ of the high resistance region of PTFT. In addition, NTFTs in the active matrix circuit to which a large voltage is applied (the width of the high-resistance region is x ₂ ) have a small required mobility, so that they are very liable to be deteriorated. For improvement, it is required that x ₂ > x ₃ > x ₄ ≧ x ₁ . For example, x ₂ is 0.5 to 1 [mu] m, x ₃
Is 0.2~0.3μm, x ₄ is 0~0.2μm, x ₁ is 0~0.1μm. Thus, the shift register could operate at 1 to 50 MHz. In the present embodiment, the effect of suppressing the leakage current when the width of the offset of the TFT (the right TFT) for controlling the pixel electrode is sufficiently larger than that of the first embodiment is great.

Embodiment 3 FIG. 5 shows this embodiment. The present embodiment relates to a monolithic active matrix liquid crystal display. The left side of the figure shows complementary TFTs of a driver circuit, and the right side shows pixel control TFTs of an active matrix circuit. First, a 2000-mm-thick silicon oxide film was formed as a base oxide film 302 on a substrate (Corning 7059, 300 mm × 400 mm) 301. As a method for forming the oxide film, a film decomposed and deposited by a sputtering method or a plasma CVD method in an oxygen atmosphere may be used.

Thereafter, the amorphous silicon film is formed in a thickness of 300 to 5000 by plasma CVD or LPCVD.
{Preferably 500-1000} and deposit 5
It was left in a reducing atmosphere at 50 to 600 ° C. for 24 hours to be crystallized. Then, the silicon film thus crystallized is patterned to form the island-shaped active layer regions 303 and 30.
4 was formed. Further, a silicon oxide film 205 having a thickness of 700 to 1500 ° was formed thereon by sputtering.

Thereafter, aluminum having a thickness of 1000 to 3 μm, for example, 6000 ° (0.1 to 0.3 wt%)
(Including Sc) was formed by a sputtering method. Then, in the same manner as in Example 2 (see FIGS. 3A to 3C), a photoresist was formed on the aluminum film by spin coating. Before forming the photoresist, an aluminum oxide film having a thickness of 100 to 1000 ° was formed on the aluminum surface by anodic oxidation. Thereafter, the photoresist and the aluminum film are patterned and etched together with the aluminum film to form a gate electrode 306,
307 and 308 and a wiring 309 were formed. The gate electrode 306, the gate electrode 307, and the gate electrode 308 are electrically independent from each other.
Are electrically connected.

Further, anodization was performed by passing an electric current through the electrolytic solution to form anodized oxide having a thickness of 3000 to 25 μm. The anodization was performed using a 3 to 20% citric acid or an acidic aqueous solution of oxalic acid, phosphoric acid, chromic acid, sulfuric acid or the like, and a constant current of 5 to 30 V was applied to the gate electrode. The anodic oxide thus obtained is porous. In this embodiment, the voltage is set to 8 in an oxalic acid solution (30 ° C.).
V and anodized for 20 to 140 minutes. The thickness of the anodic oxide is controlled by the anodic oxidation time,
And 307 include 500-2000 °, for example, 100
A thin anodic oxide of 0 ° is formed, and the gate electrode 308 and the wiring 309 are provided with 3000 to 9000 °, for example, 500 °.
A thick anodic oxide of 0 ° was formed.

Next, the mask was removed, and a current was again applied to the gate electrode in the electrolytic solution. This time, 3-1
A PH ≒ 7 ethylene glycol solution containing 0% tartaric acid, boric acid, and nitric acid was used. This time, the same voltage was applied to all the gate electrodes and wirings. For this reason, barrier-type anodic oxide was formed on the top and side surfaces of all the gate electrodes and wirings. In the present embodiment, the thickness of the barrier type anodic oxide was 1000 °. (FIG. 5 (A))

Thereafter, the silicon oxide film 305 was etched by a dry etching method. In this etching, a plasma mode of isotropic etching or a reactive ion etching mode of anisotropic etching may be used. However, it is important to prevent the active layer from being etched deeply by sufficiently increasing the selectivity between silicon and silicon oxide. For example, if CF ₄ is used as an etching gas, the anodic oxide is not etched, that is, the silicon oxide film 305 below the gate electrodes 306, 307, 308, and the wiring 313 is not etched, and the gate insulating film is not etched. Membranes 310, 311;
312, and remained as an insulating film 313. (FIG. 5 (B))

Thereafter, the porous anodic oxide was etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. Then, the active layers 303 and 304 of the TFT are formed by ion doping.
Then, impurities were implanted in a self-aligned manner using the gate electrode portion (that is, the gate electrode and the surrounding anodic oxide film) and the gate insulating film as a mask. In this case, various combinations of the impurity regions can be considered depending on the ion acceleration voltage and the dose. For example, the acceleration voltage is set to be as high as 50 to 90 kV, and the dose is set to 1 × 10 ^{13 to} 5 × 10 ¹⁴ cm.
If it is set to ^-2 , most of the impurity ions in the regions 314 to 316 pass through the active layer and show the maximum concentration in the base film. Therefore, the regions 314 to 316 are extremely low-concentration impurity regions. On the other hand, the gate insulating film 310
In the regions 317 to 319 where the region 312 is present, the high-speed ions are decelerated by the gate insulating film, and the impurity concentration is maximized, so that a low-concentration impurity region can be formed.

Conversely, if the acceleration voltage is set as low as 5 to 30 kV and the dose is set as large as 5 × 10 ^{14 to} 5 × 10 ¹⁵ cm ⁻² , many impurity ions are formed in the regions 314 to 316. Is implanted to form a high-concentration impurity region. On the other hand, regions 317 to 3 where gate insulating films 310 to 312 exist
In 19, low-speed ions are prevented by the gate insulating film, the amount of implanted impurity ions is low, and a low-concentration impurity region can be formed. As described above, regardless of which method is used, the regions 317 to 319 become low-concentration impurity regions, and in this embodiment, any method may be employed. Thus, ion doping is performed, and N
After forming the low-concentration impurity regions 317 and 319 and the low-concentration impurity regions 318 of the P type, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) is irradiated to activate the impurity ions introduced into the active layer. Was done. This step may use RTP (rapid thermal process). (FIG. 5 (C))

As a result, the width of the high resistance region (that is, the low concentration region and the offset region) was different for each TFT. That is, in the N-channel type TFT of the driver circuit, the width x ₁ of the high resistance region is 2000Å plus width 1000Å lightly-doped region in the offset width 1000Å, also P
In the channel type TFT, x ₂ is 1000 ° which is only the width of the low concentration region, and in the pixel control TFT,
x ₃ is the width 500 of the low-density region to the offset width 1000Å
It was 6000 ° with 0 ° added.

Further, a coating of a suitable metal, for example, titanium, nickel, molybdenum, tungsten, platinum, palladium, etc., for example, a titanium film 320 having a thickness of 50 to 500.degree. As a result, the metal film (here, titanium film) 320 was formed in close contact with the high concentration (or extremely low concentration) impurity regions 314 to 316. (FIG. 5 (D))

Then, irradiation with a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) reacts the metal film (here, titanium) with the silicon of the active layer,
Regions 330-33 of metal silicide (here titanium silicide)
2 was formed. Laser energy density 200 ~ 4
00 mJ / cm ² , preferably 250 to 300 mJ / c
m ² was appropriate. In addition, when the substrate was heated to 200 to 500 ° C. during laser irradiation, peeling of the titanium film could be suppressed. In this embodiment, an excimer laser is used as described above, but it goes without saying that another laser may be used. However, when using a laser, a pulsed laser is preferred. In the case of a continuous wave laser, the irradiation time is long, and there is a risk that an object to be irradiated is separated by expansion due to heat.

As for the pulse laser, Nd: YAG
Infrared laser such as laser (preferably Q-switched pulse oscillation) and its visible light such as its second harmonic, Kr
Various ultraviolet lasers using excimers such as F, XeCl, and ArF can be used. However, when laser irradiation is performed from the upper surface of the metal film, it is necessary to select a laser having a wavelength that is not reflected by the metal film. However, there is almost no problem when the metal film is extremely thin. Further, the laser light may be applied from the substrate side. In this case, it is necessary to select a laser beam that passes through the underlying silicon semiconductor film.

The annealing may be performed by lamp annealing by irradiation of visible light or near infrared light.
When lamp annealing is performed, the surface to be irradiated is 600
The lamp irradiation is performed for several minutes at 600 ° C. and for several tens of seconds at 1000 ° C. so that the temperature becomes about 1000 ° C. Annealing with near-infrared rays (for example, 1.2 μm infrared rays) selectively absorbs near-infrared rays into silicon semiconductors and does not heat the glass substrate so much. It is convenient in use because it can be suppressed.

Thereafter, the unreacted titanium film was etched with an etching solution in which hydrogen peroxide, ammonia and water were mixed at a ratio of 5: 2: 2. The titanium film other than the portion in contact with the exposed active layer (for example, the titanium film existing on the gate insulating film or the anodic oxide film) remains in a metal state as it is,
It can be removed by this etching. On the other hand, since titanium silicide 330 to 332 which is a metal silicide is not etched,
It could be left. In this embodiment, the silicide region 3
The sheet resistance of 30 to 332 was 10 to 50 Ω / □. On the other hand, in the low concentration impurity regions 317 to 319, 10 to 10
It was 100 kΩ / □.

The NT of the active matrix circuit
500-3000mm thick on FT337, eg 10
A silicon nitride film 322 of 00 ° was formed. Generally, a silicon nitride film has a property of capturing holes. Therefore, in applications in which hot carriers are easily generated, for example, in a TFT of an active matrix circuit, etc., the silicon nitride film 322 is used to prevent charge-up of electrons due to hot electrons in the gate insulating film due to hot carrier injection.
Was effective. However, in the case of a PTFT, the silicon nitride film is preferably not formed in a portion where a complementary circuit exists, since the effect is opposite. In the present embodiment, the reason why the silicon nitride film is left only in the active matrix circuit (right side in the figure) is as described above.

Further, an interlayer insulator 321 is formed on the entire surface.
The silicon oxide film is formed to a thickness of 2000 to 1 μm by the CVD method.
m, for example, 5000 °. Then, the wiring 309
Then, a hole 324 was formed, and the silicon nitride film 322 was exposed.
Then, an ITO film was formed by a sputtering method, and this was patterned and etched to form a pixel electrode 323. The pixel electrode 323 has a barrier type anodic oxide (1000Å) and a silicon nitride film (1000Å) in the hole 324.
To form a capacitance with the wiring 309. On this occasion,
Both anodic oxide and silicon nitride have a large dielectric constant and are thin, so that a large capacity can be obtained with a small area. This capacity is
It is used as a so-called storage capacitor which is inserted in parallel with the capacitor formed by the pixels of the active matrix and the counter electrode. That is, the wiring 309 is kept at the same potential as the counter electrode.

Thereafter, the interlayer insulator 321 is etched to form contact holes in the source / drain of the TFT, the gate electrode, and the like, and a wiring / electrode of a multilayer film of titanium nitride and aluminum having a thickness of 2000 to 1 μm, for example, 5000 mm is formed. 325-329 were formed. (FIG. 5
(E)) In the present embodiment, N
The value of the high resistance region width of the TFT 337, the decoder, the CPU, the memory, the NTFT for high frequency and low power consumption, the NTFT for the driver for high power driving, and the PTFT are the same as those in the second embodiment. Thus, in a thin film integrated circuit having a monolithic electro-optical device, an N-channel TF
T and P channel TFTs have been shown to optimize the width of the high resistance region. FIG. 6 is a block diagram of an electro-optical system using an integrated circuit in which a display, a CPU, and a memory are mounted on one glass substrate. In the first to third embodiments, only the active matrix circuit and the X and Y decoders / drivers are mainly shown, but if this embodiment is developed,
It is easy to imagine that it is possible to construct more advanced circuits and systems.

Here, the input port means that a signal inputted from the outside is read and converted into an image signal, and the correction memory is unique to a panel for correcting an input signal or the like in accordance with the characteristics of the active matrix panel. Memory. In particular, this correction memory is used for financing and individually correcting information unique to each pixel as a nonvolatile memory. That is, if a pixel of the electro-optical device has a point defect, a signal corrected in accordance therewith is sent to pixels around the point to cover the point defect and make the defect inconspicuous. Or, if the pixel is darker than the surrounding pixels,
A larger signal is sent to the pixel so that the surrounding pixels have the same brightness. The CPU and the memory are the same as those of an ordinary computer. In particular, the memory has an image memory corresponding to each pixel as a RAM. Further, the backlight that irradiates the substrate from the back surface can be changed according to the image information.

Then, in order to obtain the width of the high resistance region suitable for each of these circuits, it is only necessary to form three to ten systems of wirings so that the anodic oxidation conditions can be individually changed. Typically, in an active matrix circuit, the channel length is 10 μm and the width of the high resistance region is 0.4
１1 μm, for example, 0.6 μm. In the driver, an N-channel TFT has a channel length of 8 μm and a channel width of 200 μm, and the width of the high resistance region is 0.2 to 0.3.
μm, for example, 0.25 μm. P-channel type TF
In T, the channel length is 5 μm and the channel width is 500 μm.
m, and the width of the high resistance region is 0 to 0.2 μm, for example,
0.1 μm. In the decoder, N-channel type TF
At T, the channel length is 8 μm and the channel width is 10 μm, and the width of the high resistance region is 0.3 to 0.4 μm, for example, 0.35 μm.
μm. Similarly, in a P-channel type TFT, the channel length may be 5 μm and the channel width may be 10 μm, and the width of the high resistance region may be 0 to 0.2 μm, for example, 0.1 μm. Further, the width of the high resistance region may be optimized for the CPU, the input port, the correction memory, and the NTFT and PTFT of the memory in FIG. 6, similarly to the decoder for high frequency operation and low power consumption. Thus, the electro-optical device 64 could be formed on the same substrate having an insulating surface.

In the present invention, the width of the high resistance region is set to 2 to
It is characterized in that it can be changed to four types or more depending on the application. In addition, this region does not need to be exactly the same material and the same conductivity type as the channel formation region. That is, in the NTFT, a small amount of N-type impurities and P
In a TFT, a small amount of P-type impurity is added, and carbon, oxygen, nitrogen or the like is selectively added to form a high-resistance region.
This is effective in eliminating a trade-off with off current.

[0055]

According to the present invention, a TFT having a high resistance region having an optimum width in accordance with the characteristics and reliability required of each TFT.
The FT can be manufactured on the same substrate. as a result,
Unprecedented flexibility can be obtained, and a highly integrated circuit can be configured. As described above, the present invention is an invention having great industrial value. In particular, a TFT group is formed on a large-area substrate, and the TFT group is used for an active matrix, a driver circuit, a CPU, and a memory to form an electro-optical system. If the board is an ultra-thin personal computer or a mobile terminal, the field of use can be expanded without limit. Furthermore, the electro-optic system is intelligent and has sufficient qualities to form a new industry by being combined with other single crystal semiconductor CPUs, computer systems, and image processing systems.

[Brief description of the drawings]

FIG. 1 illustrates a method for manufacturing a TFT circuit. (Cross section, Example 1)

FIG. 2 illustrates a method for manufacturing a TFT circuit. (Top view, Example 1)

FIG. 3 illustrates a method for manufacturing a TFT circuit. (Cross-sectional view, Example 2)

FIG. 4 illustrates a method for manufacturing a TFT circuit. (Top view, Example 2)

FIG. 5 illustrates a method for manufacturing a TFT circuit. (Cross-sectional view, Example 3)

FIG. 6 shows an example of a block diagram of an integrated circuit.

[Explanation of symbols]

Reference Signs List 101 substrate 102 base insulating film 103, 104 island-shaped semiconductor region (silicon) 105 gate insulating film (silicon oxide) 106-109 gate electrode / wiring (aluminum) 110-113 anodic oxide (aluminum oxide) 114, 116 N-type impurity Region 115 P-type impurity region 117 Interlayer insulator (silicon oxide) 118 Pixel electrode (ITO) 119 Contact hole 120 to 124 Metal wiring (titanium nitride / aluminum)

 ──────────────────────────────────────────────────の Continuing from the front page (72) Inventor, Mutsuo Yamamoto 398 Hase, Hase, Atsugi-shi, Kanagawa Prefecture Inside the Semi-Conductor Energy Laboratory Co., Ltd.

Claims (3)

[Claims] A step of forming first and second semiconductor regions on an insulating surface; a step of forming an insulating film on the first and second semiconductor regions; and a step of forming the first and second semiconductor regions. Forming a gate electrode on each of the regions via the insulating film; forming a porous anodic oxide on the gate electrode on the first semiconductor region; Forming a barrier-type anodic oxide on a gate electrode on the semiconductor region, and using the gate electrode, the porous anodic oxide, and the barrier-type anodic oxide as masks to form the first and second semiconductor regions. Forming an offset region having a different width between the first semiconductor region and the second semiconductor region in the first and second semiconductor regions by adding an impurity to the semiconductor. Device manufacturing method. A step of forming first and second semiconductor regions on an insulating surface; a step of forming an insulating film on the first and second semiconductor regions; and a step of forming the first and second semiconductor regions. Forming a gate electrode on each of the regions via the insulating film; and forming a gate electrode on the first and second semiconductor regions on the first semiconductor region and the second semiconductor region. A step of forming a porous anodic oxide having a different thickness from the above, a step of forming a barrier type anodic oxide on the gate electrode on the second semiconductor region, and the step of forming the gate electrode and the porous anodic oxide Using the barrier anodic oxide as a mask, etching the insulating film to pattern the insulating film, removing the porous anodic oxide by etching, the gate electrode, the patterned Insulation The first and second films using the film and the barrier type anodic oxide as a mask.
Adding an impurity to the first semiconductor region and forming a low-concentration impurity region having a width different from each other in a channel length direction in the first semiconductor region and the second semiconductor region;
Forming an offset region only in the semiconductor region of (1). A step of forming first and second semiconductor regions on an insulating surface; a step of forming an insulating film on the first and second semiconductor regions; and a step of forming the first and second semiconductor regions. Forming a gate electrode on each of the regions via the insulating film; and forming a gate electrode on the first and second semiconductor regions on the first semiconductor region and the second semiconductor region. Forming a porous anodic oxide having a different thickness between the first and second semiconductor regions; and forming a gate electrode on the first and second semiconductor regions on the first and second semiconductor regions. Forming a barrier type anodic oxide having the same thickness; and patterning the insulating film by etching the insulating film using the gate electrode, the porous anodic oxide, and the barrier type anodic oxide as a mask. And etching the porous anodic oxide Removing the grayed, the gate electrode, said patterned insulating film as a mask the barrier type anodic oxide, the first and second
Forming a low-concentration impurity region having different widths in a channel length direction in the first semiconductor region and the second semiconductor region by adding an impurity to the first semiconductor region. .