JPH10190410A - Digital filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a circuit scale in a digital filter which consists of multipliers and an adder, etc. SOLUTION: This filter consists of plural delaying means 1 which delay a digital signal of m bits which are inputted from an input terminal 8, bit number reducing means 4-i (i=1,...L) which reduce the bit number of each of these delayed signals into mi (i=1,...L) which is mi <=m, bit number reducing means 5-i (i=1,...L) which reduce the bit number of a coefficient ai (0<ai<1, i=1,...L) into ni (i=1,...L) which is ni <=n, multipliers 2-i (i=1,...L) which multiply an output signal of the means 4-i (i=1,...L) by a coefficient that is outputted from the means 5-i (i=1,...L) respectively and an adder 3 which separately shifts output signals of the multipliers 2-i (i=1,...L) by only (m-mi ) in the direction of a high order and adds them. The mi is separately selected to satisfy mi >m+ log2 ai (i=1,...L).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter having a multiplier and an adder as components.

[0002]

2. Description of the Related Art Conventionally, a digital filter for processing a digital signal, and in particular, a digital filter for changing a filter characteristic by changing a coefficient value, is, for example, "Digital signal processing of image" (author: Takahiko Fuukiki) (Publisher: Nikkan Kogyo Shimbun) Figure 7-4 on page 97
It is disclosed in (a). FIG. 9 shows an FIR filter having the number of taps L as an example.

In FIG. 9, reference numeral 8 denotes an input terminal to which m-bit digital signal data is input, and 1 denotes a delay means for delaying the input signal data by a data period D.
It is composed of flip-flops. 2-i (i = 1,..., L) is a multiplier, and n-bit coefficient data a _i (i = 1) input from the input terminal 7-i (i = 1,. ,..., L) are multiplied by m-bit delayed signal data output from the respective delay means. 3 is an adder, which is output from each of the multipliers (m _i
+ N _i ) -bit signals are added and output from the output terminal 9.

The operation of the digital filter thus configured will be described below. Input signal data input from the input terminal 8 at a certain discrete time j is D _I (j),
Assuming that the output signal data output from the output terminal 9 is Do (j), an operation represented by the following equation is performed.

[0005]

(Equation 1)

FIGS. 10 (a), 10 (b) and 10 (c) show examples of three types of coefficient data given to the digital filter, respectively, and correspond to LPFs having different cutoff frequencies. In the digital filter having the above configuration, LPFs having various cutoff frequencies can be realized by changing the coefficient data while maintaining the same configuration.

[0007]

However, usually,
In order to obtain sufficient filter characteristics, the tap length L should be 10
As described above, the number of bits n of the coefficient data is also 10 bits or more, and when the input signal is a video signal, m is also a value of 10 or more. In the above-described conventional configuration, since many multipliers are included, the circuit scale is large. Has the problem of becoming large.

An object of the present invention is to solve the above-mentioned conventional problems and to provide a digital filter having a reduced circuit scale.

[0009]

In order to achieve the above object, a digital filter according to the present invention has the following arrangement.

The first configuration comprises a plurality of delay means for delaying an m-bit input signal by a predetermined time, and higher-order _mi (i = 1,..., L) of the delay signal output from the delay means. ) Bits and coefficient data consisting of only n _i (i = 1,..., L) effective bits, respectively, and output signals output from the L multipliers Are shifted by (m−m _i ) bits in the upper bit direction and added, and the value of the _mi (i = 1,..., L) is changed to a value satisfying m _i ≦ m. It is characterized by choosing.

In the above configuration, preferably, when the L coefficients are a _i (0 <a _i <1, i = 1,..., L), the m
_i (i = 1,..., L) is selected as an integer that satisfies m _i > m + log ₂ a _i (i = 1,..., L).

In the above configuration, preferably, L
Are the coefficients a _i (0 <a _i <1, i = 1,..., L), and the coefficient a _i (i = 1,. was a a _max, the coefficients a _i of L in this _{a max (i = 1, ···} , L) those each normalized b _{i (i} = 1, ··
., L), the above-mentioned _mi (i = 1,..., L) is expressed as _mi > m + log ₂
Choose an integer that satisfies b _i (i = 1,..., L).

The second configuration comprises a plurality of delay means for delaying an m-bit input signal by a predetermined time, and higher-order _mi (i = 1,..., L) of the delay signal output from the delay means. ) Bits and coefficient data consisting of only n _i (i = 1,..., L) effective bits, respectively, and L multipliers each outputting (L) m <sub>i
+ N i) (i = 1</sub> , ···, L) , respectively upper p _{i (i} = 1 of the output signal data bits, · · ·, L) consists adder for adding the bits, the smallest among the m _i those when was the m _min of the value of p _i each _{m min + n i <p i} ≦
A value that satisfies m _i + n _i (i = 1,..., L) is selected.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS. (Embodiment 1) FIG. 1 is a diagram showing a configuration of a digital filter according to (Embodiment 1), and the same components as those in the conventional example are given the same numbers. Reference numeral 8 denotes an input terminal to which m-bit signal data is input, and 1 denotes a delay means for delaying the input signal data by a data period D, and is usually constituted by a D flip-flop. 2-i (i = 1,..., L) are multipliers each having (m _i × n _i ) (i = 1,..., L) input bits.
7-i (i = 1,..., L) is n-bit coefficient data a _i (i = 1,..., L)
Are input terminals to be input respectively. 4-i (i = 1, ..., L)
Is a bit number reducing means for outputting higher-order _mi (i = 1,..., L) bits of the input m-bit signal data. Therefore, the number of bits of the signal data of each tap is reduced from m to _mi (m _i ≦ m), and the multiplier 2-i (i = 1,
.., L). 5-i (i = 1,..., L) is a bit number reducing means, and lower n _i (i = 1,..., L) bits which are effective bits of the inputted n-bit coefficient data. Are output. Therefore, the number of bits of the coefficient data a _i of each tap is reduced from n to _ni ( _ni ≦ n), and
i (i = 1,..., L). An adder 3 is output from the multiplier 2-i (i = 1,..., L) (m _i + n
_i ) (i = 1,..., L)
_i ) Bit shift is performed in the upper bit direction (that is, leftward direction) by bits and added.

Next, the specific number of bits of each component will be described with reference to FIGS. In this embodiment, an input digital video signal is processed, and the number m of bits of the input signal is 10 bits, and the number n of bits of coefficient data a _i of a filter input from the outside is 1 including a code.
It is assumed that 0 bits and the tap number L of the filter is 14.

FIG. 2 shows an input terminal 7-i (i = 1,..., L) when the coefficient values set in this embodiment are the three types shown in FIG.
It shows the length of effective bits that are not always 0 among the bits of each coefficient data a _i of n = 10 bits input from each of the taps.

FIG. 3 compares the number of input bits of each multiplier of this embodiment with that of the conventional configuration. In this embodiment, the number of bits of the signal input of each multiplier is selected so as to satisfy, for example, m _i ≦ m as shown in FIG.
The number of bits of the coefficient input is made to match the effective bit length of the coefficient of FIG. 2 as shown in FIG.

The operation of the digital filter of the present invention configured as described above will be described with reference to FIG. The 10-bit signal data input from the input terminal 8 is respectively delayed by the delay means 1 and then, as shown in FIG. 3A, the bit number reduction means 5-i (i = 1,..., The number of bits is reduced in L) and input to each multiplier 2-i (i = 1,..., L). on the other hand,
For example, 10-bit coefficient data shown in FIG. 10A is input from the input terminal 7-i (i = 1,..., L), and the number of bits is set as shown in FIG. Is reduced, and is input to each of the multipliers 2-i (i = 1,..., L). Since the multipliers have different numbers of input bits, the multipliers have different numbers of output bits as shown by hatching in FIG. Therefore, as shown by the arrow in FIG. 4, the adder 3 adds (m-m _i ) bits to the left after each shifting in order to align the bit position (digit) of each multiplication output. In this way, output signal data that has been subjected to LPF processing corresponding to the coefficient of FIG. 10A can be obtained from the adder 3.

As described above, the digital filter of the present invention can be configured with a multiplier having a smaller number of input bits than the conventional one, and the circuit scale can be reduced. Further, in the present invention, since the effective bits of the coefficient data are secured as they are, exactly the same filter characteristics as those of the related art are realized.

In this embodiment, an example of the FIR type LPF has been described, but an IIR type or HPF may be used. Embodiment 2 In Embodiment 1, since the number of bits of signal data input to each multiplier is reduced,
An operation error is added. This embodiment is one method for reducing this calculation error without reducing the amount of circuit reduction. Its configuration and operation are the same as those of the first embodiment.

[0021] In this embodiment, coefficient data a _i the number of bits reduced in is the same as (Embodiment 1), the integer m _i that satisfies the following formula the number of bits of the signal input of each multiplier
(I = 1,..., L).

[0022]

(Equation 2)

Hereinafter, the effect of this embodiment will be specifically described. Assuming that n = 10, m = 10, L = 14, and the filter coefficient data a _i values are as shown in the following (Table 1), the multiplier input signal data in this embodiment calculated according to (Equation 2) The bit number m _i of FIG.
become that way. Therefore, the circuit scale of the multiplier is much smaller than in the first embodiment.

[0024]

[Table 1]

On the other hand, the total quantization noise amount N (quantization noise originally included in the input signal + operation error) contained in the output signal of the digital filter of FIG.
It can be calculated according to (Equation 4).

[0026] However, e _mi by the following equation, e _m, respectively m _i,
This is the quantization noise of m-bit data.

[0027]

(Equation 3)

[0028]

(Equation 4)

[0029] When calculated according to the above equation (Embodiment 1) and the total quantization noise amount N1, N2 of the output signal of this _{embodiment, N1 = 4.26 · e 10,} N2 = 2.43 · e 10
Thus, according to this embodiment, the calculation error is improved.

As described above, according to this embodiment, there is an advantage that not only the circuit scale can be reduced but also the calculation error can be reduced. (Embodiment 3) This embodiment is another method for reducing the calculation error without reducing the amount of circuit reduction. Its configuration and operation are the same as those of the first embodiment.

[0031] In this embodiment, coefficient data a _i the number of bits reduced in is the same as (Embodiment 1), the integer m _i that satisfies the following formula the number of bits of the signal input of each multiplier
(I = 1,..., L). Where a _max is a _i (i = 1,..., L)
Is the value of the largest one.

[0032]

(Equation 5)

Hereinafter, the effect of this embodiment will be specifically described. n = 10, m = 10, L = 14, the coefficient data a _i values of the filter and the was as in (Table 1), the m _i of this embodiment calculated according equation (5) 6 become that way. Therefore, the circuit scale of the multiplier is smaller than in the first embodiment.

When the total quantization noise amount N3 of the output signal of this embodiment is calculated according to the above (Equation 3) and (Equation 4),
N3 = 0.84 · e _10, and the calculation error according to this embodiment is significantly improved. As described above, according to this embodiment, there is an advantage that not only the circuit scale can be reduced but also the calculation error can be reduced.

(Embodiment 4) FIG. 7 shows (Embodiment 4).
FIG. 2 is a diagram showing a configuration of a digital filter according to the first embodiment, and the same components as those in the conventional example are denoted by the same reference numerals.

6-i (i = 1,..., L) is a bit number reducing means.
Higher p of input signal data_i(i = 1, ..., L) bits
Each is output. Therefore, the output signal of each multiplier
The number of data bits is (m_i + N_i ) To p_i Reduced to
And input to the adder 3. In this embodiment,
Number of input bits m of signal data of multiplier 2-i (i = 1,..., L) _i 
M is the smallest one of_min Satisfies the following equation
Integer p_i (I = 1,..., L) are selected.

[0037]

(Equation 6)

The other structure is the same as that of the first embodiment, and the method of selecting the bit numbers m _i and n _i (i = 1,..., L) is the same as that of the second embodiment. And Next, the operation of this embodiment will be described with reference to FIG.

The operation until the multiplication result is output from each multiplier is the same as that of the first embodiment. FIG. 8 shows the number of bits of the output signal of each multiplier by oblique lines. X in FIG.
At least one of the L = 14 pieces of signal data input to the adder 3 includes bits that are not valid bits in the bits lower than the bit position indicated by. Therefore, even if the bits lower than X in FIG. 8 are added, a valid result cannot be obtained with the bits lower than X in the data after the addition.
The condition for discarding bits lower than X in the output signal of each multiplier is (Equation 6). In this way, according to this embodiment, without increasing the calculation error due to the truncation of the output signal of each multiplier,
The circuit size of the adder 3 can be reduced. Also, by cutting off lower bits in advance, the adder 3
This eliminates the need to perform a bit shift for each input data.

[0040]

As described above, according to the present invention, a digital filter is provided with a bit number reducing means to reduce the number of bits of signal data and coefficient data, and then input these to a multiplier and an adder. Thus, the circuit scale of the filter can be reduced. Further, by determining how to reduce the number of bits in accordance with the magnitude of each coefficient, it is possible to reduce the circuit scale without increasing the calculation error.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a digital filter according to Embodiment 1;

FIG. 2 is a diagram showing an effective bit length of a filter coefficient according to the first embodiment.

FIG. 3 is a diagram illustrating the number of bits of a signal input of the multiplier according to the first embodiment and a diagram illustrating the number of bits of a coefficient data input of the multiplier;

FIG. 4 is a diagram illustrating an operation of an adder according to the first embodiment.

FIG. 5 is a diagram showing the number of bits of a signal input of a multiplier according to the second embodiment.

FIG. 6 is a diagram illustrating the number of bits of a signal input of a multiplier according to a third embodiment.

FIG. 7 is a configuration diagram of a digital filter according to a fourth embodiment.

FIG. 8 is a diagram illustrating an operation of a bit number reducing unit according to (Embodiment 4);

FIG. 9 is a configuration diagram of a conventional digital filter.

FIG. 10 is a diagram showing an example of filter coefficient data of a conventional digital filter, a diagram showing another example of filter coefficient data, and a diagram showing still another example of filter coefficient data.

[Explanation of symbols]

 1 delay means 2-1,2-2, ~ 2-L multiplier 3 adder 4-1,4-2, ~ 4-L bit number reduction means 5-1,5-2, ~ 5-L bit number Reduction means 6-1,6-2, ~ 6-L Bit number reduction means 7-1,7-2, ~ 7-L Bit number reduction means 8 Input terminal 9 Output terminal

Claims (5)

[Claims] 1. A plurality of delay means for delaying an m-bit input signal by a predetermined time, respectively;
_{i (i = 1, ···,} L) bits and each _{n i (i = 1, ···} , L) and L multipliers for multiplying the coefficient data comprising only effective bits of the bit, respectively, which Output signals of the L multipliers are respectively (m−m _i )
A digital filter comprising: an adder that shifts by bits in a higher-order bit direction and adds the values, and selects the value of m _i (i = 1,..., L) to a value satisfying m _i ≦ m. . 2. The method according to claim 1, wherein the L pieces of coefficient data are represented by a _i (0 <a _i <1,
i = 1, ···, when the L), the _{m i (i = 1, ···} , L) a m _i> m
_2. The digital filter according to claim 1, wherein an integer satisfying + log ₂ a _i (i = 1,..., L) is selected. 3. The method according to claim 1, wherein the L coefficients are a _i (0 <a _i <1, i = 1,.
·, L), the coefficients _{a i (i = 1, ···} , those with the largest magnitude among L) and a _max, the coefficient of the L in this a _max a
_i (i = 1, ..., L) are normalized to b _i (i = 1, ...,
L), m _i (i = 1,..., L) is defined as m _i > m + log ₂ b
_2. The digital filter according to claim 1, wherein an integer satisfying _i (i = 1,..., L) is selected. 4. The higher-order p _i (i = 1,...) Of (m _i + n _i ) (i = 1,..., L) bits of output signal data output from the L multipliers. , L) bits are input to the adder, and the p _i (i = 1,..., L) is replaced by p _i ≦ m _i + n _i (i = 1,.
2. The digital filter according to claim 1, wherein a value that satisfies is satisfied. 5. When the smallest one of the m _i is m _min , the p _i (i = 1,..., L) is defined as p _i > m _min + n _i (i = 1,
5. The digital filter according to claim 4, wherein an integer satisfying..., L) is selected.