JPH10190051A - Led light emitting element - Google Patents
Led light emitting elementInfo
- Publication number
- JPH10190051A JPH10190051A JP34177296A JP34177296A JPH10190051A JP H10190051 A JPH10190051 A JP H10190051A JP 34177296 A JP34177296 A JP 34177296A JP 34177296 A JP34177296 A JP 34177296A JP H10190051 A JPH10190051 A JP H10190051A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- light emitting
- led light
- epitaxial growth
- emitting element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims description 20
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052737 gold Inorganic materials 0.000 abstract description 3
- 239000010931 gold Substances 0.000 abstract description 3
- 239000000919 ceramic Substances 0.000 description 11
- 239000011347 resin Substances 0.000 description 6
- 229920005989 resin Polymers 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 239000002390 adhesive tape Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Led Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はＬＥＤランプの発光
源とされるＬＥＤチップに関するものであり、詳細には
そのＬＥＤチップの構成に係るものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LED chip serving as a light emitting source of an LED lamp, and more particularly to a structure of the LED chip.
【０００２】[0002]
【従来の技術】従来のこの種のＬＥＤ発光素子９０、８
０の構成の例を示すものが、図９〜図１０であり、一方
の面にエピタキシャル成長面９１ａが形成された、例え
ばGaAsP 基板（ウエハー）９１のエピタキシャル成長面
９１ａ側から拡散を行い、この基板９０の全面に所定の
深さのＰＮ接合面９２を形成する。2. Description of the Related Art Conventional LED light emitting devices 90 and 8 of this type are known.
FIGS. 9 and 10 show an example of the structure of FIG. 0. Diffusion is performed from the epitaxial growth surface 91a side of, for example, a GaAsP substrate (wafer) 91 having an epitaxial growth surface 91a formed on one surface. A PN junction surface 92 having a predetermined depth is formed on the entire surface of the substrate.
【０００３】続いて、ＬＥＤ発光素子９０の他方の面９
１ｂ、即ち、エピタキシャル成長面９１ａが形成されて
いない側の面の全面にＮ電極９３を形成すると共に、エ
ピタキシャル成長面９１ａ側にはドット状にＰ電極９４
を形成し、しかる後に基板９１を縦横に切断し、図９に
示すＬＥＤ発光素子９０を得るものである。Subsequently, the other surface 9 of the LED light emitting element 90
1b, that is, the N electrode 93 is formed on the entire surface where the epitaxial growth surface 91a is not formed, and the P electrode 94 is formed in a dot shape on the epitaxial growth surface 91a side.
Is formed, and then the substrate 91 is cut lengthwise and crosswise to obtain the LED light emitting element 90 shown in FIG.
【０００４】また、途中過程の図示は省略するが、前記
エピタキシャル成長面９１ａの全面にＰ電極９４を形成
し、この基板９１を上記と同様に縦横に切断すること
で、図１０に示すようにエピタキシャル成長面９１ａと
他方の面９１ｂとが共に覆われたＬＥＤ発光素子８０を
形成することもある。Further, although illustration of the intermediate process is omitted, a P electrode 94 is formed on the entire surface of the epitaxial growth surface 91a, and the substrate 91 is cut vertically and horizontally in the same manner as described above. The LED light emitting element 80 in which both the surface 91a and the other surface 91b are covered may be formed.
【０００５】ここで、図９に示したＬＥＤ発光素子９０
を、セラミック基板６０に取付ける場合には、図１１に
示すように、Ｎ電極９３側はセラミック基板６０にダイ
ボンドを行い、Ｐ電極９４側は金ワイヤーなどによりワ
イヤーボンドを行うことで固定と配線とを行うものであ
り、従って、ＰＮ接合面９２はセラミック基板６０に対
し平行の状態となる。Here, the LED light emitting device 90 shown in FIG.
Is attached to the ceramic substrate 60, as shown in FIG. 11, the N-electrode 93 side is die-bonded to the ceramic substrate 60, and the P-electrode 94 side is wire-bonded with a gold wire or the like, thereby fixing and wiring. Therefore, the PN junction surface 92 is parallel to the ceramic substrate 60.
【０００６】また、図１０に示すＬＥＤ発光素子８０
を、上記と同様なセラミック基板６０に取付ける場合に
は、図１２に示すようにＬＥＤ発光素子８０をＮ電極９
３とＰ電極９４とが前記セラミック基板６０に接触する
状態として載置し、この状態でハンダ付け、導電接着剤
による接着などにより取付けを行うものである。従っ
て、ＰＮ接合面９２はセラミック基板６０に対し鉛直の
状態となる。The LED light emitting device 80 shown in FIG.
When the LED light emitting element 80 is mounted on the same ceramic substrate 60 as described above, the LED light emitting element 80 is connected to the N electrode 9 as shown in FIG.
3 and the P electrode 94 are placed in a state of being in contact with the ceramic substrate 60, and in this state, they are attached by soldering or adhesion with a conductive adhesive. Therefore, the PN junction surface 92 is vertical to the ceramic substrate 60.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、前記し
た従来の構成のＬＥＤ発光素子８０、９０においては、
先ず、ＬＥＤ発光素子８０ではエピタキシャル成長面９
１ａと他方の面９１ｂとが共にＮ電極９３とＰ電極９４
とで完全に覆われると共に、セラミック基板６０に取付
けを行う際に側面の一面に接するものと成るので、都合
３面が覆われて発光量が減少する問題点を生じている。However, in the LED light emitting elements 80 and 90 having the above-mentioned conventional configuration,
First, in the LED light emitting device 80, the epitaxial growth surface 9
1a and the other surface 91b are both N-electrode 93 and P-electrode 94
, And comes into contact with one surface of the side surface when mounting to the ceramic substrate 60. Therefore, there is a problem that three surfaces are covered and the amount of light emission is reduced.
【０００８】また、ＬＥＤ発光素子９０では、確かに５
面から光は放射されるものとなるが、光を取出すときの
主方向となるエピタキシャル成長面９１ａにＰ電極９４
が設けられると共に金ワイヤーなどによる影も生じるも
のと成るので、上記と同様に発光量が減少する問題点を
生じている。Also, in the LED light emitting device 90, it is
Although light is emitted from the surface, a P electrode 94 is formed on the epitaxial growth surface 91a which is a main direction when extracting light.
Is provided, and a shadow due to a gold wire or the like also occurs, which causes a problem that the light emission amount is reduced in the same manner as described above.
【０００９】更には、ＬＥＤ発光素子８０においても、
ＬＥＤ発光素子９０においてもＰＮ接合面９２が側面に
露出するものとなるので、例えばモールドによる樹脂ケ
ースで覆うなど厳重な防湿処理が要求され、これにより
生産時の工数が増加したり、或いは、大型化するなどの
問題点を生じ、これらの点の解決が課題とされるものと
なっている。Further, also in the LED light emitting element 80,
Also in the LED light emitting element 90, since the PN junction surface 92 is exposed on the side surface, strict moisture-proof treatment is required, for example, by covering with a resin case by molding, thereby increasing man-hours during production or However, there are problems such as becoming more serious, and the solution of these problems is becoming an issue.
【００１０】尚、図１１および図１２に示したものは、
何れもＬＥＤ発光素子９０、８０を用いて面実装型のＬ
ＥＤランプを形成したときの例であり、上記した樹脂ケ
ース６１を形成するために、一旦、ＬＥＤ発光素子９０
を端子部６０ａ、配線部６０ｂが形成されたセラミック
基板６０上にマウントし、そして、このセラミック基板
６０上に樹脂ケース６１を形成するものである。Incidentally, those shown in FIG. 11 and FIG.
Each of them is a surface mount type L using LED light emitting elements 90 and 80.
This is an example in which an ED lamp is formed. In order to form the resin case 61, the LED light emitting element 90
Are mounted on the ceramic substrate 60 on which the terminal portions 60a and the wiring portions 60b are formed, and the resin case 61 is formed on the ceramic substrate 60.
【００１１】[0011]
【課題を解決するための手段】本発明は前記した従来の
課題を解決するための具体的な手段として、基板のエピ
タキシャル成長面に拡散を行いＰＮ接合面を形成し、該
ＰＮ接合面に対して駆動電力を供給するためのＰ電極お
よびＮ電極が設けられて成るＬＥＤ発光素子において、
前記ＰＮ接合面は前記エピタキシャル成長面上に設けた
絶縁層に開口部を設けて拡散を行うことで前記エピタキ
シャル成長面に選択的に形成し、このＰＮ接合面上にＰ
電極を設けると共に、前記エピタキシャル成長面のＰＮ
接合面が形成されていない部分にＮ電極が設けられてい
ることを特徴とするＬＥＤ発光素子を提供することで課
題を解決するものである。As a concrete means for solving the above-mentioned conventional problems, the present invention forms a PN junction surface by diffusing on an epitaxial growth surface of a substrate, and with respect to the PN junction surface, In an LED light emitting element provided with a P electrode and an N electrode for supplying driving power,
The PN junction surface is selectively formed on the epitaxial growth surface by providing an opening in an insulating layer provided on the epitaxial growth surface and performing diffusion, and P is formed on the PN junction surface.
An electrode is provided and PN of the epitaxial growth surface is provided.
The problem is solved by providing an LED light-emitting element characterized in that an N electrode is provided in a portion where a bonding surface is not formed.
【００１２】[0012]
【発明の実施の形態】つぎに、本発明を図に示す実施形
態に基づいて詳細に説明する。図１に符号１で示すもの
は本発明に係るＬＥＤ発光素子であり、このＬＥＤ発光
素子１はウエハー基板２のエピタキシャル成長面２ａに
拡散を行いＰＮ接合面３を形成するものであり、そし
て、このＰＮ接合面３に駆動電力を供給するＰ電極４お
よびＮ電極５が設けられているものである点は従来例の
ものと同様である。Next, the present invention will be described in detail based on an embodiment shown in the drawings. 1 is an LED light emitting device according to the present invention. The LED light emitting device 1 diffuses an epitaxial growth surface 2a of a wafer substrate 2 to form a PN junction surface 3. The point that the P electrode 4 and the N electrode 5 for supplying driving power are provided on the PN junction surface 3 is the same as that of the conventional example.
【００１３】ここで、従来例のものがＰＮ接合面３を形
成するに当たりエピタキシャル成長面２ａの全面に形成
していたのに対し、本発明においては、図２に示すよう
に前記エピタキシャル成長面２ａをSiO2、Si3N4 などの
絶縁膜６で覆い、更にホトレジスト膜（図示は省略す
る）を設けてエッチングを行うことで、この絶縁膜６に
エピタキシャル成長面２ａに達する、例えば縦横のマト
リクス状に複数のＰ開口部６ａを設ける。In the conventional example, the PN junction surface 3 was formed on the entire surface of the epitaxial growth surface 2a, whereas in the present invention, the epitaxial growth surface 2a is formed by SiO 2 as shown in FIG. 2 , by covering with an insulating film 6 such as Si 3 N 4 and further by providing a photoresist film (not shown) for etching, the insulating film 6 reaches the epitaxial growth surface 2a. P opening 6a is provided.
【００１４】そして、前記Ｐ開口部６ａを有する絶縁膜
６でエピタキシャル成長面２ａを覆った状態で拡散処理
を行うことで、前記Ｐ開口部６ａが配置されたマトリク
ス状と同じ配置となるＰＮ接合面３を形成するものとし
ている。従って、拡散処理が行われた後のエピタキシャ
ル成長面２ａにはＰＮ接合面３が形成された部分と、形
成されない部分とが存在するものとなる。Then, a diffusion process is performed while the epitaxial growth surface 2a is covered with the insulating film 6 having the P openings 6a, so that the PN junction surface has the same arrangement as the matrix in which the P openings 6a are arranged. 3 is to be formed. Therefore, a portion where the PN junction surface 3 is formed and a portion where the PN junction surface 3 is not formed exist on the epitaxial growth surface 2a after the diffusion process is performed.
【００１５】上記した拡散処理が行われた後には、前記
Ｐ開口部６ａの部分に金、アルミニウムなど導電性部材
の蒸着を行うと、図３に示すように蒸着が行われた導電
性部材は前記Ｐ開口部６ａを通じてＰＮ接合面３に接す
るものとなり、Ｐ電極４が形成されるものとなる。After the above diffusion process is performed, when a conductive member such as gold or aluminum is deposited on the P opening 6a, the conductive member deposited as shown in FIG. It comes into contact with the PN junction surface 3 through the P opening 6a, and the P electrode 4 is formed.
【００１６】しかる後に、図４に示すように前記Ｐ電極
４を含む絶縁膜６の全面を再びホトレジスト膜（図示は
省略する）で覆い、この絶縁膜６のＰＮ接合面３が形成
されない部分にエピタキシャル成長面２ａに達するＮ開
口部６ｂを設け、このＮ開口部６ｂに上記と同様に導電
性部材の蒸着を行うとＮ電極５が形成されるものとな
る。Thereafter, as shown in FIG. 4, the entire surface of the insulating film 6 including the P electrode 4 is covered again with a photoresist film (not shown), and the PN junction surface 3 of the insulating film 6 is not formed. When an N opening 6b reaching the epitaxial growth surface 2a is provided and a conductive member is deposited on the N opening 6b in the same manner as described above, the N electrode 5 is formed.
【００１７】そして、図５に示すようにＰ電極４とＮ電
極５とが一対となるようにダイシングを行い、続いて、
図６に示すようにダイシングが行われた四面と、Ｐ電極
４とＮ電極５とが形成されているエピタキシャル成長面
２ａとは反対側となる基板面２ｂとに、SiO2或いは透明
樹脂などによる透明絶縁膜７を形成すれば本発明のＬＥ
Ｄ発光素子１（図１参照）が得られるものと成る。尚、
図中に符号８で示すものはダイシングを行った後にもＬ
ＥＤ発光素子１を保持させるための粘着テープである。Then, dicing is performed so that the P electrode 4 and the N electrode 5 are paired as shown in FIG.
As shown in FIG. 6, the four surfaces on which dicing has been performed and the substrate surface 2b opposite to the epitaxial growth surface 2a on which the P electrode 4 and the N electrode 5 are formed have transparent surfaces such as SiO 2 or transparent resin. If the insulating film 7 is formed, the LE of the present invention can be obtained.
D light emitting element 1 (see FIG. 1) is obtained. still,
In the drawing, the reference numeral 8 indicates that even after dicing, L
An adhesive tape for holding the ED light emitting element 1.
【００１８】次いで、上記の構成とした本発明のＬＥＤ
発光素子１の作用および効果について説明する。図７に
示すものは、例えば回路基板１０などに取付けた状態を
示すものであり、本発明によりＰ電極４とＮ電極５とが
共にエピタキシャル成長面２ａに形成されたことで、回
路基板１０に配線パッド１０ａを設けることで金ワイヤ
ーなどを使用することなく一面での取付けを可能とす
る。Next, the LED of the present invention having the above structure
The function and effect of the light emitting element 1 will be described. FIG. 7 shows, for example, a state in which the P electrode 4 and the N electrode 5 are formed on the epitaxial growth surface 2a according to the present invention. Providing the pad 10a enables one-sided mounting without using a gold wire or the like.
【００１９】従って、ＰＮ接合面３から放射される光は
エピタキシャル成長面２ａを除く５面から透明絶縁膜７
を透過して外部に放出されるものとなり、しかもこのと
きには、従来例のものの如くに主方向にＰ電極４、金ワ
イヤーなど影を生じるものが存在しないので、光量の損
失を生じないものとすることが可能である。Therefore, the light radiated from the PN junction surface 3 is transmitted from the five surfaces excluding the epitaxial growth surface 2a to the transparent insulating film 7
Is transmitted to the outside, and at this time, since there is no such thing as a P-electrode 4, a gold wire or the like in the main direction which causes a shadow as in the conventional example, no loss of light quantity occurs. It is possible.
【００２０】また、本発明のＬＥＤ発光素子１において
は、ＰＮ接合面３が選択的に形成されたことで、ダイシ
ングにより個別に分離が行われる時点でＰＮ接合面３を
切断し、切断面にＰＮ接合面３が露出することがなく、
最初に形成された絶縁膜６と、Ｐ電極４とで外気から遮
断されたものとなる。Further, in the LED light emitting device 1 of the present invention, since the PN junction surface 3 is selectively formed, the PN junction surface 3 is cut at the time when separation is individually performed by dicing, and the cut surface is formed. Without exposing the PN junction surface 3,
The insulating film 6 formed first and the P electrode 4 are cut off from the outside air.
【００２１】従って、従来例のものの如くに必ず樹脂ケ
ースを設ける必要はなく、よって、セラミック基板など
を設けることなく図７にも示すようにＬＥＤ発光素子１
の状態のままで面実装型のＬＥＤランプとしての使用が
可能であり、小型化が可能となると共に、生産工程も簡
素化する。Therefore, unlike the conventional example, it is not necessary to provide a resin case, and therefore, without providing a ceramic substrate or the like, as shown in FIG.
In this state, it can be used as a surface-mount type LED lamp, miniaturization is possible, and the production process is simplified.
【００２２】図８に示すものは本発明の別の実施形態で
あり、本発明では前記エピタキシャル成長面２ａを絶縁
膜６で覆い、更にホトレジスト膜（図示は省略する）を
設けてエッチングを行うことで、この絶縁膜６にエピタ
キシャル成長面２ａに達するＰ開口部６ａを設け、そし
て、Ｐ開口部６ａを通じて拡散処理を行うものであるの
で、前記Ｐ開口部６ａの形状は露光マスクなどにより自
在として設定できるものとなる。FIG. 8 shows another embodiment of the present invention. In the present invention, the epitaxial growth surface 2a is covered with an insulating film 6, and a photoresist film (not shown) is further provided for etching. Since the insulating film 6 is provided with a P opening 6a reaching the epitaxial growth surface 2a and performing diffusion processing through the P opening 6a, the shape of the P opening 6a can be freely set by an exposure mask or the like. It will be.
【００２３】よって、この実施形態ではＰ開口部６ａを
円形として形成し、このＰ開口部６ａを通じて拡散処理
を行うことでＰＮ接合面３を円形のものとし、発光した
ときには円形の発光形状が得られるものとしている。従
って、本発明によれば発光形状も自在に設定可能と成る
のである。尚、上記以外の作用、効果は前の実施形態と
同様であるので、ここでの詳細な説明は省略する。Therefore, in this embodiment, the P opening 6a is formed in a circular shape, and the PN junction surface 3 is made circular by performing diffusion processing through the P opening 6a. It should be. Therefore, according to the present invention, the light emission shape can be freely set. Since the operation and effects other than those described above are the same as those of the previous embodiment, the detailed description is omitted here.
【００２４】[0024]
【発明の効果】以上に説明したように本発明により、Ｐ
Ｎ接合面はエピタキシャル成長面上に設けた絶縁層に開
口部を設けて拡散を行うことでエピタキシャル成長面に
選択的に形成し、このＰＮ接合面上にＰ電極を設けると
共に、エピタキシャル成長面のＰＮ接合面が形成されて
いない部分にＮ電極が設けられているＬＥＤ発光素子と
したことで、Ｐ電極とＮ電極とが共にエピタキシャル成
長面に形成され、金ワイヤーなどを使用することなく一
面での取付けを可能とする。As described above, according to the present invention, P
The N junction surface is selectively formed on the epitaxial growth surface by providing an opening in an insulating layer provided on the epitaxial growth surface and performing diffusion. A P electrode is provided on this PN junction surface, and the PN junction surface of the epitaxial growth surface is formed. The LED light-emitting element has an N-electrode in the area where no is formed, so both the P-electrode and the N-electrode are formed on the epitaxial growth surface, and can be mounted on one surface without using gold wires etc. And
【００２５】従って、ＰＮ接合面から放射される光はエ
ピタキシャル成長面を除く５面から透明絶縁膜を透過し
て外部に放出されるものとなり、しかもこのときには、
従来例のものの如くに主方向にＰ電極、金ワイヤーなど
影を生じるものが存在しないので、光量の損失を生じな
いものとして格段の光量増加が可能とし、ＬＥＤ発光素
子の性能向上に極めて優れた効果を奏するものである。Therefore, the light radiated from the PN junction surface is transmitted through the transparent insulating film from the five surfaces excluding the epitaxial growth surface and is emitted to the outside.
As there is no P electrode, a gold wire, or the like that produces a shadow in the main direction as in the conventional example, the light amount can be increased remarkably without causing a loss of the light amount, and the performance of the LED light emitting element is extremely improved. It is effective.
【００２６】また、Ｐ電極とＮ電極とが共にエピタキシ
ャル成長面に形成されたことと、ＰＮ接合面が選択的に
形成されてダイシングにより分離が行われる時点でＰＮ
接合面を切断して切断面にＰＮ接合面が露出することが
なくなり耐湿性が向上することで、ＬＥＤ発光素子の状
態のままで、チップマウントを可能とし従来は必要であ
ったセラミック基板、樹脂ケースを不要とし、部品と工
数とを共に低減してコストダウンにも優れた効果を奏す
るものである。Also, when the P electrode and the N electrode are both formed on the epitaxial growth surface, and when the PN junction surface is selectively formed and the separation is performed by dicing, the PN junction is formed.
By cutting the bonding surface, the PN bonding surface is not exposed on the cut surface and the moisture resistance is improved, so that chip mounting can be performed in the state of the LED light emitting element and ceramic substrates and resins conventionally required This eliminates the need for a case, reduces both parts and man-hours, and has an excellent effect on cost reduction.
【図１】 本発明に係るＬＥＤ発光素子の実施形態を示
す断面図である。FIG. 1 is a sectional view showing an embodiment of an LED light emitting device according to the present invention.
【図２】 同じ実施形態における拡散工程を示す説明図
である。FIG. 2 is an explanatory diagram showing a diffusion step in the same embodiment.
【図３】 同じ実施形態におけるＰ電極の形成工程を示
す説明図である。FIG. 3 is an explanatory view showing a step of forming a P electrode in the same embodiment.
【図４】 同じ実施形態におけるＮ電極の形成工程を示
す説明図である。FIG. 4 is an explanatory view showing a process of forming an N electrode in the same embodiment.
【図５】 同じ実施形態におけるダイシング工程を示す
説明図である。FIG. 5 is an explanatory diagram showing a dicing step in the same embodiment.
【図６】 同じ実施形態における透明絶縁膜形成工程を
示す説明図である。FIG. 6 is an explanatory diagram showing a transparent insulating film forming step in the same embodiment.
【図７】 本発明に係るＬＥＤ発光素子のプリント基板
への取付状態を示す説明図である。FIG. 7 is an explanatory diagram showing a state in which the LED light emitting device according to the present invention is mounted on a printed circuit board.
【図８】 同じく本発明に係るＬＥＤ発光素子の別の実
施形態を示す正面図である。FIG. 8 is a front view showing another embodiment of the LED light emitting device according to the present invention.
【図９】 従来例のＬＥＤ発光素子を示す断面図であ
る。FIG. 9 is a cross-sectional view showing a conventional LED light emitting device.
【図１０】 別の従来例のＬＥＤ発光素子を示す断面図
である。FIG. 10 is a cross-sectional view showing another conventional LED light emitting element.
【図１１】 従来例のＬＥＤ発光素子で形成したチップ
マウント型ＬＥＤランプを示す断面図である。FIG. 11 is a cross-sectional view showing a chip-mounted LED lamp formed with a conventional LED light-emitting element.
【図１２】 別の従来例のＬＥＤ発光素子で形成したチ
ップマウント型ＬＥＤランプを示す断面図である。FIG. 12 is a cross-sectional view showing a chip-mounted LED lamp formed by another conventional LED light emitting element.
１……ＬＥＤ発光素子 ２……ウエハー基板 ２ａ……エピタキシャル成長面 ３……ＰＮ接合面 ４……Ｐ電極 ５……Ｎ電極 ６……絶縁膜 ６ａ……Ｐ開口部 ６ｂ……Ｎ開口部 ７……透明絶縁膜 ８……粘着テープ DESCRIPTION OF SYMBOLS 1 ... LED light emitting element 2 ... Wafer substrate 2a ... Epitaxial growth surface 3 ... PN junction surface 4 ... P electrode 5 ... N electrode 6 ... Insulating film 6a ... P opening 6b ... N opening 7 …… Transparent insulating film 8 …… Adhesive tape
Claims (2)
いＰＮ接合面を形成し、該ＰＮ接合面に対して駆動電力
を供給するためのＰ電極およびＮ電極が設けられて成る
ＬＥＤ発光素子において、前記ＰＮ接合面は前記エピタ
キシャル成長面上に設けた絶縁層に開口部を設けて拡散
を行うことで前記エピタキシャル成長面に選択的に形成
し、このＰＮ接合面上にＰ電極を設けると共に、前記エ
ピタキシャル成長面のＰＮ接合面が形成されていない部
分にＮ電極が設けられていることを特徴とするＬＥＤ発
光素子。1. An LED light emitting device comprising: a diffusion layer formed on an epitaxial growth surface of a substrate to form a PN junction surface; and a P electrode and an N electrode for supplying drive power to the PN junction surface. The PN junction surface is selectively formed on the epitaxial growth surface by providing an opening in the insulating layer provided on the epitaxial growth surface and performing diffusion. A P electrode is provided on the PN junction surface, and the PN junction surface is formed on the epitaxial growth surface. An LED light emitting device, wherein an N electrode is provided in a portion where a PN junction surface is not formed.
Ｎ電極が設けられた場所以外の全面が透明絶縁膜で覆わ
れていることを特徴とする請求項１記載のＬＥＤ発光素
子。2. The LED light emitting device according to claim 1, wherein the entire surface of the LED light emitting device other than the place where the P electrode and the N electrode are provided is covered with a transparent insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34177296A JPH10190051A (en) | 1996-12-20 | 1996-12-20 | Led light emitting element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP34177296A JPH10190051A (en) | 1996-12-20 | 1996-12-20 | Led light emitting element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10190051A true JPH10190051A (en) | 1998-07-21 |
Family
ID=18348652
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP34177296A Pending JPH10190051A (en) | 1996-12-20 | 1996-12-20 | Led light emitting element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10190051A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005191138A (en) * | 2003-12-24 | 2005-07-14 | Kyocera Corp | Light-emitting device |
| KR100579644B1 (en) * | 2003-01-29 | 2006-05-16 | 연세대학교 산학협력단 | Photo detection diode and manufacturing method thereof |
| JP6861900B1 (en) * | 2019-09-27 | 2021-04-21 | 三菱電機株式会社 | Manufacturing method of optical semiconductor device |
-
1996
- 1996-12-20 JP JP34177296A patent/JPH10190051A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100579644B1 (en) * | 2003-01-29 | 2006-05-16 | 연세대학교 산학협력단 | Photo detection diode and manufacturing method thereof |
| JP2005191138A (en) * | 2003-12-24 | 2005-07-14 | Kyocera Corp | Light-emitting device |
| JP6861900B1 (en) * | 2019-09-27 | 2021-04-21 | 三菱電機株式会社 | Manufacturing method of optical semiconductor device |
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