JPH10189993A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the difference between crystallization energy and activation energy by providing a polysilicon layer which is formed thinner at the part directly above a gate electrode than at other parts, and a pair of impurity diffusion layers formed in the polysilicon at the opposite sides of gate electrode. SOLUTION: An amorphous silicon 5 is about 50nm thick at the part of a light-doped N-type diffusion layer 10 and a heavily-doped N-type diffusion layer 12, but the thickness of the amorphous silicon 5 is decreased to 30-40nm at the part of undoped channel region. Consequently, the difference between the crystallization energy and the energy required for activation is reduced. According to the arrangement, crystallization of the amorphous silicon 5 at the part of channel region and activation of impurities at the part of the source- drain region, i.e., the lightly-doped N-type diffusion layer 10 and a heavily-doped N-type diffusion layer 12, can be carried out favorably through single irradiation of pulse laser 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device such as a bottom gate type polycrystalline silicon thin film transistor (TFT) and a method of manufacturing the same.

[0002]

2. Description of the Related Art For a high resolution display, a polycrystalline silicon thin film transistor (TF) is used as a switching element.
A small, high-definition active matrix liquid crystal display (LCD) panel using T) has been developed. When a polycrystalline silicon TFT is used for the active element of the LCD, the pixel array section and the drive array section can be manufactured on the same transparent insulating substrate by the same process, and thus there is an advantage that steps such as wire bonding and mounting of a drive IC can be reduced. Yes.

On the other hand, in order to realize a large-sized and high-definition LCD panel using a polycrystalline silicon TFT, a low-temperature technology has attracted attention. This low-temperature technology reduces the process temperature to 600 ° C or lower. In this temperature range, a cheap and large-area hard glass substrate can be used, so a large LCD with an integrated drive circuit and a smaller, lower-cost, smaller one can be used. LCD
Can be realized.

However, it is not technically easy to produce a high-performance polycrystalline silicon TFT in this temperature range, and various techniques have been tried in the past. For example, an amorphous silicon thin film formed by a chemical vapor deposition (CVD) method or a polycrystalline silicon thin film formed by a CVD method, which is made amorphous by ion-implanting silicon, is subjected to a laser such as a pulse laser. The laser annealing method in which crystallization is performed by irradiating energy is intended to promote the growth of the crystal grain size (grain) to increase the crystallinity, thereby improving the mobility of the TFT.

[0005]

In particular, in the case of a polycrystalline silicon TFT manufactured by a low-temperature technology, an impurity is introduced into a source / drain region in an amorphous silicon film state, and the impurity is activated. It is convenient to simultaneously perform the crystallization treatment of the amorphous silicon film and one laser annealing. As a result, the number of laser energy irradiations can be reduced, and the process can be simplified.Also, the maintenance cycle of a device that requires periodic gas filling such as an excimer laser can be extended. Thus, productivity is improved.

However, particularly in the case of a bottom gate type polycrystalline silicon TFT, a gate electrode made of a metal film having high thermal conductivity exists under the channel region.
There has been a problem that the difference between the laser energy required for crystallization of amorphous silicon and the laser energy required for activating the impurities is considerably large.

For example, in the case of a top gate type in which an amorphous silicon film is formed directly on a glass substrate, the laser energy required for activating impurities is, for example, 280 m
The laser energy required for crystallization of amorphous silicon is about 320 mJ / cm ² , while it is about J / cm ² . However, in the case of the bottom gate type, some of the thermal energy required for crystallization of amorphous silicon escapes from the gate electrode having a high thermal conductivity existing under the channel region, so that the crystallization of amorphous silicon is performed. 380mJ / cm
^{About 2} laser energies are required.

Therefore, particularly in a bottom gate type polycrystalline silicon TFT, it is very difficult to set the irradiation laser energy when crystallization of amorphous silicon and activation of impurities are attempted at the same time. For example, when the irradiation laser energy is set to a relatively low value required for activating the impurity, crystallization in the channel region into which the impurity is not introduced becomes insufficient. On the other hand, if the irradiation laser energy is set to a relatively high value required for crystallization of amorphous silicon, excessive energy is supplied to the portion where the impurity is introduced, so that film skipping occurs in that portion. Failure occurs. In other words, the portion into which the impurity is introduced can be ablated on the silicon film at a value lower than the energy for crystallizing the portion into which the impurity has not been introduced. Irradiation with very high energy causes film destruction.

In short, the difference between the laser energy required for crystallization of amorphous silicon and the laser energy required for activating impurities, which was not so problematic in a top gate type polycrystalline silicon TFT, is a bottom gate type polycrystalline silicon TFT. In the case of the polycrystalline silicon TFT of, there has been a serious problem.
This problem is solved by the fact that the crystallization and the activation of the amorphous silicon can be simultaneously performed after the formation of the gate electrode. This makes it difficult to perform simultaneous processing.

Therefore, an object of the present invention is, for example, in a bottom gate type polycrystalline silicon TFT, the crystallization energy of amorphous silicon in the channel region and the source / source energy.
A semiconductor device in which the difference between the energy necessary for activation of impurities in the drain region and the activation of impurities can be easily performed at the same time by one laser annealing and a semiconductor device and its manufacture Is to provide a method.

[0011]

A semiconductor device according to the present invention for solving the above-mentioned problems includes an insulating substrate, a gate electrode formed in a predetermined pattern on the insulating substrate, and a gate electrode formed on the gate electrode. A gate insulating film, a polycrystalline silicon film formed on the gate insulating film and having a portion at a position immediately above the gate electrode thinner than other portions;
A pair of impurity diffusion layers formed in the polycrystalline silicon film on both sides of the gate electrode.

Further, a method of manufacturing a semiconductor device according to the present invention
Forming a gate electrode in a predetermined pattern on the insulating substrate; forming a gate insulating film on the entire surface of the insulating substrate including the gate electrode; and forming an amorphous silicon film on the entire surface of the gate insulating film. Forming the amorphous silicon film so that the thickness of the amorphous silicon film in a portion immediately above the gate electrode is smaller than in other portions; and Introducing an impurity into the amorphous silicon film on both sides of the amorphous silicon film, and irradiating the amorphous silicon film with laser energy to crystallize the amorphous silicon film and form the amorphous silicon film. Activating the impurities introduced into the film.

A method of manufacturing a semiconductor device according to another aspect of the present invention includes a step of forming a gate electrode in a predetermined pattern on an insulating substrate, and a gate insulating film over the entire surface of the insulating substrate including the gate electrode. And a step of forming an amorphous silicon film over the entire surface of the gate insulating film, and the film thickness of the amorphous silicon film in a portion immediately above the gate electrode is smaller than that in other portions. So that the amorphous silicon film is processed, and the amorphous silicon film is crystallized into a polycrystalline silicon film by irradiating the amorphous silicon film with a first laser energy. A step of introducing an impurity into the polycrystalline silicon film on both sides of the gate electrode; and irradiating the polycrystalline silicon film with a second laser energy to form an impurity in the polycrystalline silicon film. And a step of activating the introduced the impurity, the.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described according to preferred embodiments.

First, referring to FIGS. 1 to 4, a first embodiment in which the present invention is applied to a bottom gate type N-channel type polycrystalline silicon thin film transistor (TFT) and a method for manufacturing the same will be described in accordance with the method for manufacturing the same. explain.

First, as shown in FIG. 1A, on a transparent insulating substrate 1 such as a glass substrate, a gate electrode 2 made of a metal such as Mo, Ta, or Mo—Ta having a thickness of about 200 nm is formed in a predetermined pattern. Form.

Next, as shown in FIG. 1B, a plasma CV is applied to the entire surface of the transparent insulating substrate 1 including the gate electrode 2.
By a D (chemical vapor deposition) method, a silicon nitride (SiN _x ) film 3 having a thickness of about 50 nm to be a gate insulating film and a silicon oxide (SiO ₂ ) having a thickness of about 100 nm thereon are formed.
The film 4 is formed sequentially.

Next, as shown in FIG. 1C, an amorphous silicon film 5 is formed on the silicon oxide film 4 by the plasma CVD method. At this time, the thickness of the amorphous silicon film 5 is formed to be, for example, about 10 nm or more larger than the thickness required in the channel region. For example, the amorphous silicon film 5 is formed to a thickness of about 50 nm. In addition,
The amorphous silicon film 5 is a polycrystalline silicon film formed by plasma C
After the formation by the VD method, silicon may be ion-implanted into the polycrystalline silicon film to make it amorphous.

Next, as shown in FIG. 2A, a negative type photoresist 6 is applied and formed on the entire surface of the amorphous silicon film 5 and then the gate electrode 2 is formed from the back side of the transparent insulating substrate 1.
The photoresist 6 is exposed and developed by using the mask as a mask, and an opening 7 having a pattern matching the pattern of the gate electrode 2 is formed in the photoresist 6.

Next, as shown in FIG. 2B, the amorphous silicon film 5 is dry-etched through the opening 7 of the photoresist 6, and as shown in the drawing, the amorphous portion of the portion immediately above the gate electrode 2 is amorphous. The film thickness of the silicon film 5 is processed to about 30 to 40 nm.

At this time, in the present embodiment, the photoresist 6 is exposed and patterned from the back side of the transparent insulating substrate 1 using the gate electrode 2 as a mask. The thin portion of the amorphous silicon film 5 which is formed in a self-aligned manner and thus becomes a channel region of the TFT later is also formed in a self-aligned manner with respect to the gate electrode 2. Further, by processing the thickness of the amorphous silicon film 5 by dry etching, the thickness of the amorphous silicon film 5 can be easily reduced, and etching with relatively strong anisotropy is performed. Thus, the thin portion of the amorphous silicon film 5 can be formed with good shape and dimensional control.

Next, as shown in FIG. 2C, the photoresist 6 is removed by ashing.

Next, as shown in FIG. 3A, a positive type photoresist 8 is applied and formed on the entire surface, and then, using the gate electrode 2 as a mask, the photoresist is also applied from the back side of the transparent insulating substrate 1. The photoresist 8 is exposed and developed to leave a photoresist 8 in a pattern that matches the pattern of the gate electrode 2 as shown.

Thereafter, using this photoresist 8 as an ion implantation mask, an N-type impurity 9, for example, phosphorus (P) is self-aligned with the gate electrode 2 in the amorphous silicon film 5 by PH ₃ , for example. Ion implantation is performed at a relatively low concentration, and an N-type low concentration diffusion layer having a concentration of, for example, about 10 ¹⁸ to 10 ¹⁹ / cm ³ is formed in the thick portion of the amorphous silicon film 5 on both sides of the gate electrode 2. Form 10.

Next, as shown in FIG. 3B, after the photoresist 8 is removed by ashing, the photoresist 11 is formed in a relatively wide region including the gate electrode 2 this time. Then, using this photoresist 11 as an ion implantation mask, an N-type impurity 9, for example, phosphorus (P) is ion-implanted into the amorphous silicon film 5 at a relatively high concentration by, for example, PH ₃ , and then, for example, 10 ^{19 ~10 21} / c
An N-type high concentration diffusion layer 12 having a concentration of about m ³ is formed. As a result, the N-type low-concentration diffusion layer 10 is formed inside the N-type high-concentration diffusion layer 12 which mainly constitutes the source / drain of the TFT.
Is formed to provide an LDD (Lightly Doped Drain) structure. The introduction of impurities into the amorphous silicon film 5 may be performed by a diffusion method.

Next, as shown in FIG. 3 (c), after the photoresist 11 is removed by ashing, the entire surface is irradiated with a pulse laser 13 to crystallize the amorphous silicon film 5 and reduce the N-type conductivity. The activation of the impurities respectively introduced into the concentration diffusion layer 10 and the N-type high concentration diffusion layer 12 is simultaneously performed. And
The amorphous silicon film 5 is crystallized to form a polycrystalline silicon film 1.
4.

At this time, in this embodiment, although the thickness of the amorphous silicon film 5 in the portions of the N-type low concentration diffusion layer 10 and the N-type high concentration diffusion layer 12 into which the impurities are introduced is about 50 nm. On the other hand, the film thickness of the amorphous silicon film 5 in the channel region where impurities are not introduced is relatively small, about 30 to 40 nm. That is, by making the film thickness of the amorphous silicon film 5 in the part where impurities are not introduced relatively smaller than the film thickness in the part where impurities are introduced, the crystallization energy in that part is made relatively small. Thus, the difference between the crystallization energy and the energy required for activating the impurities is reduced. As a result, crystallization of the amorphous silicon film 5 in the channel region portion and activation of impurities in the N-type low concentration diffusion layer 10 and the N-type high concentration diffusion layer 12 which are the source / drain regions are performed. One irradiation with the pulse laser 13 can be suitably performed with the same energy.

For this purpose, the thickness of the amorphous silicon film in the other portion is 1.8 to 5 times or more the thickness of the amorphous silicon film in the portion where the impurity is not introduced, that is, It is preferable that the thickness of the amorphous silicon film in the portion where the impurity is not introduced be set to 80 to 20% or less of the thickness of the amorphous silicon film in the other portion. For example, the thickness of the portion of the amorphous silicon film where no impurity is introduced is set to about 10 to 40 nm,
It is preferable to set the thickness of the amorphous silicon film in other portions to 50 nm or more. If the ratio of the thickness of the amorphous silicon film in the portion where the impurity is not introduced to the thickness of the amorphous silicon film in the other portion is smaller than the above range, the crystallization energy of the amorphous silicon and the activity of the impurity are reduced. In some cases, the effect of reducing the difference from the energy required for the formation may not be sufficiently obtained. On the other hand, if the ratio is larger than the above range, the thickness of the channel region becomes too small as compared with the source / drain regions. In addition, there is a possibility that the channel resistance becomes too large. If the thickness of the channel portion is smaller than 10 nm, a leak current may be generated due to a tunnel effect.

Next, after the laser annealing process for crystallization of silicon and activation of impurities shown in FIG. 3C is completed, although not shown, each TFT has its active layer, which is an active layer. The crystalline silicon film 14 is cut into islands,
The individual TFTs are electrically separated.

Thereafter, as shown in FIG. 4A, a silicon oxide (Si) having a thickness of about 100 nm is formed as an interlayer insulating film.
O ₂ ) film 15 and a silicon nitride (SiN _x ) film 1 having a thickness of about 200 nm as a passivation film thereon.
6 are sequentially formed. Thereafter, annealing is performed at about 350 ° C. in a nitrogen atmosphere to reduce defect levels in each film.

Next, as shown in FIG. 4B, an opening 17 reaching the N-type high-concentration diffusion layer 12 is formed in the silicon nitride film 16 and the silicon oxide film 15 by photolithography and dry or wet etching. . Thereafter, an aluminum (Al) film 18 having a thickness of about 500 nm is formed on the entire surface including the inside of the opening 17, and then the Al film 18 is formed by photolithography and dry etching.
Is patterned as shown in FIG.
Al wirings 18 electrically connected to the N-type high-concentration diffusion layers 12 which are the source / drain of the FT are formed.

Through the above steps, the bottom gate type N-channel type polycrystalline silicon TFT is manufactured. Note that N
The N-type impurity introduced into the source / drain regions of the channel-type polycrystalline silicon TFT is not limited to phosphorus (P) in the above example, but arsenic (As) may be used. Also,
In the case of a P-channel type polycrystalline silicon TFT, by using a P-type impurity such as boron (B) as an impurity to be introduced into its source / drain region, substantially the same as the above-mentioned N-channel type polycrystalline silicon TFT is obtained. It can be manufactured in process.

Next, a second embodiment of the present invention will be described with reference to FIGS. In this second embodiment, parts corresponding to those in the above-described first embodiment are designated by the same reference numerals as those in the above-described first embodiment.

In the second embodiment, in the bottom gate type polycrystalline silicon TFT, the crystal of silicon in the channel region and other regions due to the presence of the gate electrode having high thermal conductivity under the channel region. The non-uniformization of the energy for energy reduction is made smaller by making the film thickness of the amorphous silicon film in the channel region smaller than that in other portions.

That is, the bottom gate type polycrystalline silicon TF
In T, the laser energy required for crystallization of silicon differs between the channel region portion where the gate electrode exists below and the other portion where the gate electrode does not exist. For example, the crystallization energy of silicon in a portion where there is no gate electrode below is the same as that of the above-described top gate type, for example, 3
Whereas it is 20 mJ / cm ² or so, the channel region portion is present a gate electrode underneath, as described above, since the thermal energy necessary for crystallization of the silicon from the gate electrode escape part, of silicon 380mJ / for crystallization
About ² cm ² of laser energy is required.

Therefore, in the second embodiment, in order to reduce the difference in the crystallization energies, the thickness of the amorphous silicon film in the channel region is made smaller than that in the other portions. Crystallize by annealing.

That is, in the second embodiment, first,
By performing the same steps as those of FIGS. 1 and 2 of the first embodiment described above, the film thickness of the channel region portion of the amorphous silicon film 5 is made smaller than other portions.

Thereafter, as shown in FIG. 5A, the entire surface of the amorphous silicon film 5 is irradiated with a first pulse laser 19 to crystallize the amorphous silicon film 5 and to form a polycrystalline silicon film. Set to 14. At this time, in the second embodiment,
Since the film thickness of the channel region portion of the amorphous silicon film 5 is made smaller than that of the other portion and the crystallization energy in that portion is made relatively small, the channel region portion where the gate electrode exists below is formed. And the difference in crystallization energy of silicon between the gate electrode and the other portion where the gate electrode is not formed becomes small, and crystallization is performed almost uniformly over the entire amorphous silicon film 5. As a result, a good quality polycrystalline silicon film 14 having a large crystal grain size is obtained as a whole, and the characteristics of the TFT are improved.

Next, as shown in FIG. 5B, similar to the case of the first embodiment, a photoresist 8 is applied and formed on the entire surface, and then patterned, as shown in FIG. The photoresist 8 having a pattern matching the pattern of the gate electrode 2 is left. Thereafter, using this photoresist 8 as an ion implantation mask, an N-type impurity 9 is ion-implanted into the polycrystalline silicon film 14 at a relatively low concentration in a self-aligned manner with the gate electrode 2 to form a film on both sides of the gate electrode 2. The N-type low concentration diffusion layer 1 is formed in the thick portion of the amorphous silicon film 5.
0 is formed.

Next, as shown in FIG. 5C, after the photoresist 8 is removed by ashing, a photoresist 11 is formed in a relatively wide area including the gate electrode 2 this time. Then, using the photoresist 11 as an ion implantation mask, the N-type impurity 9 is ion-implanted into the amorphous silicon film 5 at a relatively high concentration to form an N-type high concentration diffusion layer 12.

Next, as shown in FIG. 6A, after the photoresist 11 is removed by ashing, the entire surface is irradiated with a second pulsed laser 20 to remove the N-type low-concentration diffusion layer 10 and the N-type high-concentration diffusion layer. The impurities introduced into the concentration diffusion layer 12 are activated. At this time, in the second embodiment, the second
It is sufficient to irradiate the pulse laser 20 with the energy necessary for activating the impurities. Therefore, the second pulse laser 20 may have lower energy than the first pulse laser 19 for crystallization described above. .

Next, as in the case of the first embodiment described above, the polycrystalline silicon film 14, which is the active layer, is cut into islands for each TFT, and the individual TFTs are electrically connected. To separate.

Thereafter, as shown in FIG. 6B, a silicon oxide (Si
O ₂ ) film 15 and a silicon nitride (SiN _x ) film 1 having a thickness of about 200 nm as a passivation film thereon.
6 are sequentially formed. Thereafter, nitrogen annealing is performed at about 350 ° C. to reduce defect levels in each film.

Next, as shown in FIG. 6C, an opening 17 reaching the N-type high concentration diffusion layer 12 is formed in the silicon nitride film 16 and the silicon oxide film 15 by photolithography and dry etching. After this, opening 1
Aluminum (Al) with a thickness of about 500 nm on the entire surface including the inside of 7
After the film 18 is formed, the Al film 18 is patterned by photolithography and dry etching, and as shown in FIG. An Al wiring 18 is formed to be electrically connected.

Through the above steps, a bottom gate N-channel type polycrystalline silicon TFT is manufactured.

Although the embodiments in which the present invention is applied to the bottom gate type polycrystalline silicon TFT and the method of manufacturing the same have been described, the present invention is not limited to these embodiments. For example, in the above-described embodiment, the insulating substrate on which the TFT is formed is, for example, the transparent insulating substrate 1 for a liquid crystal display (LCD) panel, and the photoresist 6 and the photoresist 8 are respectively replaced by the transparent insulating substrate 1. Exposure was performed from the back side, and these were patterned in a self-aligned manner on the gate electrode 2. However, the present invention can be applied to a bottom gate type polycrystalline silicon TFT other than for LCDs and a method of manufacturing the same. In other words, the insulating substrate does not necessarily need to be transparent. In this case, the photoresist 6 and the photoresist 8 may be patterned from the surface side of the insulating substrate using an appropriate exposure mask.

[0047]

According to the present invention, for example, a polycrystalline silicon film, which is an active layer of a bottom gate type polycrystalline silicon thin film transistor, is formed such that a portion immediately above a gate electrode is thinner than other portions. Make up.

Therefore, for example, after the impurity is introduced into the amorphous silicon film, the difference between the crystallization energy and the activation energy when crystallization of the amorphous silicon film and activation of the impurity are simultaneously performed is reduced. This makes it easy to perform these processes simultaneously, for example, by one laser annealing. As a result, the number of manufacturing steps is reduced, the steps are simplified, and, for example, the maintenance cycle of an excimer laser device used as a pulse laser can be extended, thereby improving productivity.

Further, for example, it is possible to eliminate the non-uniformity of the crystallization energy of the amorphous silicon film in the portion where the gate electrode is present and the portion where the gate electrode is not present, and it is possible to uniformly crystallize the entire surface. A crystalline silicon film can be obtained.
As a result, a bottom gate type polycrystalline silicon thin film transistor having excellent characteristics can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a bottom-gate polycrystalline silicon TFT according to a first embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view illustrating a method of manufacturing a bottom-gate polycrystalline silicon TFT according to the first embodiment of the present invention in the order of steps.

FIG. 3 is a cross-sectional view showing a method of manufacturing a bottom-gate polycrystalline silicon TFT according to the first embodiment of the present invention in the order of steps.

FIG. 4 is a cross-sectional view showing a method of manufacturing the bottom gate type polycrystalline silicon TFT according to the first embodiment of the present invention in the order of steps.

FIG. 5 is a cross-sectional view illustrating a method of manufacturing a bottom-gate polycrystalline silicon TFT according to a second embodiment of the present invention in the order of steps.

FIG. 6 is a cross-sectional view showing a method of manufacturing a bottom-gate polycrystalline silicon TFT according to the second embodiment of the present invention in the order of steps.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 transparent insulating substrate 2 gate electrode 3 silicon nitride film 4 silicon oxide film 5 amorphous silicon film 6
8, 11: photoresist, 9: N-type impurity, 10: N
Type low-concentration diffusion layer, 12 N-type high-concentration diffusion layer, 13 pulse laser, 14 polycrystalline silicon film, 15 silicon oxide film, 16 silicon nitride film, 18 aluminum wiring, 1
9: first pulse laser, 20: second pulse laser

Claims (17)

[Claims] An insulating substrate, a gate electrode formed in a predetermined pattern on the insulating substrate, a gate insulating film formed on the gate electrode, and formed on the gate insulating film; A polycrystalline silicon film in which the portion immediately above the gate electrode is thinner than the other portion, and a pair of impurity diffusion layers formed in the polycrystalline silicon film on both sides of the gate electrode. Semiconductor device. 2. The thickness of the polycrystalline silicon film in a portion immediately above the gate electrode is 1.8 to 5 times or more the thickness of the polycrystalline silicon film in another portion. 1
3. The semiconductor device according to claim 1. 3. The film thickness of the polycrystalline silicon film in a portion immediately above the gate electrode is 10 to 40 nm, and the film thickness of the polycrystalline silicon film in another portion is 50 nm or more. 3. The semiconductor device according to claim 1. 4. The semiconductor device according to claim 1, wherein said insulating substrate is a transparent insulating substrate. 5. A step of forming a gate electrode in a predetermined pattern on an insulating substrate; a step of forming a gate insulating film on the entire surface of the insulating substrate including on the gate electrode; Forming an amorphous silicon film; and processing the amorphous silicon film such that the thickness of the amorphous silicon film in a portion immediately above the gate electrode is smaller than in other portions. Introducing an impurity into the amorphous silicon film on both sides of the gate electrode; irradiating the amorphous silicon film with laser energy to crystallize the amorphous silicon film; Activating the impurity introduced into the amorphous silicon film. A method for manufacturing a semiconductor device, comprising: 6. The processing is performed so that the film thickness of the amorphous silicon film at a position directly above the gate electrode is 80 to 20% or less of the film thickness of the amorphous silicon film at another part. A method for manufacturing a semiconductor device according to claim 5. 7. After forming the amorphous silicon film to a thickness of 50 nm or more, the film thickness of the amorphous silicon film at a position immediately above the gate electrode is processed to 10 to 40 nm. 7. The method for manufacturing a semiconductor device according to item 6. 8. The method of manufacturing a semiconductor device according to claim 5, wherein the thickness of said amorphous silicon film in a portion immediately above said gate electrode is processed by dry etching. 9. A transparent insulating substrate is used as the insulating substrate, and after forming the amorphous silicon film on the gate insulating film, a photoresist film is formed on the entire surface of the amorphous silicon film. By exposing the photoresist film from the back surface side of the transparent insulating substrate using the gate electrode as a mask, an opening having a pattern aligned with the gate electrode is formed in the photoresist film. 9. The method of manufacturing a semiconductor device according to claim 8, wherein a thickness of the amorphous silicon film in a portion immediately above the gate electrode is processed through the opening by the dry etching. 10. The method for manufacturing a semiconductor device according to claim 5, wherein a pulsed laser is used as the laser energy. 11. A step of forming a gate electrode in a predetermined pattern on an insulating substrate, a step of forming a gate insulating film on the entire surface of the insulating substrate including on the gate electrode, and a step of forming a gate insulating film on the entire surface of the gate insulating film. Forming an amorphous silicon film; and processing the amorphous silicon film such that the thickness of the amorphous silicon film in a portion immediately above the gate electrode is smaller than in other portions. Irradiating the amorphous silicon film with a first laser energy to crystallize the amorphous silicon film into a polycrystalline silicon film; and forming the polycrystalline silicon film on both sides of the gate electrode. Introducing an impurity into the film; and irradiating the polycrystalline silicon film with a second laser energy to activate the impurity introduced into the polycrystalline silicon film. The method of manufacturing a semiconductor device according to claim Rukoto. 12. The processing is performed so that the film thickness of the amorphous silicon film at a position directly above the gate electrode is 80 to 20% or less of the film thickness of the amorphous silicon film at another part. A method for manufacturing a semiconductor device according to claim 11. 13. After forming the amorphous silicon film to a thickness of 50 nm or more, the thickness of the amorphous silicon film at a position immediately above the gate electrode is processed to 10 to 40 nm. 13. The method for manufacturing a semiconductor device according to item 12. 14. The method of manufacturing a semiconductor device according to claim 11, wherein a thickness of said amorphous silicon film in a portion immediately above said gate electrode is processed by dry etching. 15. A transparent insulating substrate is used as the insulating substrate, and after forming the amorphous silicon film on the gate insulating film, a photoresist film is formed on the entire surface of the amorphous silicon film. By exposing the photoresist film from the back side of the transparent insulating substrate using the gate electrode as a mask, an opening having a pattern matching the gate electrode is formed in the photoresist film, and then the photoresist film is exposed to light. 15. The method of manufacturing a semiconductor device according to claim 14, wherein the film thickness of the amorphous silicon film in a portion directly above the gate electrode is processed through the opening by the dry etching. 16. The method according to claim 11, wherein a pulse laser is used as the first and second laser energies. 17. The method of manufacturing a semiconductor device according to claim 11, wherein the irradiation energy of the second laser energy is smaller than the irradiation energy of the first laser energy.