JPH10189927A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH10189927A
JPH10189927A JP8349646A JP34964696A JPH10189927A JP H10189927 A JPH10189927 A JP H10189927A JP 8349646 A JP8349646 A JP 8349646A JP 34964696 A JP34964696 A JP 34964696A JP H10189927 A JPH10189927 A JP H10189927A
Authority
JP
Japan
Prior art keywords
semiconductor
light receiving
silicon
semiconductor device
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8349646A
Other languages
Japanese (ja)
Inventor
Masahiko Suzumura
正彦 鈴村
Hitomichi Takano
仁路 高野
Takashi Kishida
貴司 岸田
Yoshifumi Shirai
良史 白井
Yoshiki Hayazaki
嘉城 早崎
Yuji Suzuki
裕二 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP8349646A priority Critical patent/JPH10189927A/en
Publication of JPH10189927A publication Critical patent/JPH10189927A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which photovoltaic voltage can be increased upon irradiation with light. SOLUTION: This semiconductor device employs an SOI substrate comprising a semiconductor substrate, i.e., a support silicon substrate 1, and an active silicon layer 3 formed thereon through an insulation layer 2, e.g. a silicon oxide, and a plurality of silicon islands 5 comprising the electrically isolated active silicon layer 3 are formed by making grooves 4 reaching the insulation layer 2 from the surface of the active silicon layer 3. Light-receiving elements are formed on respective silicon islands 5 and are connected electrically in series through metal wirings.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置に関す
るものであり、特に、SOI構造型の受光素子に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a light receiving element having an SOI structure.

【0002】[0002]

【従来の技術】図4は、従来例に係るSOI構造型の受
光素子を示す略断面図である。従来例に係るSOI構造
型の受光素子は、支持体シリコン基板1と、支持体シリ
コン基板1上にシリコン酸化膜等の絶縁層2を介して形
成されたp型の活性シリコン層3とで構成されたSOI
(Silicon On Insulator)基板の活性シリコン層3内
に、活性シリコン層3の表面に露出するようにリン
(P)等のn型不純物をイオン注入することによりn+
型不純物領域を形成し、n+型不純物領域を囲み、か
つ、活性シリコン層3の表面に露出するように活性シリ
コン層3内にボロン(B)等のp型不純物をイオン注入
することによりp+型不純物領域を形成する。このn+
型不純物領域はn+型カソード領域8として動作し、p
+型不純物領域はp+型アノード領域9として動作す
る。そして、n+型カソード領域8と電気的に接続され
るようにカソード電極(図示せず)が形成され、p+型
アノード領域9と電気的に接続されるようにアノード電
極(図示せず)が形成されている。
2. Description of the Related Art FIG. 4 is a schematic sectional view showing an SOI structure type light receiving element according to a conventional example. The SOI structure type light receiving element according to the conventional example includes a support silicon substrate 1 and a p-type active silicon layer 3 formed on the support silicon substrate 1 via an insulating layer 2 such as a silicon oxide film. SOI
(Silicon On Insulator) An n-type impurity such as phosphorus (P) is ion-implanted into the active silicon layer 3 of the substrate so as to be exposed on the surface of the active silicon layer 3.
A p-type impurity such as boron (B) is ion-implanted into active silicon layer 3 so as to form a p-type impurity region, surround the n + -type impurity region, and expose the surface of active silicon layer 3. An impurity region is formed. This n +
Type impurity region operates as n + type cathode region 8, and
The + type impurity region operates as the p + type anode region 9. Then, a cathode electrode (not shown) is formed so as to be electrically connected to n + type cathode region 8, and an anode electrode (not shown) is formed so as to be electrically connected to p + type anode region 9. Have been.

【0003】SOI構造型の受光素子は、受光素子とパ
ワー素子や制御回路等の半導体素子との集積化への期待
や、活性シリコン層3の薄膜化による高耐圧化等により
注目されている。
[0003] Light receiving elements of the SOI structure type have attracted attention due to expectations for integration of light receiving elements with semiconductor elements such as power elements and control circuits, and to increase the breakdown voltage by reducing the thickness of the active silicon layer 3.

【0004】シリコン受光素子が光照射時に発生させる
ことができる開放電圧は〜0.6V程度である。このこ
とは、例えば、発光素子と受光素子を光結合し、受光素
子からの光起電力をパワーMOSやIGBT等の絶縁ゲ
ート型パワー素子のゲート電極に印加することでパワー
素子の導通/遮断状態の駆動を行う半導体素子を用い
た、いわゆるソリッドステート型リレーでは、ただ1つ
の受光素子を用いた場合、パワー素子の閾値電圧は少な
くとも0.5V以下で設計する必要がある。
The open-circuit voltage that can be generated by the silicon light receiving element during light irradiation is about 0.6 V. This means, for example, that the light emitting element and the light receiving element are optically coupled, and the photoelectromotive force from the light receiving element is applied to the gate electrode of an insulated gate type power element such as a power MOS or IGBT, so that the power element is turned on / off. In a so-called solid-state relay using a semiconductor element that drives a semiconductor device, when only one light receiving element is used, the threshold voltage of the power element must be designed to be at least 0.5 V or less.

【0005】[0005]

【発明が解決しようとする課題】しかし、低い閾値電圧
のパワー素子の設計は容易でなく、誤動作や歩留まりの
低下等を引き起こすという問題があった。
However, it is not easy to design a power element having a low threshold voltage, and there has been a problem that a malfunction or a decrease in yield is caused.

【0006】また、導通時にパワーMOSFETのゲー
トへの実効的な印加電圧は、ゲート印加電圧値から閾値
電圧値を引いた値であり、この実効的な電圧値はオン抵
抗値と比例関係にあるため、導通時の損失をより低くす
るためには受光素子から印加される電圧はより高い電圧
が必要である。
The effective applied voltage to the gate of the power MOSFET during conduction is a value obtained by subtracting the threshold voltage value from the gate applied voltage value, and the effective voltage value is proportional to the on-resistance value. Therefore, in order to reduce the loss during conduction, a higher voltage is required as the voltage applied from the light receiving element.

【0007】本発明は、上記の点に鑑みて成されたもの
であり、その目的とするところは、光照射時の光起電圧
を大きくすることのできる半導体装置を提供することに
ある。
The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device capable of increasing a photovoltaic voltage at the time of light irradiation.

【0008】[0008]

【課題を解決するための手段】請求項1記載の発明は、
半導体基板と該半導体基板上に絶縁層を介して形成され
た半導体層とで構成されるSOI基板の該半導体層表面
から前記絶縁層に到達するように溝部が形成され、該溝
部及び前記絶縁層により絶縁分離された複数の前記半導
体層から成る半導体島が形成され、該半導体島毎に受光
素子が形成され、該受光素子が電気的に直列接続されて
成ることを特徴とするものである。
According to the first aspect of the present invention,
A groove is formed so as to reach the insulating layer from the surface of the semiconductor layer of the SOI substrate including the semiconductor substrate and the semiconductor layer formed on the semiconductor substrate via the insulating layer, and the groove and the insulating layer are formed. A semiconductor island composed of a plurality of the semiconductor layers which are insulated and separated from each other, a light receiving element is formed for each of the semiconductor islands, and the light receiving elements are electrically connected in series.

【0009】請求項2記載の発明は、請求項1記載の半
導体装置において、該半導体島が、絶縁層と半導体層と
の多層構造であり、深さ方向に対して複数の前記半導体
島を有して成ることを特徴とするものである。
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the semiconductor island has a multilayer structure of an insulating layer and a semiconductor layer, and has a plurality of the semiconductor islands in a depth direction. It is characterized by comprising.

【0010】請求項3記載の発明は、請求項1または請
求項2記載の半導体装置において、前記受光素子が、金
属配線により電気的に直列接続されて成ることを特徴と
するものである。
According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the light receiving elements are electrically connected in series by metal wiring.

【0011】請求項4記載の発明は、請求項1または請
求項2記載の半導体装置において、前記受光素子を、実
装基板に形成された金属配線上に配置することにより電
気的に直列接続するようにしたことを特徴とするもので
ある。
According to a fourth aspect of the present invention, in the semiconductor device according to the first or second aspect, the light receiving elements are electrically connected in series by being arranged on a metal wiring formed on a mounting substrate. It is characterized by having made it.

【0012】[0012]

【発明の実施の形態】以下、本発明の一実施形態につい
て図面に基づき説明する。なお、本実施形態において
は、説明の便宜上、第一導電型をp型,第二導電型をn
型として説明するが、p型とn型が逆の場合にも適用さ
れる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. In this embodiment, the first conductivity type is p-type and the second conductivity type is n for convenience of explanation.
Although described as a type, the present invention is also applied to a case where p-type and n-type are reversed.

【0013】図1は、本発明の一実施形態に係るSOI
構造型の受光素子を示す略断面図である。本実施形態に
係る半導体装置は、半導体基板としての支持体シリコン
基板1と、支持体シリコン基板1上にシリコン酸化膜等
の絶縁層2を介して形成された活性シリコン層3とで構
成されるSOI基板を用い、活性シリコン層3の表面か
ら絶縁層2に到達する溝部4が形成されることにより、
互いに電気的に絶縁された活性シリコン層3から成る複
数のシリコン島5が形成されている。
FIG. 1 shows an SOI according to an embodiment of the present invention.
It is a schematic sectional drawing which shows a structural type light receiving element. The semiconductor device according to the present embodiment includes a support silicon substrate 1 as a semiconductor substrate and an active silicon layer 3 formed on the support silicon substrate 1 via an insulating layer 2 such as a silicon oxide film. By using a SOI substrate, a groove 4 reaching the insulating layer 2 from the surface of the active silicon layer 3 is formed.
A plurality of silicon islands 5 composed of active silicon layers 3 electrically insulated from each other are formed.

【0014】なお、溝部4の形成方法の一例としては、
所定形状にパターニングされたシリコン酸化膜をマスク
としてKOH水溶液等のアルカリ系のエッチャントを用
いて異方性エッチングを行うことにより形成する方法が
ある。
As an example of a method for forming the groove portion 4,
There is a method in which anisotropic etching is performed using an alkaline etchant such as a KOH aqueous solution using a silicon oxide film patterned into a predetermined shape as a mask.

【0015】そして、各シリコン島5に受光素子(図示
せず)を形成し、各受光素子を金属配線で電気的に直列
接続する。
A light receiving element (not shown) is formed on each silicon island 5, and each light receiving element is electrically connected in series by a metal wiring.

【0016】従って、単一では約0.6V程度の開放電
圧の発生しか期待できないシリコン受光素子を、本実施
形態においては、SOI基板の活性シリコン層3を複数
個に絶縁分離し、絶縁分離された各シリコン島5に受光
素子を形成して、各受光素子を電気的に直列接続するよ
うにしたので、数V以上の開放電圧を容易に達成するこ
とができる。
Accordingly, in the present embodiment, a single silicon photodetector which can only be expected to generate an open voltage of about 0.6 V is insulated and separated into a plurality of active silicon layers 3 of the SOI substrate. Since the light receiving elements are formed on each of the silicon islands 5 and the light receiving elements are electrically connected in series, an open circuit voltage of several volts or more can be easily achieved.

【0017】なお、図2に示すように、図1に示す溝部
4により複数個に絶縁分離された各シリコン島5を、さ
らに深さ方向において絶縁層2aを介在させることによ
り更に複数個の絶縁分離されたシリコン島5を形成し、
各シリコン島5に受光素子を形成して、各受光素子を金
属配線により直列接続するようにすれば、さらに高い値
の開放電圧を達成することができる。
As shown in FIG. 2, each of the silicon islands 5 insulated and separated by the groove 4 shown in FIG. 1 is further separated into a plurality of insulating islands 2 by interposing an insulating layer 2a in the depth direction. Forming isolated silicon islands 5,
If a light receiving element is formed on each silicon island 5 and each light receiving element is connected in series by a metal wiring, a higher value open circuit voltage can be achieved.

【0018】また、本実施形態においては、金属配線に
より各受光素子を電気的に直列接続するようにしたが、
これに限定される必要はなく、例えば、図3に示すよう
に、予め金属配線7が形成された実装基板6上に、図1
または図2に示すSOI基板に形成された受光素子を配
置することにより各受光素子を直列接続するようにして
も良い。
In this embodiment, the respective light receiving elements are electrically connected in series by metal wiring.
The present invention is not limited to this. For example, as shown in FIG.
Alternatively, the light receiving elements formed on the SOI substrate shown in FIG. 2 may be arranged to connect the respective light receiving elements in series.

【0019】[0019]

【発明の効果】請求項1記載の発明は、半導体基板と半
導体基板上に絶縁層を介して形成された半導体層とで構
成されるSOI基板の半導体層表面から絶縁層に到達す
るように溝部が形成され、溝部及び絶縁層により絶縁分
離された複数の半導体層から成る半導体島が形成され、
半導体島毎に受光素子が形成され、受光素子が電気的に
直列接続されて成るので、数V以上の開放電圧を容易に
達成することができ、光照射時の光起電圧を大きくする
ことのできる半導体装置を提供することができた。
According to the first aspect of the present invention, a groove is formed so as to reach an insulating layer from a semiconductor layer surface of an SOI substrate including a semiconductor substrate and a semiconductor layer formed on the semiconductor substrate via an insulating layer. Is formed, a semiconductor island composed of a plurality of semiconductor layers insulated and separated by the trench and the insulating layer is formed,
Since a light receiving element is formed for each semiconductor island and the light receiving elements are electrically connected in series, an open circuit voltage of several volts or more can be easily achieved, and the photovoltaic voltage at the time of light irradiation can be increased. A semiconductor device that can be provided.

【0020】請求項2記載の発明は、請求項1記載の半
導体装置において、半導体島が、絶縁層と半導体層との
多層構造であり、深さ方向に対して複数の半導体島を有
して成るので、さらに多くの受光素子を形成することが
でき、さらに高い値の開放電圧を達成することができ
る。
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the semiconductor island has a multilayer structure of an insulating layer and a semiconductor layer, and has a plurality of semiconductor islands in a depth direction. Therefore, more light receiving elements can be formed, and a higher value open circuit voltage can be achieved.

【0021】請求項3記載の発明は、請求項1または請
求項2記載の半導体装置において、受光素子が、金属配
線により電気的に直列接続されて成るので、半導体素子
の配線を行う際に同時に配線を行うことができ、工程数
が増えることなく高い開放電圧を達成することができ
る。
According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the light receiving elements are electrically connected in series by metal wiring, so that the wiring of the semiconductor elements can be performed simultaneously. Wiring can be performed, and a high open-circuit voltage can be achieved without increasing the number of steps.

【0022】請求項4記載の発明は、請求項1または請
求項2記載の半導体装置において、受光素子を、実装基
板に形成された金属配線上に配置することにより電気的
に直列接続するようにしたので、実装基板に実装すると
同時に受光素子を電気的に直列接続することができ、高
い開放電圧を容易に達成することができる。
According to a fourth aspect of the present invention, in the semiconductor device according to the first or second aspect, the light receiving element is electrically connected in series by disposing the light receiving element on a metal wiring formed on the mounting substrate. Therefore, the light receiving elements can be electrically connected in series while being mounted on the mounting board, and a high open-circuit voltage can be easily achieved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態に係るSOI構造型の受光
素子を示す略断面図である。
FIG. 1 is a schematic cross-sectional view showing an SOI structure type light receiving element according to an embodiment of the present invention.

【図2】本発明の他の実施形態に係るSOI構造型の受
光素子を示す略断面図である。
FIG. 2 is a schematic cross-sectional view showing an SOI structure type light receiving element according to another embodiment of the present invention.

【図3】本発明の他の実施形態に係るSOI構造型の受
光素子を示す略断面図である。
FIG. 3 is a schematic sectional view showing an SOI structure type light receiving element according to another embodiment of the present invention.

【図4】従来例に係るSOI構造型の受光素子を示す略
断面図である。
FIG. 4 is a schematic sectional view showing a SOI structure type light receiving element according to a conventional example.

【符号の説明】[Explanation of symbols]

1 支持体シリコン基板 2,2a 絶縁層 3 活性シリコン層 4 溝部 5 シリコン島 6 実装基板 7 金属配線 8 n+型カソード領域 9 p+型アノード領域 DESCRIPTION OF SYMBOLS 1 Supporting silicon substrate 2, 2a Insulating layer 3 Active silicon layer 4 Groove part 5 Silicon island 6 Mounting substrate 7 Metal wiring 8 n + type cathode region 9 p + type anode region

─────────────────────────────────────────────────────
────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成9年7月2日[Submission date] July 2, 1997

【手続補正1】[Procedure amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】0004[Correction target item name] 0004

【補正方法】変更[Correction method] Change

【補正内容】[Correction contents]

【0004】シリコン受光素子が光照射時に発生させる
ことができる開放電圧は〜0.6V程度である。このこ
とは、例えば、発光素子と受光素子を光結合し、受光素
子からの光起電力をパワーMOSやIGBT等の絶縁ゲ
ート型パワー素子のゲート電極に印加することでパワー
素子の導通/遮断状態の駆動を行う半導体素子を用い
た、いわゆる半導体型リレーでは、ただ1つの受光素子
を用いた場合、パワー素子の閾値電圧は少なくとも0.
5V以下で設計する必要がある。
The open-circuit voltage that can be generated by the silicon light receiving element during light irradiation is about 0.6 V. This means, for example, that the light emitting element and the light receiving element are optically coupled, and the photoelectromotive force from the light receiving element is applied to the gate electrode of an insulated gate type power element such as a power MOS or IGBT, so that the power element is turned on / off. In the case of a so-called semiconductor type relay using a semiconductor element for driving a semiconductor device, when only one light receiving element is used, the threshold voltage of the power element is at least 0.
It is necessary to design at 5V or less.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 白井 良史 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 早崎 嘉城 大阪府門真市大字門真1048番地松下電工株 式会社内 (72)発明者 鈴木 裕二 大阪府門真市大字門真1048番地松下電工株 式会社内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoshifumi Shirai 1048 Kadoma Kadoma, Kadoma City, Osaka Prefecture Inside Matsushita Electric Works, Ltd. (72) Inventor Yuji Suzuki 1048 Kazuma Kadoma, Kadoma City, Osaka Inside Matsushita Electric Works, Ltd.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板と該半導体基板上に絶縁層を
介して形成された半導体層とで構成されるSOI基板の
該半導体層表面から前記絶縁層に到達するように溝部が
形成され、該溝部及び前記絶縁層により絶縁分離された
複数の前記半導体層から成る半導体島が形成され、該半
導体島毎に受光素子が形成され、該受光素子が電気的に
直列接続されて成ることを特徴とする半導体装置。
An SOI substrate including a semiconductor substrate and a semiconductor layer formed on the semiconductor substrate via an insulating layer, wherein a groove is formed from the surface of the semiconductor layer to reach the insulating layer; A semiconductor island comprising a plurality of the semiconductor layers insulated and separated by the groove and the insulating layer is formed, a light receiving element is formed for each semiconductor island, and the light receiving elements are electrically connected in series. Semiconductor device.
【請求項2】 該半導体島が、絶縁層と半導体層との多
層構造であり、深さ方向に対して複数の前記半導体島を
有して成ることを特徴とする請求項1記載の半導体装
置。
2. The semiconductor device according to claim 1, wherein said semiconductor island has a multilayer structure of an insulating layer and a semiconductor layer, and has a plurality of said semiconductor islands in a depth direction. .
【請求項3】 前記受光素子が、金属配線により電気的
に直列接続されて成ることを特徴とする請求項1または
請求項2記載の半導体装置。
3. The semiconductor device according to claim 1, wherein said light receiving elements are electrically connected in series by metal wiring.
【請求項4】 前記受光素子を、実装基板に形成された
金属配線上に配置することにより電気的に直列接続する
ようにしたことを特徴とする請求項1または請求項2記
載の半導体装置。
4. The semiconductor device according to claim 1, wherein said light receiving elements are electrically connected in series by being arranged on a metal wiring formed on a mounting substrate.
JP8349646A 1996-12-27 1996-12-27 Semiconductor device Pending JPH10189927A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8349646A JPH10189927A (en) 1996-12-27 1996-12-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8349646A JPH10189927A (en) 1996-12-27 1996-12-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH10189927A true JPH10189927A (en) 1998-07-21

Family

ID=18405150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8349646A Pending JPH10189927A (en) 1996-12-27 1996-12-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH10189927A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9306106B2 (en) 2012-12-18 2016-04-05 International Business Machines Corporation Monolithic integration of heterojunction solar cells

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9306106B2 (en) 2012-12-18 2016-04-05 International Business Machines Corporation Monolithic integration of heterojunction solar cells
US9397246B2 (en) 2012-12-18 2016-07-19 International Business Machines Corporation Monolithic integration of heterojunction solar cells
US9472703B2 (en) 2012-12-18 2016-10-18 International Business Machines Corporation Monolithic integration of heterojunction solar cells
US9935223B2 (en) 2012-12-18 2018-04-03 International Business Machines Corporation Monolithic integration of heterojunction solar cells
US10256357B2 (en) 2012-12-18 2019-04-09 International Business Machines Corporation Monolithic integration of heterojunction solar cells
US10541343B2 (en) 2012-12-18 2020-01-21 International Business Machines Corporation Monolithic integration of heterojunction solar cells

Similar Documents

Publication Publication Date Title
JP5052091B2 (en) Semiconductor device
KR970008646A (en) Semiconductor device and manufacturing method thereof
JP3085037B2 (en) Insulated gate bipolar transistor
JP3369391B2 (en) Dielectric separated type semiconductor device
KR890007433A (en) Semiconductor device having bipolar transistor and manufacturing method thereof
JP2001085731A (en) Photoelectric voltage generator
JP2007287732A (en) Thin-film transistor, manufacturing method thereof, and display
JP3694918B2 (en) Semiconductor device
JPH10189927A (en) Semiconductor device
JPH10270674A (en) Semiconductor device and manufacture thereof
JP3217552B2 (en) Horizontal high voltage semiconductor device
JP2002094046A (en) Semiconductor device
KR100192966B1 (en) Mos control diode and manufacturing method thereof
JPH10163514A (en) Semiconductor device
JPH10163314A (en) Semiconductor device and its manufacture
JPH10256542A (en) Semiconductor device
JPH11121768A (en) Semiconductor integrated circuit
US20060154430A1 (en) Soi structure comprising substrate contacts on both sides of the box, and method for the production of such a structure
JPS61174672A (en) Vmos transistor
JPH0729974A (en) Semiconductor device
JP3608410B2 (en) Photovoltaic device
JPH10223925A (en) Semiconductor device
JPH09246371A (en) Semiconductor device and manufacture thereof
KR19990066466A (en) Power device with built-in diode and manufacturing method thereof
KR0145119B1 (en) Darlington connected semiconductor device and manufacturing method thereof