JPH10189764A - Vertical soi device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a practical MOS transistor of 0.1 micron or finer. SOLUTION: A high performance MOS transistor having a submicron gate length is fabricated without relying upon electron beam lithography by forming a channel vertically to an SOI silicon substrate 1. A CMOS transistor can also be fabricated easily. Since a body contact 11 can be made easily at the channel part of the MOS transistor, a conventional problem, i.e., floating body effect, can be controlled and a high performance low power consumption integrated circuit can be fabricated by reducing the capacitance through the use of an SOI substrate. Furthermore, it can function as a vertical bipolar transistor when the gate potential of the vertical MOS transistor is fixed lower than a threshold level and the body contact is defined as a base.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, in particular, an SOI.
(Silicon on insulator) This invention relates to a low capacity, high performance, low power consumption MOS transistor formed on a substrate.

[0002]

2. Description of the Related Art Conventionally, as semiconductor devices have become more highly integrated, their components have been miniaturized. Especially,
MOS transistors are being miniaturized to improve their performance and to achieve higher integration of integrated circuits. However, as the total number of transistors on an integrated circuit increases, the power consumption becomes extremely large, which is becoming an obstacle to integration. Furthermore, at present, MOS of 0.1 micron or less
Research and development of type transistors is active, and the gate length is 0.
025 micron devices have also been reported to operate as transistors at room temperature (eg, C. Fiegna et a).
l., IEEE Transaction on Electron Devices, vol.41,
No.6 p.941). However, these lithography are no longer optically possible, and electron beam lithography is mainly used at the research stage, and the prospect of mass production is not clear.

[0003]

According to the present invention, a high-performance MOS transistor having an extremely fine gate length is formed without using electron beam lithography, and the capacitance is reduced to achieve low power consumption. An object is to form a high-performance integrated circuit.

In the present invention, a high-performance MOS transistor having an extremely fine gate length is formed without using electron beam lithography by forming a channel perpendicular to a silicon substrate. Furthermore, by forming this transistor on an SOI substrate, the capacitance can be reduced and a low power consumption and high performance integrated circuit can be formed.

[0005]

An embodiment will be described below with reference to the drawings.

FIG. 1 shows a manufacturing stage of a vertical n-channel MOS transistor according to a first embodiment of the present invention.

FIG. 1A shows a bonded SOI (silicon on insulator) substrate for forming a MOS transistor. 1 silicon 3 doped with Sb to high concentrations of about 10 ²⁰ / cm ³ on the buried oxide film 2 of about 0.5 microns and a silicon substrate are laminated. This silicon layer 3 will be a drain later. In (b), a channel is formed later by an epitaxial method at a temperature of 1000 ° C. 1
A silicon film doped with B to a concentration of about 0 ¹⁶ / cm ^{3 is} deposited to a thickness of about 0.1 μm, and
Sb at a temperature of 0 ° C. to a thickness of 0.2 μm at 10 ²⁰ / cm
A silicon layer 5 doped at a high concentration of about ³ is formed.
Thereafter, as shown in (c), the epitaxial silicon layer 5 serving as a source, the epitaxial silicon layer 4 serving as a channel, and the epitaxial silicon layer 3 serving as a drain are processed by dry etching. Thereafter, a silicon oxide film 6 having a thickness of about 0.2 μm is formed as a protective film (passivation film) by a chemical vapor deposition method (CVD method). In (d), the region for forming the gate of the transistor is processed by the usual lithography method and dry etching method as shown in the figure. In (e), a silicon oxide film 7 having a thickness of about 3 nm is
Form at ° C. Thereafter, a polycrystalline silicon film 8 doped with As at a high concentration of about 0.3 μm as a gate electrode is deposited and processed. In (f), a contact hole is formed by a dry etching method, an electrode material such as W is deposited so as to fill the contact hole, and a gate terminal 9 and a source terminal 1 are formed.
0, body contact terminal 11, and drain terminal 1
2 are formed.

Next, the fact that this SOI vertical MOS transistor can be actually formed will be described based on computer simulation results. FIG. 2 was formed by the steps of the above embodiment.
3 shows a distribution of impurity concentration in a vertical direction of a MOS transistor.
From the surface, it can be seen that the distribution of the impurity concentration of the source, the channel, and the drain is clearly formed. Especially,
From this figure, it can be seen that the transistor channel length is as short as about 0.1 micron and a high-speed and high-performance device can be formed.

Since the device manufactured in this embodiment is formed on an SOI substrate, it has a small capacitance and a reduced power consumption. Further, since the body contact is easy as shown in FIG. 1 (f), it is possible to prevent the characteristic fluctuation (floating body effect) due to the accumulation of minority carriers, which is a problem in the conventional SOI type MOS transistor. Further, since the potential of the body contact terminal can be freely changed, the threshold voltage of the transistor can be controlled.
Moreover, if the gate electrode and the body contact terminal are connected, the threshold can be controlled to be low, and the device can be easily operated at a low voltage.

Further, the body contact 11 is regarded as a base electrode by either the method of fixing the gate voltage of the vertical MOS transistor shown in FIG. By operating the drain 11 as a collector and base as a vertical bipolar transistor, a vertical MOS transistor and a chip can be mixed. This facilitates the formation of a BiCMOS circuit and greatly facilitates circuit design. On the other hand, in the SOI, since the vertical bipolar transistor and the vertical MOS transistor can be completely separated from each other by a dielectric, a power supply circuit can be formed on the same chip.

In the above embodiment, the respective diffusion layers are formed by using the epitaxial deposition method of silicon. However, the same effect can be realized by using an ion implantation method, a solid phase diffusion method or the like.

Next, as a second embodiment, a complementary MOS (CMOS) transistor using a vertical transistor will be described. FIG. 3 is a conceptual sectional view of the CMOS process. FIG. 3A shows a process of forming a device using a normal bonded SOI substrate. 0.5 on silicon substrate 1
A buried oxide film 2 having a thickness of micron is formed, and a single crystal SOI layer 13 doped with B of about 10 ¹⁵ / cm ³ is formed thereon to a thickness of about 0.1 μm. In (b), B ions are implanted at 2 × 10 ¹⁵ / cm ² at an acceleration energy of 20 keV using the photoresist 14 as a mask, and nitrogen annealing is performed to form ap ⁺ diffusion layer 15. Next, in FIG. 5C, As shown in the figure, As is ion-implanted into the remaining region at a concentration of 5 × 10 ¹⁵ / cm ² at an acceleration energy of 80 keV using the photoresist 16 as a mask, followed by nitrogen annealing to form an n ⁺ diffusion layer 17.
In (d), the film thickness is 0.2 μm and the phosphorus impurity concentration is 4 ×.
An n ^- epitaxial silicon film 18 of 10 ¹⁷ / cm ³ is formed. In (e), using a photoresist 19 for a part of the n ^- layer 18, B is accelerated to 1 × with an acceleration energy of 20 keV.
10 ¹³ / cm ² ions are implanted to form the p ⁻ layer 20.
In (f), a non-doped polycrystalline silicon film 21 having a thickness of 0.1 μm is deposited. In (g), an n ⁺ -doped oxide film is deposited on the surface of the non-doped polycrystalline silicon film 21 by spin coating or the like, and is processed as shown in the figure by a normal photolithography method. In (h), ap ⁺ -doped oxide film 23 is deposited on the exposed surface of the non-doped polycrystalline silicon film 21 by spin coating or the like, and then B ⁺
Ion implantation is performed at 0 keV at 1 × 10 ¹⁵ / cm ² . This was performed for the purpose of compensating for a small amount of B diffused from the oxide film 23 to the polycrystalline silicon film 21 due to a difference in segregation coefficient. After that, RTA (rapid thermal
As shown in (i), ap ⁺ diffusion layer 24 and an n ⁺ diffusion layer 25 are formed by nitrogen annealing by annealing.
(J) is a diagram processed by a dry etching method to separate the pMOS region and the nMOS region on the right side of the drawing. Thereafter, as shown in (k), in the same steps as in the first embodiment, the pMOS gate oxide film 26, the nMOS gate oxide film 27, the pMOS gate polycrystalline silicon film 28, and the nMOS gate polycrystalline silicon film 2 are formed.
9, passivation film 30, passivation film 3
1, gate terminal 32 for p-MOS, source terminal 3 for p-MOS
3. A p-MOS body contact terminal 34, an n-MOS gate terminal 35, an n-MOS source terminal 36, an n-MOS body contact terminal 37 and the like are formed to form a CMOS structure. Although the connection terminals of the p + diffusion layer 15 and the n + diffusion layer 17 are not shown in FIG. 7 (k), this is not necessary if the two terminals are ohmically joined. Of course, connection can also be made using metal wiring. According to the present embodiment, the transistor can be formed without a transistor electron beam writing apparatus having a channel length of about 0.1 μm. Another characteristic is that the body contact is easy and the substrate potential of the pMOS and nMOS transistors can be freely controlled differently from conventional CMOS.
Since the threshold values of the transistors can be controlled independently, the degree of freedom in circuit design can be greatly improved.

[0013]

As described above, in the present invention,
By forming the channel perpendicular to the silicon substrate,
To form high-performance MOS transistors with ultra-fine gate lengths without using electron beam lithography. Furthermore, since the MOS type transistor can easily form a body contact in the channel portion, the floating body effect, which has been a problem in the past, can be controlled, and the capacitance can be reduced by forming the MOS transistor on an SOI substrate. An integrated circuit with high power consumption and high performance can be formed.

[0014]

[Brief description of the drawings]

FIGS. 1A to 1F are conceptual views of a cross section of a manufacturing process of an n-channel vertical MOS transistor, which are divided into FIGS. 1A to 1F to explain a first embodiment of the present invention.

FIG. 2 is a simulation result of an impurity distribution showing that an n-channel vertical MOS transistor according to the first embodiment of the present invention can be manufactured.

FIGS. 3A and 3B are conceptual views showing a cross section of a manufacturing process of a CMOS structure in which an n-channel vertical MOS transistor and a p-channel vertical MOS transistor are manufactured in the same process, in order to explain a second embodiment of the present invention; FIG.

FIG. 4 is a conceptual diagram of a cross section of a CMOS structure manufacturing process for manufacturing an n-channel vertical MOS transistor and a p-channel vertical MOS transistor in the same process for explaining a second embodiment of the present invention.

FIG. 5 is a simulation result of impurity distribution showing that a CMOS vertical MOS transistor according to the second embodiment of the present invention can be manufactured.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 Si substrate 2 silicon oxide 3 SOI layer 4 epitaxial silicon doped with B 5 epitaxial silicon doped with Sb 6 passivation layer 7 gate oxide film 8 gate electrode 9 gate terminal 10 source terminal 11 body contact terminal 12 drain terminal

(72) Inventor Toshiaki Ikoma 17 Miyukigaoka, Tsukuba City, Ibaraki Prefecture Inside the Texas Instruments Tsukuba R & D Center (72) Inventor Naoki Abe 2350 Kihara, Miura Village, Inashiki-gun, Ibaraki Prefecture Nippon Texas Instruments Miura factory

Claims (5)

[Claims] To 1. A SOI substrate, respectively to form the source / channel / drain n ⁺ (p ⁺⁾ silicon layer / p ^-
A stacked film of (n ⁻ ) silicon layer / n ⁺ (p ⁺ ) silicon layer is formed, a gate insulating film is formed on a cross section of the stacked film in a direction perpendicular to the SOI substrate, and a surface of the gate insulating film is formed. A vertical SOI device having a gate electrode and a vertical MOS transistor. 2. A p-channel and n-channel vertical MOS transistor having a source and a drain connected to each other, and
2. The vertical SOI device according to claim 1, wherein a vertical MOS transistor is formed. 3. A vertical MOS transistor and a CMOS vertical MO.
3. The vertical SOI device according to claim 2, wherein the S transistor includes a vertical MOS transistor having a body contact terminal. 4. The vertical SOI device according to claim 3, wherein the threshold voltage of the vertical MOS transistor and the CMOS vertical MOS transistor is adjusted by adjusting a bias voltage applied to the body contact terminal. 5. A method in which a body contact is regarded as a base electrode and a source and a drain are defined as a collector and a base, respectively, by either fixing the gate voltage of the vertical MOS transistor below a threshold value or not forming a gate electrode. 4. The vertical SOI device according to claim 3, wherein the device is operated as a bipolar transistor.