CN110429030A - The preparation method of nanometer grid and nanometer gate device - Google Patents
The preparation method of nanometer grid and nanometer gate device Download PDFInfo
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- CN110429030A CN110429030A CN201910696974.0A CN201910696974A CN110429030A CN 110429030 A CN110429030 A CN 110429030A CN 201910696974 A CN201910696974 A CN 201910696974A CN 110429030 A CN110429030 A CN 110429030A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention is suitable for technical field of semiconductor device, provide the preparation method of a kind of nanometer of grid, it include: the photoetching offset plate figure on the first photoresist according to first medium layer surface deposition, first time etching is carried out to the region other than first medium layer surface photoetching offset plate figure, first photoresist of the first medium layer surface deposition after removal first time etching, the step structure that the first medium layer after obtaining substrate and first time etching is constituted；The deposited metal layer on the horizontal surface and vertical sidewall of step structure, and second dielectric layer is grown on the surface of metal layer；Second is carried out to metal layer and second dielectric layer to etch；Three dielectric layer of growth regulation on step structure after being etched at second, and third dielectric layer surface is polished, third dielectric layer upper surface is flushed and exposes the corresponding metal of metal layer, obtain nanometer grid.The present invention can accurately control the size of nanometer grid using the metal layer of step vertical sidewall as nanometer grid, reduce the manufacture difficulty of nanometer grid.
Description
Technical field
The invention belongs to technical field of semiconductor device more particularly to the preparation sides of a kind of nanometer of grid and nanometer gate device
Method.
Background technique
In integrated circuit fields, in order to promote the performance and integrated level of semiconductor chip, in decades using silicon materials as base
The transistor feature size of plinth constantly reduces, and moves closer to its physics limit.
Grid is the control terminal of transistor, and size has great influence to the performance of electronic device.Currently, device is received
Meter level grid length dimensioned becomes further difficult.When preparing electronic device using existing photoetching technique, grid length size is not only
Dependent on the resolution ratio of lithographic equipment, photoresist type in photoetching process, baking temperature, exposure dose, development are additionally depended on
The various factors such as temperature and time.This causes the grid length size of device to be not easy to be accurately controlled, especially nanoscale
Grid preparation is difficult.In order to maintain the continuous development of IC industry, need to develop new preparation method, in order to can simplify
The preparation of the grid of nanoscale, it is accurate to control grid length size, and realize the preparation of nanometer gate device, and then promote electronic device
Performance.
Summary of the invention
In view of this, the embodiment of the invention provides the preparation method of a kind of nanometer of grid, to solve in existing photoetching process
There are various factors, and device grid length size to be caused to be not easy to be accurately controlled, and the grid preparation of especially nanoscale is difficult to ask
Topic.
The first aspect of the embodiment of the present invention provides the preparation method of a kind of nanometer of grid, comprising:
According to the photoetching offset plate figure on the first photoresist of the first medium layer surface deposition grown on substrate, to described
Region other than photoetching offset plate figure described in first medium layer surface carries out first time etching, and the after removing the first time etching
First photoresist of one dielectric layer surface deposition, what the first medium layer after obtaining the substrate and first time etching was constituted
Step structure；
One layer of metal layer is deposited on the horizontal surface and vertical sidewall of the step structure, and in the table of the metal layer
It looks unfamiliar long second dielectric layer；
Second is carried out to the metal layer and the second dielectric layer to etch；
Three dielectric layer of growth regulation on step structure after being etched described second, and to the third dielectric layer surface into
Row polishing, flushes third dielectric layer upper surface and exposes the corresponding metal of the metal layer, obtains nanometer grid.
Optionally, the substrate is semi-insulating substrate or High resistivity substrate.
Optionally, the material of the semi-insulating substrate is any one of silicon, silicon carbide, sapphire or diamond；
The material of the High resistivity substrate is in glass, flexible mylar, flexible polyimide film, mica or ceramics
It is any.
Optionally, the first medium layer, the second dielectric layer and the third dielectric layer are all made of atomic layer deposition
ALD equipment or the growth of plasma enhanced chemical vapor deposition PECVD device.
Optionally, the material of the first medium layer, the second dielectric layer and the third dielectric layer is titanium dioxide
One of silicon, aluminium oxide, hafnium oxide, titanium oxide, silicon nitride and aluminium nitride or a variety of combinations.
Optionally, the first medium layer with a thickness of 100nm；
The second dielectric layer with a thickness of 10nm；
The third dielectric layer with a thickness of 120nm.
Optionally, the first time etching is using inductively coupled plasma ICP etching apparatus to the first medium layer
Region other than photoetching offset plate figure described in surface carries out dry etching.
Optionally, the metal layer with a thickness of 1nm-500nm.
It is optionally, described that one layer of metal layer is deposited on the horizontal surface and vertical sidewall of the step structure, comprising:
Using electron beam evaporation equipment, a thickness is deposited on the deposition horizontal surface and vertical sidewall of the step structure
Degree is the metal layer of 10nm；
The material of the metal layer be gold, silver, copper, aluminium, zinc, molybdenum, iridium, tungsten, cobalt, cadmium, nickel, iron, platinum, chromium, titanium, palladium, germanium,
One of lead and beryllium or a variety of combinations.
The second aspect of the embodiment of the present invention provides the preparation method of a kind of nanometer of gate device, comprising: uses above-mentioned
After the preparation method production nanometer grid of nanometer grid described in one embodiment, gate medium is grown in the third dielectric layer upper surface of polishing
Layer；
Semiconductor material is prepared on the gate dielectric layer；
According to the photoetching offset plate figure on the second photoresist deposited on the semiconductor material, on second photoresist
Photoetching offset plate figure other than the corresponding gate dielectric layer in region and semiconductor material carry out third time etching, until exposing the gold
Belong to the corresponding metal of layer；
The grid that the nanometer gate device is prepared on the nanometer grid is not being etched etched grid by the third time
The source electrode and drain electrode of the nanometer gate device is prepared on the conduction channel region that dielectric layer and semiconductor material are formed.
The embodiment of the present invention forms a step structure by the first medium layer after substrate and etching, by Step-edge Junction
Deposited metal layer and the metal layer of step structure horizontal surface is removed on structure, retains the metal layer of step structure vertical sidewall, benefit
With the metal layer of step structure vertical sidewall, nanometer grid are prepared, nanometer grid are made by step structure, rather than pass through deposition multilayer
Photoresist photoetching reduces the manufacture difficulty of nanometer grid, by setting the thickness of metal layer, can accurately control the ruler of nanometer grid
It is very little, obtain high-precision nanometer grid.
Nanometer gate device is prepared using the nanometer grid of preparation of the embodiment of the present invention, since the embodiment of the present invention can obtain height
The nanometer grid of precision, and then the nanometer gate device with high-precision grid length can be obtained, and then promote the performance of nanometer gate device.
Detailed description of the invention
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to embodiment or description of the prior art
Needed in attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only of the invention some
Embodiment for those of ordinary skill in the art without any creative labor, can also be according to these
Attached drawing obtains other attached drawings.
Fig. 1 is the preparation method flow diagram of a kind of nanometer of grid provided in an embodiment of the present invention；
Fig. 2 (1) is the structural schematic diagram of one dielectric layer of growth regulation on substrate provided in an embodiment of the present invention；
Fig. 2 (2) is the structural schematic diagram provided in an embodiment of the present invention that photoetching offset plate figure is formed on the first photoresist；
Fig. 2 (3) is the structural schematic diagram after progress first time etching provided in an embodiment of the present invention；
Fig. 2 (4) is deposited metal layer provided in an embodiment of the present invention and grows the structural schematic diagram after second dielectric layer；
Fig. 2 (5) is the structure provided in an embodiment of the present invention carried out after second of etching to metal layer and second dielectric layer
Schematic diagram；
Fig. 2 (6) is three dielectric layer of growth regulation on the step structure provided in an embodiment of the present invention after second of etching
Structural schematic diagram；
Fig. 2 (7) is that the structure provided in an embodiment of the present invention for carrying out polishing acquisition nanometer grid to third dielectric layer surface is shown
It is intended to；
Fig. 3 (1) is that the structure of growth gate dielectric layer and semiconductor material provided in an embodiment of the present invention on nanometer grid is shown
It is intended to；
Fig. 3 (2) is the knot provided in an embodiment of the present invention carried out after third time etching to gate dielectric layer and semiconductor material
Structure schematic diagram；
Fig. 3 (3) is the structural schematic diagram of a kind of nanometer of gate device provided in an embodiment of the present invention.
In figure: 1- substrate；2- first medium layer；Photoetching offset plate figure on the first photoresist of 3-；4- metal layer；5- second is situated between
Matter layer；6- third dielectric layer；7- gate dielectric layer；8- semiconductor material；9- grid；10- source electrode；11- drain electrode.
Specific embodiment
In being described below, for illustration and not for limitation, the tool of such as particular system structure, technology etc is proposed
Body details, to understand thoroughly the embodiment of the present invention.However, it will be clear to one skilled in the art that there is no these specific
The present invention also may be implemented in the other embodiments of details.In other situations, it omits to well-known system, device, electricity
The detailed description of road and method, in case unnecessary details interferes description of the invention.
In order to illustrate technical solutions according to the invention, the following is a description of specific embodiments.
(1) to Fig. 2 (7), the preparation method of a kind of nanometer of grid provided in an embodiment of the present invention include: referring to Fig. 1 and Fig. 2
Step S101, according to the photoresist on the first photoresist of 2 surface of the first medium layer deposition grown on substrate 1
Figure 3 carries out first time etching to the region other than photoetching offset plate figure 3 described in the first medium layer surface, removes described the
First photoresist of the first medium layer surface deposition after primary etching, after obtaining the substrate 1 and first time etching
The step structure that first medium layer 2 is constituted.
(1) referring to fig. 2, one dielectric layer 2 of growth regulation on substrate 1.
As shown in Fig. 2 (2), the photoetching offset plate figure 3 on the first photoresist covers the part of first medium layer, to not by
The region that photoetching offset plate figure 3 on one photoresist is covered carries out first time etching, removes the photoresist figure on the first photoresist
Photoresist representated by shape 3, the step structure that the first medium layer 2 after obtaining substrate 1 in Fig. 2 (3) and etching for the first time is constituted.
Optionally, substrate 1 is semi-insulating substrate or High resistivity substrate.
Optionally, the material of semi-insulating substrate is any one of silicon, silicon carbide, sapphire, diamond；High resistivity substrate
Material is any one of glass, flexible mylar, flexible polyimide film, mica or ceramics.
Wherein, flexible mylar (Polyethylene terephthalate, PET) abbreviation PET film is with poly- to benzene
Dioctyl phthalate ethyl alcohol ester is raw material, sheet is made using extrusion molding, then through thin-film material made of biaxial tension, usually colourless
Bright, glossiness film, good mechanical performance, rigidity, hardness and toughness are high, puncture-resistant, rub resistance, high temperature resistant and low temperature, resistance to
Chemicals.Oil resistivity, air-tightness and fragrance protectiveness are good, are one of common barrier laminated film substrates.
Wherein, flexible polyimide film (Polyimide Film, PI) abbreviation PI film is best thin of performance in the world
Film class insulating materials is passed through in intensive polar solvent through polycondensation and casting film-forming again by pyromellitic acid anhydride and diaminodiphenyl ether
Imidization forms.
PI film is in yellow transparent, and relative density 1.39~1.45, PI film is with excellent resistant of high or low temperature, electric insulation
Property, caking property, radiation resistance, resistance to medium, can be used for a long time within the temperature range of -269 DEG C~280 DEG C, can reach in short-term
400 DEG C of high temperature.The glass transition temperature of common producer PI film is respectively 280 DEG C (Upilex R), 385 DEG C (Kapton) and 500
DEG C or more (Upilex S).PI film tensile strength at 20 DEG C is 200MPa, and 100MPa is greater than at 200 DEG C, particularly suitable to be used as
Flexible circuit board substrate and various heat resisting motor electrical apparatus insulation materials.
Illustratively, on semi insulating silicon carbide silicon substrate 1, atomic layer deposition (Atomic Layer is utilized
Deposition, ALD) equipment growth aluminium oxide first medium layer 2, with a thickness of 100nm；On 2 surface of aluminium oxide first medium layer
It coats the first photoresist, after exposure development, forms the photoetching offset plate figure 3 on the first photoresist.
Illustratively, on HR-Si substrate 1, plasma enhanced chemical vapor deposition (Plasma Enhanced is utilized
Chemical Vapor Deposition, PECVD) equipment growth silica first medium layer 2, with a thickness of 100nm；Two
2 surface of silica first medium layer coats the first photoresist, after exposure development, forms the photoetching offset plate figure 3 on the first photoresist.
Wherein, the thickness of first medium layer is not limited in the embodiment of the present invention, first medium thickness degree 100nm is this
A specific embodiment of substrate in inventive embodiments.
Wherein, ALD equipment, be using Atomic layer deposition method, by substance with monatomic form membrane being plated in layer
The technology of substrate surface, in atomic layer deposition process, the chemical reaction of new one layer of atomic film is that directly preceding layer is related therewith
Connection, this mode makes each reaction only deposit one layer of atom.
High controllability (thickness, composition and structure) of the technique for atomic layer deposition due to its deposition parameter, excellent deposition
Uniformity and consistency make it have a wide range of applications potentiality, such as transistor gate in the fields such as wiener electronics and nano material
Pole dielectric layer (high-k) and metal gate electrode field.
Wherein, PECVD device is to make the gas containing film composed atom by microwave or radio frequency etc., is being partially formed
Plasma, and plasma chemistry activity is very strong, it is easy to it reacts, goes out desired film in deposition on substrate.Benefit
Have deposition rate fast with PECVD device somatomedin layer, quality of forming film is good, and pin hole is less, the advantages of not being easily cracked.
Optionally, using inductively coupled plasma (Inductively Coupled Plasma, ICP) etching apparatus to
Region other than photoetching offset plate figure 3 described in one dielectric layer surface carries out dry etching.
Wherein, dry etching has anisotropic characteristics, and steep smooth side wall construction can be etched, not by first
After the region that photoetching offset plate figure 3 on photoresist is covered all is etched away, the first photoresist is removed, sidewall is formed
Step structure.
Wherein, etching will not be sheltered by upper layer masking material in subsurface material by physically and/or chemically method
Part is removed, thus obtained on subsurface material with the completely corresponding figure of masking film pattern, etch and be divided into dry etching and wet
Method etching, dry etching are that reaction gas is made to generate the high ion and electronics of reactivity using radio-frequency power supply, to needing to etch
Part carry out physical bombardment and chemical reaction, the region that we need to remove with the removal of selectivity.
ICP lithographic technique is one kind of dry etching, and the equipment abbreviation ICP of dry etching is carried out using ICP lithographic technique
Equipment, ICP lithographic technique, which has, carves fast fast, selection than high, anisotropy is high, etching injury is small, large-area uniformity is good, etching
The advantages that profiled outline controllability height and flat and smooth etching surface, ICP lithographic technique be widely used in silicon, silica and
In the etching of the materials such as III-V compound, there is good etching effect.
Step S102 deposits one layer of metal layer 4 on the horizontal surface and vertical sidewall of step structure, and in metal layer 4
Surface grow second dielectric layer 5.
Optionally, the material of metal layer 4 be gold, silver, copper, aluminium, zinc, molybdenum, iridium, tungsten, cobalt, cadmium, nickel, iron, platinum, chromium, titanium,
One of palladium, germanium, lead, beryllium or a variety of combinations.
Optionally, metal layer 4 with a thickness of 1nm-500nm.
Illustratively, referring to fig. 2 (4), using electron beam evaporation equipment, step outer surface (including horizontal surface and
Vertical sidewall), the layer gold 4 of one layer of 10nm is first deposited, it is long in 4 surface regeneration of layer gold followed by PECVD device or ALD equipment
The silica or aluminium oxide second dielectric layer 5 of 10nm thickness.
Step S103 carries out second to metal layer 4 and second dielectric layer 5 and etches.
Illustratively, using ICP equipment, the aluminium oxide second dielectric layer on step structure horizontal surface is first etched away, is hung down
Aluminium oxide second dielectric layer on straight sidewall remains, and followed by ICP equipment, etches away on step structure horizontal surface
Layer gold, the layer gold on vertical sidewall remain.
Illustratively, using ICP equipment, the silica second dielectric layer of step structure horizontal surface is first etched away, is hung down
Silica second dielectric layer on straight sidewall remains, and followed by ICP equipment, etches away on step structure horizontal surface
Layer gold, the layer gold on vertical sidewall remains.
(5) referring to fig. 2, for the metal layer 4 and second dielectric layer 5 remained on step structure vertical sidewall.
Wherein, the second dielectric layer 5 on vertical sidewall has the function of guard metal layer 4, when making etching sheet metal 4, hangs down
Metal layer on straight sidewall is not etched, and thickness remains constant.
Wherein, since ICP equipment is to etch from top to bottom, thus can retain second dielectric layer and gold on vertical sidewall
Belong to layer.
Step S104, three dielectric layer 6 of growth regulation on the step structure after second of etching, and to 6 table of third dielectric layer
Face is polished, and is flushed the upper surface of third dielectric layer 6 and is exposed the corresponding metal of metal layer 4, and nanometer grid are obtained.
Illustratively, using ALD equipment, the aluminium oxide of the step structure surface growth 120nm thickness after being etched at second
Third dielectric layer carries out planarization polishing process to aluminium oxide third dielectric layer surface, after growth aluminium oxide third dielectric layer
Step structure throw flat, enable the upper surface of aluminium oxide third dielectric layer flush, expose the layer gold of 10nm, obtain smooth light
Sliding surface.
Optionally, third dielectric layer can also be the silica third dielectric layer of 120nm thickness.
Wherein, the thickness of third dielectric layer is not limited in the embodiment of the present invention, third thickness of dielectric layers 120nm is this
A specific embodiment of substrate in inventive embodiments, the specific thickness of third dielectric layer is determines according to actual conditions.
Wherein, Fig. 2 (6) is the structural schematic diagram of three dielectric layer 6 of growth regulation on the step structure after second layer etching, figure
2 (7) are the structural schematic diagram of the nanometer grid of acquisition after polishing to 6 surface of third dielectric layer.
Metal layer at this time forms a nanometer grid structure, and the size of this nanometer of grid passes through electron beam evaporation equipment evaporated metal
It is accurately controlled when the thickness of layer, the available metal layer down to 1nm thickness of electron beam evaporation equipment.
Optionally, the material of first medium layer 2, second dielectric layer 5 and third dielectric layer 6 be silica, aluminium oxide,
One of hafnium oxide, titanium oxide, silicon nitride, aluminium nitride or a variety of combinations.
As another embodiment of the present invention, received using the preparation method production of nanometer grid described in any of the above-described embodiment
After rice grid, gate dielectric layer 7 is grown in 6 upper surface of third dielectric layer of polishing.
Semiconductor material 8 is prepared on gate dielectric layer 7.
Referring to Fig. 3 (1), gate dielectric layer 7 is grown in 6 upper surface of third dielectric layer of polishing, preparation half on gate dielectric layer 7
Conductor material 8.
Referring to Fig. 3 (2), according to the photoetching offset plate figure on the second photoresist deposited on semiconductor material 8, to described second
The corresponding gate dielectric layer 7 in the region other than photoetching offset plate figure and semiconductor material 8 on photoresist carry out third time etching, until
Expose the corresponding metal of the metal layer.
Referring to Fig. 3 (3), the grid of nanometer gate device is prepared on nanometer grid, is not being etched by the third time
Gate dielectric layer and semiconductor material formed conduction channel region on prepare nanometer gate device source electrode and drain electrode.
Illustratively, using ALD equipment, the aluminium oxide gate dielectric layer of 10nm thickness is grown on the third dielectric layer 6 of polishing
7, graphene made from chemical vapor deposition (Chemical Vapor Deposition, CVD) method is then transferred to aluminium oxide
On gate dielectric layer 7, semiconductor material 8 needed for forming preparation nanometer gate device.
It coats the second photoresist on semiconductor material 8, after exposure development, forms the photoresist figure on the second photoresist
Shape carries out third time etching to the region other than the photoetching offset plate figure on the second photoresist, etches away wherein using ICP equipment
Semiconductor material 8 and gate dielectric layer 7, until expose the corresponding metal of metal layer 4.
Wherein, 10nm thickness oxidation alum gate dielectric layer 7 is a specific embodiment in the embodiment of the present invention, the present invention couple
The thickness of gate dielectric layer is with no restriction.
Wherein the corresponding metal of the metal layer is the preparation method system using nanometer grid described in any of the above-described embodiment
The nanometer grid of work.
Wherein, the gate dielectric layer 7 and semiconductor material 8 of the photoetching offset plate figure protection on the second photoresist form conducting channel
Region forms grid on nanometer grid, forms source electrode and drain electrode on conduction channel region, forms graphene-based nanometer grid device
Part.
Illustratively, using PECVD device, the silicon dioxide gate that 10nm thickness is grown on the third dielectric layer 6 of polishing is situated between
Then molybdenum disulfide is transferred on silicon dioxide gate dielectric layer 7 by matter layer 7, semiconductor needed for forming preparation nanometer gate device
Material 8.
It coats the second photoresist on semiconductor material 8, after exposure development, forms the photoresist figure on the second photoresist
Shape carries out third time etching to the region other than the photoetching offset plate figure on the second photoresist, etches away wherein using ICP equipment
Semiconductor material 8 and gate dielectric layer 7, until expose the corresponding metal of metal layer 4.
Wherein, 10nm thickness silicon dioxide gate dielectric layer 7 is a specific embodiment in the embodiment of the present invention, the present invention
With no restriction to the thickness of gate dielectric layer.
Wherein the corresponding metal of the metal layer is the preparation method system using nanometer grid described in any of the above-described embodiment
The nanometer grid of work.
Wherein, the gate dielectric layer 7 and semiconductor material 8 of the photoetching offset plate figure protection on the second photoresist form conducting channel
Region forms grid on nanometer grid, and source electrode and drain electrode is formed on conduction channel region, forms molybdenum-disulfide radical nanometer grid device
Part.
Optionally, the material phase of the material of gate dielectric layer 7 and first medium layer 2, second dielectric layer 5 and third dielectric layer 6
It together, can be one of silica, aluminium oxide, hafnium oxide, titanium oxide, silicon nitride, aluminium nitride or a variety of combinations.
Optionally, semiconductor material 8 is graphene, two-dimentional Transition-metal dichalcogenide, black squama, diamond, silicon, oxidation
One of gallium, gallium nitride, indium phosphide, silicon carbide and organic semiconducting materials or a variety of combinations.
Nanometer gate device in the embodiment of the present invention is received since prepare in foregoing invention embodiment high-precision is utilized
Rice grid, and then the nanometer gate device with high-precision grid length can be obtained, and then promote the performance of nanometer gate device.
Embodiment described above is merely illustrative of the technical solution of the present invention, rather than its limitations；Although referring to aforementioned reality
Applying example, invention is explained in detail, those skilled in the art should understand that: it still can be to aforementioned each
Technical solution documented by embodiment is modified or equivalent replacement of some of the technical features；And these are modified
Or replacement, the spirit and scope for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution should all
It is included within protection scope of the present invention.
Claims (10)
1. the preparation method of a kind of nanometer of grid characterized by comprising
According to the photoetching offset plate figure on the first photoresist of the first medium layer surface deposition grown on substrate, to described first
Region other than photoetching offset plate figure described in dielectric layer surface carries out first time etching, and first after removing the first time etching is situated between
First photoresist of matter layer surface deposition, the step that the first medium layer after obtaining the substrate and first time etching is constituted
Structure；
One layer of metal layer is deposited on the horizontal surface and vertical sidewall of the step structure, and raw on the surface of the metal layer
Long second dielectric layer；
Second is carried out to the metal layer and the second dielectric layer to etch；
Three dielectric layer of growth regulation on step structure after being etched at described second, and the third dielectric layer surface is thrown
Light flushes third dielectric layer upper surface and exposes the corresponding metal of the metal layer, obtains nanometer grid.
2. the preparation method of as described in claim 1 nanometer of grid, which is characterized in that
The substrate is semi-insulating substrate or High resistivity substrate.
3. the preparation method of as claimed in claim 2 nanometer of grid, which is characterized in that
The material of the semi-insulating substrate is any one of silicon, silicon carbide, sapphire or diamond；
The material of the High resistivity substrate is any in glass, flexible mylar, flexible polyimide film, mica or ceramics
Kind.
4. the preparation method of as described in claim 1 nanometer of grid, which is characterized in that
The first medium layer, the second dielectric layer and the third dielectric layer are all made of atomic layer deposition ALD equipment or wait
Gas ions enhance the growth of chemical vapor deposition PECVD device.
5. the preparation method of as described in claim 1 nanometer of grid, which is characterized in that
The material of the first medium layer, the second dielectric layer and the third dielectric layer is silica, aluminium oxide, oxygen
Change one of hafnium, titanium oxide, silicon nitride and aluminium nitride or a variety of combinations.
6. such as the preparation method of nanometer grid described in any one of claim 1 to 5, which is characterized in that
The first medium layer with a thickness of 100nm；
The second dielectric layer with a thickness of 10nm；
The third dielectric layer with a thickness of 120nm.
7. the preparation method of as described in claim 1 nanometer of grid, which is characterized in that the first time etching is using inductance coupling
It closes plasma ICP etching apparatus and dry etching is carried out to the region other than photoetching offset plate figure described in the first medium layer surface.
8. the preparation method of as described in claim 1 nanometer of grid, which is characterized in that the metal layer with a thickness of 1nm-
500nm。
9. the preparation method of as claimed in claim 8 nanometer of grid, which is characterized in that the water-glass in the step structure
One layer of metal layer is deposited on face and vertical sidewall, comprising:
Using electron beam evaporation equipment, depositing a layer thickness on the deposition horizontal surface and vertical sidewall of the step structure is
The metal layer of 10nm；
The material of the metal layer be gold, silver, copper, aluminium, zinc, molybdenum, iridium, tungsten, cobalt, cadmium, nickel, iron, platinum, chromium, titanium, palladium, germanium, lead with
And one of beryllium or a variety of combinations.
10. the preparation method of a kind of nanometer of gate device characterized by comprising using the claims 1 to claim 9
Any one of described in nanometer grid preparation method production nanometer grid after, polishing third dielectric layer upper surface grow gate medium
Layer；
Semiconductor material is prepared on the gate dielectric layer；
According to the photoetching offset plate figure on the second photoresist deposited on the semiconductor material, to the light on second photoresist
The corresponding gate dielectric layer in region and semiconductor material other than photoresist figure carry out third time etching, until exposing the metal layer
Corresponding metal；
The grid that the nanometer gate device is prepared on the nanometer grid is not being etched etched gate medium by the third time
The source electrode and drain electrode of the nanometer gate device is prepared on the conduction channel region that layer and semiconductor material are formed.
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