JPH10189718A - Semiconductor device and manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacture thereof which enable formation of a fine multilayer interconnection being submicron or less without causing a problem on characteristics of an increase in electric resistance and a problem on the reliability of a phenomenon of electromigration even when an alignment error occurs. SOLUTION: An insulated gate type field effect transistor or the like is formed on a semiconductor substrate and an insulating film 1 being flattened is so formed as to cover this surface. A conductive part 3 formed on the insulating layer 1, a wiring layer 7 formed on an insulating layer 5 on the wiring layer 3 and a cylindrical wiring connecting part 9 formed in contact with the conductive part 3 and connecting the two layers 3 and 7 are provided. Since the wiring connecting part 9 is so formed as to pierce the wiring layer 7, the lateral side of the wiring layer 7 and that of the wiring connecting part 9 are in contact with each other. Accordingly, the electric connection of the wiring layer 7 and the wiring connecting part 9 is conducted on these lateral sides.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device having a connecting portion for connecting fine multi-layer wirings of submicron or less, and a structure of the connecting portion. It relates to a manufacturing method for forming.

[0002]

2. Description of the Related Art As semiconductor integrated circuits become more highly integrated,
There is a strong demand for forming fine wiring. In accordance with this requirement, it is necessary to finely form contacts for connecting these wiring layers. FIG. 7 is a schematic view showing the structure of this type of semiconductor device, and FIG.
FIG. 7B is a sectional view taken along the line DD ′. A first wiring layer 53 is formed on an insulating film 51 on a semiconductor substrate 50, and a second wiring layer 57 is formed in a direction orthogonal to the first wiring layer 53 with an insulating film 55 interposed therebetween. At the intersection of the first wiring layer 53 and the second wiring layer 57, a contact portion 59 is formed, and these wiring layers 53 and 57 are electrically connected. Further, an overcoat film 61 for protecting the semiconductor device is formed on the entire surface of the semiconductor substrate.
Are formed. As shown in FIG. 7, the first wiring layer 53
The contact portion formed in contact with the upper portion is a columnar conductor, and is in contact with the second wiring layer on the upper surface. For this reason, since the contact portion cannot be seen from the upper surface, FIG.
(A) is indicated by a broken line.

In manufacturing such a semiconductor device, the contact portion 59 is manufactured by the following steps.
For example, first, the first wiring layer 53 is formed on the insulating film 51, and then the insulating layer 55 is formed to cover the wiring layer 53.
Subsequently, after forming a connection hole reaching the first wiring layer 53 in the insulating layer 55, a conductive film made of tungsten (W) is formed to fill the connection hole. Then, the conductive film is formed by CMP until the upper surface of the insulating film 55 is exposed.
When the contact portion is removed by using the method, tungsten is buried in the connection hole to form a contact portion. After that, a second wiring layer 57 connected to the conductive film of the contact part is formed. Thereby, the first wiring layer 53, the second
A wiring layer 57 and a contact portion 59 connecting these wiring layers 53 and 57 are formed.

[0004]

However, in the above-described conventional semiconductor device, since the second wiring layer is formed by using the photolithography technique, the contact portion and the second wiring layer are formed in forming the sub-micron or less multi-layer wiring. An alignment error with the mask for forming the two wiring layers is a factor that limits the miniaturization.

FIG. 8 is a schematic view of such a semiconductor device. FIG. 8A is a plan view, and FIG. 8B is a cross-sectional view taken along line EE ′. FIG. 8 shows a case where the alignment error between the mask for forming the second wiring layer and the contact portion is large.
When the alignment error is large, a part of the contact portion 59 is exposed from the second wiring layer as shown in FIG. 8B, and the contact portion 5 is exposed as shown in FIG.
9 and the contact portion between the second wiring layer and the second wiring layer are small. Such a structure is called a borderless contact.

In the semiconductor device having the structure shown in FIG. 8, since the contact area of the connection portion between the contact portion 59 and the second wiring layer 57 is small, there is a problem in the characteristic that the electric resistance of this portion increases. Further, in this portion, the current crosses a small contact area, so that the current density increases. For this reason,
Electro-Migration (Electro-Mi
There is a reliability problem that the reliability of the wiring layer is reduced due to the "gration" phenomenon.

Therefore, conventionally, measures have been taken to secure a margin for alignment (alignment margin) so as not to cause an increase in electric resistance and a decrease in reliability of wiring due to an alignment error of the mask. For this reason, even if an attempt is made to form a fine wiring of submicron or less, a matching margin is required in the contact portion, and as a result, there has been a problem that miniaturization cannot be achieved in this portion.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device capable of forming a sub-micron or less fine multilayer wiring without causing such a problem in characteristics and a problem in reliability, and a method of manufacturing the same. It is in.

[0009]

The present invention has the following configuration.

In the semiconductor device according to the present invention, a connection hole is formed in an insulating layer on a semiconductor substrate, and a wiring connection portion made of a conductive material is provided in the connection hole. In a semiconductor device in which a conductive portion below a layer is electrically connected, the wiring connection portion extends into the wiring layer and a side surface of the wiring connection portion is electrically connected to the wiring layer.

As described above, these conductors are electrically connected by contacting the side surface of the wiring connection portion and the side surface of the wiring layer. Therefore, even if the cross-sectional area of the connection hole is reduced due to miniaturization, the contact area can be reduced. It can be larger than the structure. In addition, since the alignment error between the wiring layer forming mask and the wiring connection part becomes large, and even when the wiring layer does not surround the wiring connection part, these conductors are in contact with their respective side surfaces. A larger contact area can be ensured than in the past. For this reason, it can suppress that electrical resistance and current density become high in a contact part.

In a method for manufacturing a semiconductor device according to the present invention, a conductive part forming step of forming a conductive part on a semiconductor substrate, an insulating layer forming step of forming an insulating layer on the semiconductor substrate after the conductive part is formed, A conductive layer forming step of forming a conductive layer on the layer, a connecting hole forming step of reaching a conductive part and forming a connecting hole in the insulating layer and the conductive layer, and embedding a conductive material in the connecting hole to form a conductive part and a conductive part. The method includes a wiring connection portion forming step of forming a wiring connection portion connecting the layers, and a wiring layer forming step of forming a wiring layer by patterning the conductor layer.

As described above, a conductive portion is formed on a semiconductor substrate, then an insulating layer is formed, a conductive layer is formed on the insulating layer, and a connection hole penetrates both layers to reach the conductive portion. Since the wiring connection portion is formed by embedding the conductive material in the connection hole, the wiring connection portion penetrating the insulating layer and the conductor layer and reaching the conductive portion is formed. Further, when the wiring layer is formed by patterning the conductor layer, the side surface of the wiring connection portion comes into contact with the side surface of the wiring layer, and electrical connection can be made on this surface.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. In addition, the same portions are denoted by the same reference numerals, and redundant description will be omitted. Note that a case where a silicon semiconductor substrate is used as an example of a semiconductor substrate will be described. Alternatively, a semiconductor layer may be formed over an insulating substrate to form a semiconductor substrate.

(First Embodiment) FIG. 1 is a schematic diagram showing an example of the structure of a semiconductor device according to the present invention.
1A is a plan view, and FIG. 1B is an AA ′ cross-sectional view.
Although not shown in the drawings, an MIS-FET (insulated gate field effect transistor) or the like constituting a semiconductor integrated circuit is formed on a silicon semiconductor substrate (hereinafter, referred to as a substrate) 100. An insulating film such as a (boron-phosphorus-doped silicate glass) film is formed as a base covering this surface. The surface of the insulating film is preferably flattened in order to make the upper wiring finer.

As shown in FIG. 1, a conductive part 3 formed on a base insulating layer 1, an insulating layer 5 formed on a substrate 100 covering the conductive part 3, and a conductive part 3 formed on the insulating film 5 are formed. And a columnar wiring connection portion 9 formed in contact with the conductive portion 3 and extending into the wiring layer to connect the conductive portion 3 and the wiring layer 7. As shown in FIG. 1B, the wiring connection portion 9 is a conductor filled or embedded in a connection hole formed continuously with the insulating film 5 and the wiring layer 7, and is insulated from the wiring layer 7. It has a columnar shape formed by penetrating through the film 5 and reaching the conductive portion 3, and has a cylindrical shape as can be seen from FIG.

As described above, when the wiring connection portion 9 is formed in contact with the conductive portion 3 and penetrates the insulating film 5 and the wiring layer 7, the side surface of the wiring layer 7 and the side surface of the wiring connection portion 9 come into contact with each other. The electrical connection of the two conductors is made at these sides.

With such a structure, a conductive layer,
The connection area between the wiring layers can be increased as compared with the conventional structure. In the semiconductor device shown in FIG.
It is assumed that the wiring layer has a thickness T, for example, R = 0.6 [μm] and T = 0.5 [μm]. In the structure according to the present invention, assuming that the contact hole is almost buried, the contact area is the side area of the column having a height corresponding to the thickness of the wiring layer, so that 3.14 × R × T = 0. 942 [μm ² ]. On the other hand, the contact area in the conventional structure is 3.14 × R ² /4=0.2826 [μm ² ]. That is, when the structure according to the present invention is compared with the conventional structure, the contact area is 3.3 times. This area ratio is T / R
Therefore, when the diameter R of the wiring connection portion is reduced due to the progress of miniaturization, it becomes larger. For example, T = 0.5 [μ
m] and R = 0.3 [μm], it becomes 6.7 times.

FIG. 2 is a schematic diagram showing a case where a wiring layer mask causes a registration error in the structure of the semiconductor device according to the present invention and the wiring layer 7 is formed to the left of the drawing.
2A is a plan view, and FIG. 2B is a sectional view taken along line BB ′.

As shown in FIG. 2A, even when the wiring layers intersect around half of the periphery of the wiring connection portion, the structure according to the present invention secures a contact area of 0.471 [μm ² ]. However, in the conventional structure, it is 0.1413 [μm ² ]. As described above, even if the wiring layer is formed out of the original position due to the alignment error, the contact area can be secured as compared with the related art. Further, since the electrical connection surface is on the side surface of the wiring connection portion, the connection surface is not exposed, so that the influence of plasma damage during processing of the wiring layer 7 can be reduced.

In the present embodiment, the cross-sectional shape of the wiring connection portion is a cylindrical shape having a circular shape. However, the present invention is not limited to this. The cross-sectional shape may be a polygon, an ellipse, or the like. Also,
In order to effectively secure the contact surface with the wiring layer, a shape having long sides along the direction in which the wiring layer extends may be used.

As described above, in the semiconductor device according to the present invention, the insulating layers 1 and 5 are made of Si0
Preferred are materials based on a ₂ system, a SiN system, a SiON system, and materials containing other elements (elements added to semiconductors as impurities) because film formation and processing are easy. Further, a plurality of these materials may be stacked and formed.

The conductive portion 3 and the wiring layer 7 may be made of a conductive material such as various aluminum alloys such as pure aluminum (Al), Al-copper (Cu), Al-silicon (Si), and Al-Si-Cu. Materials are preferred because they are easy to form and process. In addition, conductive materials such as pure Cu and Cu alloy,
This is preferable because a low-resistance wiring can be realized. Alternatively, a material formed by stacking a plurality of these materials may be used.
Further, as the conductive material as the material of the wiring connection portion, a metal is preferable because of its low resistance. In particular, a high melting point metal such as tungsten (W), an aluminum alloy, and the like are preferable because they can be easily formed and processed.

In this embodiment, the case of a two-layer structure including the conductive portion 3 and the wiring layer 7 has been described, but the present invention can be applied to a multilayer wiring having three or more layers. In this case, the same structure may be repeatedly formed by regarding the formed wiring layer as a conductive portion.

As described above, in the semiconductor device according to the present invention, these conductors are connected by contacting the side surface of the wiring connection portion and the side surface of the wiring layer. Can be made larger than before. Specifically, in the conventional structure, the contact area is proportional to the square of the diameter of the connection hole, but in the present structure, it is proportional to the diameter, which is a preferable structure for miniaturization. Also,
Even when the alignment error between the wiring layer forming mask and the wiring connection part becomes large and the wiring layer contacts and crosses a part of the periphery of the wiring connection part, these conductors are in contact on their respective side surfaces. Therefore, a larger contact area can be secured as compared with the related art. Therefore, it is possible to suppress the problem that the electric resistance and the current density increase at the contact portion.

That is, since the above problem can be prevented even if an alignment error occurs, it is not necessary to secure an alignment margin as in the related art, so that the margin between the wiring connection portion and the wiring layer can be reduced. Therefore, a fine semiconductor device with high electrical characteristics and high reliability can be provided.

(Second Embodiment) FIG. 3 and FIG.
FIG. 5 is a schematic cross-sectional view of a main step for describing one embodiment of a method for manufacturing a semiconductor device according to the present invention. A method for manufacturing a semiconductor device will be described with reference to these drawings. Although not shown in the drawings, a semiconductor element such as a MIS-FET constituting a semiconductor integrated circuit is formed on the substrate 100.

First, an insulating film 1 is formed on a semiconductor element (FIG. 3A). The insulating film 1 is, for example, a BPSG film formed of C
VD (Chemical Vapor Deposit)
(ion: chemical vapor deposition) method. After that, it is preferable to flatten the insulating film 1 in miniaturizing the upper wiring layer. The flattening is performed by reflow by heat treatment and CMP (Chemical Mechanical).
ical polishing: chemical mechanical polishing)
Method, an etch-back method or the like.

Next, a conductive portion 3 is formed (FIG. 3).
(A): conductive part forming step). The conductive portion 3 is made of, for example, Al
After forming a Cu film by a 500 [nm] sputtering method, a wiring pattern is formed by a photolithography technique, and RIE (Reactive Ion Ethcin) is performed.
g: reactive ion etching).

Subsequently, an insulating layer 5 is formed (FIG. 3)
(A): insulating layer forming step). The insulating layer 5 is made of, for example, Si
An O ₂ film is formed to a thickness of 2000 [nm] by a CVD method.
The surface is polished and flattened by the MP method. CM
An example of the polishing conditions using the P method is as follows: The number of rotations of the polishing plate: 20 [rpm] The number of rotations of the substrate holding indicator: 20 [rpm] The polishing pressure: 450 [g / cm ² ] The polishing liquid: It becomes a solution containing a silica-based abrasive.

Thereafter, the conductor layer 13 which is to be patterned and becomes the wiring layer 7 is formed (FIG. 3A: conductor layer forming step). The conductor layer 13 is made of, for example, an Al-Cu film of 500
[Nm] A film is formed by a sputtering method.

After the formation of the conductor layer 13, a connection hole 17 in which a wiring connection portion 19 is formed is opened (FIG. 3B: connection hole forming step). The connection hole 17 can be formed by the following procedure. First, a first resist film 15 is applied on the conductor layer 13, and a connection hole pattern is formed by photolithography. Next, using this pattern as a mask, the conductive layer 13 and the insulating layer 5 are continuously etched until the conductive layer 3 is reached. By doing so, a continuous connection hole can be formed between the conductor layer 13 and the insulating layer 5. After the completion of the etching, the first resist film 15 is peeled off. Note that the connection hole includes a conductive portion called a contact hole, a via (via) hole, a through hole, and the like, and a hole formed for connecting conductors such as a wiring layer. So, for example,
When there is a first metal wiring to a third metal wiring, a wiring connecting the first metal wiring and the third metal wiring is also included.

After the resist is stripped, a wiring connection portion 19 is formed (FIG. 4A: wiring connection portion forming step). Wiring connection 1
9 is, for example, 500 [n] made of tungsten (W).
m] of a conductive film (not shown) is formed on the entire surface of the substrate 100 by a CVD method. Thereafter, the conductive film is polished and removed by the CMP method until the upper surface of the conductive layer 13 is exposed, and the wiring connection portion 19 is formed in a state of being buried in the connection hole 17. In this way, the formed W film is filled in the connection hole, and a columnar conductor portion penetrating through the wiring layer 7 and the insulating layer 5 and reaching the conductive portion 3 can be formed in the connection hole 17. This conductor portion becomes a columnar wiring connection portion 19 that contacts the conductive portion 3 on the bottom surface and contacts the wiring layer 7 on the upper side surface.

The CV when the conductive film is a W film
An example of the D condition and an example of the CMP condition are shown below. CVD condition: film forming gas and flow rate: WF ₆ / H ₂ / Ar = 75/500
/ 2000 [sccm] Atmospheric pressure: 80 [Torr] Substrate temperature: 450 [° C] CMP condition: Number of rotations of polishing plate: 20 [rpm] Number of rotations of substrate holding indicator: 20 [rpm] Polishing pressure: 450 [g] / Cm ² ] Polishing liquid: A solution containing an alumina-based abrasive and an oxidizing agent. In addition, using Al, Al alloy as the conductive film,
An etch-back method may be used as a planarization method.

After the formation of the wiring connection portion 19, the wiring layer 7 is formed (FIG. 4B: wiring layer forming step). The wiring layer 7
For example, a second resist film 21 is applied on the conductor layer 13,
Form wiring pattern by photolithography technology,
It is formed by anisotropic etching by RIE. An example of such etching conditions is as follows: Etching gas: BCl ₃ / Cl ₂ = 80/120 [sc]
cm] Atmospheric pressure: 1067 [mPa] RF power: 120 [W]. Further, it is preferable that the wiring connection portion 19 exposed from the second resist film 21 is hardly etched, so that the material has a high selectivity with respect to the material of the previously formed wiring connection portion.
After the etching is completed, the second resist film 21 is peeled off. In FIG. 4B, an alignment error occurs between the wiring layer mask and the wiring connection part, and the wiring layer 7 is formed on the left side of the wiring connection part 19.

Thereafter, an overcoat film 11 is formed on the entire surface of the semiconductor substrate (FIG. 4C).
Is formed by, for example, forming a silicon nitride (SiN) film over the entire surface of a semiconductor substrate by a CVD method.

Through the above steps, a semiconductor device according to the present invention can be manufactured. Thus, the insulating layer 5 and the conductor layer 13 are formed after the conductive portion forming step, and both these layers 5,
Since the conductor is buried in the connection hole formed by penetrating through the conductor 13 and reaching the conductive part 3 to form the wiring connection part 19, the wiring connection part 19 that contacts the conductive part 3 on the bottom surface and contacts the wiring layer 7 on the side surface. Can be formed. Therefore, electrical connection between the conductive portion 3 and the wiring connection portion 19 and between the wiring layer 7 and the wiring connection portion 19 can be established at these contact surfaces. Therefore, the conductive portion 3 and the wiring layer 7 can be electrically connected.

FIG. 5 is a plan view of the semiconductor device manufactured as described above, and the cross section taken along the line CC ′ corresponds to FIG. 4C. As shown in FIG. 5, the conductive portion 3 which is a lower wiring layer
Are connected to each other through a wiring connection portion 19 formed to penetrate the wiring layer 7 as the upper wiring layer.

In the above description of the manufacturing method, the conductive part 3
And the wiring layer 7 was formed by a sputtering method,
For example, a film may be formed by a vacuum evaporation method, which is another physical vapor deposition method, or a CVD method may be used. The planarization of the insulating layer 5 is performed by the CMP method, but may be performed by an etch back method using an SOG film or a resist. Further, the insulating layer 1 and the insulating layer 5 are formed by the CVD method, but are not limited thereto.

In the present embodiment, the case of two layers of the conductive part 3 and the wiring layer 7 has been described. However, in the case of a multilayer wiring of three or more layers, the conductive part forming step, the insulating layer forming step, the conductive layer The present invention can be applied by repeating a series of steps including a forming step, a connecting hole forming step, a wiring connecting part forming step, and a wiring layer forming step for an underlying insulating film.

(Third Embodiment) FIG. 6 is a sectional view showing an example of the structure of a semiconductor device according to the present invention.

As shown in FIG. 6, a diffusion layer 33 which is a conductive portion formed on the surface of a silicon semiconductor substrate (hereinafter, referred to as a substrate) 30 is formed to surround the diffusion layer 33 and to separate the layer 33. Insulation layer 31, diffusion layer 33 and insulation layer 35 formed on insulation layer 31, insulation layer 3
5, a diffusion layer 33 and a wiring layer 3 formed on
7 is connected to a wiring connection portion 4 buried in a connection hole continuously formed in the insulating layer 35 and the wiring layer 37.
9 is provided.

As described above, the wiring connection portion 49 is formed by the insulating layer 35.
Since it is formed in a column shape penetrating through the wiring layer 37, it is in contact with the diffusion layer 33 on the bottom surface and is in contact with the wiring layer 37 on the side surface. Therefore, the electrical connection between the diffusion layer 33 and the wiring layer 37 is made at these contact surfaces.

An outline of a method of manufacturing the semiconductor device shown in FIG. First, the Si substrate 30 is thermally oxidized to form an oxide film 31 by the LOCOS method. Next, the substrate 30 is self-aligned using the oxide film 31 as a mask by ion implantation.
The impurity is introduced into the surface layer to form the diffusion layer 33 as a conductive portion. Subsequently, a BPSG film is formed by a CVD method, and is further flattened by using an etch back method using an SOG film.
An insulating layer 35 is formed. After that, an Al—Cu film is formed by a sputtering method to form a conductor layer to be the wiring layer 37. Thereafter, the wiring connection portion 49 is formed in the same manner as in FIGS. In the present embodiment, the insulating film disposed between the conductive portion 33 and the wiring layer 37 is composed of two layers, the oxide film 31 and the insulating layer 35. The same material as that of the first embodiment can be used for the material of the wiring layer 37 and the material of the wiring connection part.

As described above, the conductive portion of the semiconductor device according to the present invention is not limited to a metal layer, but may be a diffusion layer or a silicide layer typified by a source / drain region formed on a substrate. Good. Also, as this application,
The present invention can be applied to a polysilicon layer, a polycide layer, and the like. That is, the connection hole includes a conductive portion such as a contact hole, a via (via) hole, and a through hole, and a hole that connects between conductors such as a wiring layer. Therefore, if the structure described in the first embodiment and the structure described in the third embodiment are combined, the present invention can be applied to a case where a conductive portion, a wiring layer, and the like of a semiconductor device are connected.

As described above, in the semiconductor device according to the present invention, these conductors are connected by bringing the side surface of the wiring connection portion into contact with the side surface of the wiring layer, so that the contact area between the two conductors can be increased as compared with the related art. In addition, the alignment error between the wiring layer forming mask and the wiring connection part increases, and even when the wiring connection part protrudes from the side surface of the wiring layer, these conductors are in contact with each side surface. Can be increased. Therefore, it is possible to suppress an increase in electric resistance and an increase in current density at the connection portion. In other words, even if an alignment error occurs, the above problem can be prevented, so that the alignment margin between the wiring connection portion and the wiring layer can be reduced.

[0047]

As described above in detail, in the semiconductor device and the method of manufacturing the same according to the present invention, the connection between the wiring layer and the wiring connection portion is performed by bringing the respective side surfaces into contact with each other. The contact area of the connecting portion can be made larger than that of the conventional structure, and damage due to plasma during processing can be reduced. In addition, these effects become more remarkable as miniaturization progresses as compared with the related art.

In addition, even if an error occurs in the alignment between the wiring connection portion and the wiring layer, the problem of the characteristic that the electric resistance of the connection portion increases and the problem of the reliability of the wiring due to the electro-migration phenomenon occur. Can be suppressed.

Further, even if a registration error occurs, the above problem can be suppressed, so that it is not necessary to secure a registration margin as compared with the related art. For this reason, the alignment margin between the wiring connection portion and the wiring layer can be reduced. Therefore, a fine semiconductor device with high electrical characteristics and high reliability can be provided.

[Brief description of the drawings]

1 (a) and 1 (b) are schematic views showing one embodiment of a semiconductor device according to the present invention, FIG. 1 (a) is a plan view, and FIG. 1 (b) is AA FIG.

FIGS. 2A and 2B are schematic views showing one embodiment of a semiconductor device according to the present invention, FIG. 2A is a plan view, and FIG. FIG.

FIGS. 3A and 3B are schematic cross-sectional views showing main steps for describing one embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIGS. 4A to 4C are schematic cross-sectional views showing main steps for explaining one embodiment of a method of manufacturing a semiconductor device according to the present invention.

FIG. 5 is a plan view corresponding to FIG. 4 (c).

FIG. 6 is a cross-sectional view schematically illustrating one embodiment of a semiconductor device according to the present invention.

7A and 7B are schematic views for explaining a conventional semiconductor device, FIG. 7A is a plan view, and FIG.
(B) is DD 'sectional drawing.

8A and 8B are schematic views for explaining a conventional semiconductor device, FIG. 8A is a plan view, and FIG.
(B) is EE 'sectional drawing.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Insulating layer, 3 ... Conducting part, 5 ... Insulating layer, 7 ... Wiring layer,
9, 19, 49: wiring connection portion, 11: overcoat film,
13: conductor layer, 15: first resist film, 17: connection hole,
21: second resist film, 30: silicon semiconductor substrate, 3
DESCRIPTION OF SYMBOLS 1 ... Oxide film, 33 ... Diffusion layer, 35 ... BPSG film, 37 ...
Wiring layer, 100: silicon semiconductor substrate

Claims (2)

[Claims] A connection hole is formed in an insulating layer on a semiconductor substrate, and a wiring connection portion made of a conductive material is provided in the connection hole, so that a wiring layer on the insulating layer and a lower side of the insulating layer are provided. In a semiconductor device in which a conductive portion is electrically connected, the wiring connection portion extends into the wiring layer and a side surface of the wiring connection portion is electrically connected to the wiring layer. apparatus. 2. A conductive part forming step of forming a conductive part on a semiconductor base; an insulating layer forming step of forming an insulating layer on the semiconductor base after forming the conductive part; and forming a conductive layer on the insulating layer. A conductive layer forming step of forming; a connecting hole forming step of reaching the conductive portion to form a connecting hole in the insulating layer and the conductive layer; and embedding a conductive material in the connecting hole to form the conductive portion and the conductor. A method for manufacturing a semiconductor device, comprising: a wiring connection portion forming step of forming a wiring connection portion connecting to a layer; and a wiring layer forming step of forming a wiring layer by patterning the conductor layer.