JPH10189711A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make element size small without impairing element isolation function, by a method wherein a pattern is formed over the element activated region, wherein impurity diffusion layer close to the first conductive film is formed, and the first and the second conductive films, which are capacitive coupled with lower layer of the impurity diffusion layer, are integrally formed. SOLUTION: A side electrode 6 is formed on an element active region, where an impurity diffusion layer 4 is formed through a gate oxide film 8, and an electrode film is capacitive coupled with the impurity diffusion layer 5. The electrode film is formed on a silicon semiconductor substrate 1 through the gate oxide film 8. The gate electrode 4, which is formed by patterning in such a manner that it is formed in the vicinity of the boundary part of a field shield element isolation structure 2 and the element active region, is integrally formed with the side electrode 7, which is formed by patterning in the vicinity of the boundary part of the field shield element isolation structure 2 and the element active region. As a result, element isolation can be accurately accomplished by a shield plate electrode 22, and the breakdown strength of an MOS transistor can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a field shield element isolation structure in which an electrode film is buried in an insulating film as an element isolation structure for defining an element active region. And a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, as semiconductor devices have become larger and more highly integrated, the size of element formation regions has been reduced. As one of the element isolation techniques in a semiconductor element corresponding to this, a so-called field shield element isolation method has attracted attention. This element isolation method is a technique of forming a field shield element isolation structure in an element isolation region on a silicon semiconductor substrate to define an element active region.
The field shield element isolation structure is an element isolation structure in which a shield plate electrode, which is a conductive film made of polycrystalline silicon or the like, is buried in an insulating film made of SiO ₂ or the like. Alternatively, the element can be reliably separated by fixing it to another predetermined potential.

[0003] In addition, the demand for reducing the size of the element formation region imposes restrictions on the layout of various metal wirings. In this case, for example, as the size of the memory cell is reduced, the thickness of the source / drain diffusion layer is reduced, or the area where the contact hole can be arranged with respect to the source / drain diffusion layer is limited. The electric resistance of the drain diffusion layer is increased, and the MOS
The increase in the speed of the logic operation of the transistor is hindered.

Here, when the electrical resistance of the drain diffusion layer increases, the output resistance of the logic circuit increases, and the current does not decrease so much. However, a so-called RC determined by the product of the output resistance and the load capacitance is used. The delay increases. In addition, when the electric resistance of the source diffusion layer increases, the substantial transconductance decreases, the current decreases, and the load driving capability decreases. Therefore, it is necessary to reduce the electric resistance value of the source / drain diffusion layers in order to increase the logic operation speed by suppressing the delay of the signal propagation time.

More specifically, as a method for reducing the electric resistance of the source / drain diffusion layers, for example, Japanese Patent Laid-Open No.
No. 5309 discloses that in a gate array type semiconductor integrated circuit, power supply lines are arranged so that the number of contacts in source / drain regions can be sufficiently secured.

That is, in Japanese Patent Application Laid-Open No. 5-235309, the first power supply line of the first wiring layer, which is arranged across a plurality of regularly arranged basic cells composed of MOS transistors, is removed. Power is supplied to the block from a second power supply line disposed in the second wiring layer by a power supply wiring provided in the first wiring layer via a through hole. Therefore, the power supply wiring to the functional block composed of the basic cells is not restricted by the first power supply line, and even if the functional block is formed between the first power supply lines, the contact of the source / drain region is not required. Many can be provided, and reduction of the resistance value of the source / drain region is realized.

Japanese Patent Application Laid-Open No. 4-237165 discloses that a silicide layer is formed by depositing a high melting point metal layer made of Mo, W or the like on a part of the surface of a source / drain region and performing heat treatment. Is disclosed. In this case, the silicide layer significantly reduces the resistance value of the source / drain region and suppresses signal propagation delay.

[0008]

By the way, recently,
Semiconductor devices typified by MOS transistors have been further shrinking, and the following problems have arisen, for example, when forming gate electrodes of MOS transistors.

In forming a gate electrode of a MOS transistor or the like, an electrode-shaped photoresist is applied on a polycrystalline silicon film deposited and formed on a silicon semiconductor substrate in a photolithography step in forming the gate electrode. The photoresist is exposed using a photomask on which a predetermined pattern is formed. Here, as the element size is reduced, the separation distance between the gate electrode formed in the element active region and the adjacent element isolation structure also becomes smaller, so that the reflected light from the step portion with respect to the element active region of the element isolation structure becomes smaller. It cannot be ignored. That is, a part that should be an unexposed part that is originally shielded from light by the pattern of the photoresist photomask, for example, the side part of the photoresist is exposed by the reflected light, and the side part of the completed resist mask is thinned, The resist mask becomes different from the original design dimensions.

When a gate electrode is formed by etching a polycrystalline silicon film using this resist mask, the formed gate electrode also has a constricted shape in accordance with the shape of the resist mask, which increases the sub-threshold current of the transistor and increases the standby state. Inconveniences such as an increase in leak current are caused.

This tendency is remarkable when a single wavelength light such as a g-line or an i-line, which is generally used recently, is used as a light source, and when the thickness is severe, it is about 0.1 μm to 0.15 μm on one side.
m, and as the gate electrode width approaches the size of 0.5 μm, it is being increasingly viewed as a problem.

Therefore, as disclosed in, for example, JP-A-6-342905 and JP-A-7-297379, a field oxide film having an element isolation structure formed by a LOCOS method when forming a gate electrode is used. There is a method of forming an electrode also at a boundary portion between a source diffusion layer and a drain diffusion layer (in JP-A-7-297379, only the drain diffusion layer). According to this method, in the photolithography process at the time of forming the gate electrode, it is possible to prevent the gate electrode from being constricted by light reflected on the bird's beak surface.

However, when the above-described method is applied to a semiconductor device having a field shield element isolation structure as an element isolation structure, the potential applied to the electrode formed at the boundary is determined by the field isolation element isolation structure. Function may be impaired. In addition, for example, in the case where a plurality of gate electrodes are formed, it is necessary to consider how to arrange adjacent gate electrodes, and it is necessary to take measures to efficiently suppress the occurrence of the constriction corresponding to various layouts. No.

Japanese Patent Publication No. 6-105772 discloses that an upper electrode of a capacitor extends from a field oxide film adjacent to a gate electrode to an n-type diffusion region via a silicon oxide film so as to be adjacent to the gate electrode. A DRAM provided is disclosed. However, in this case,
The upper electrode needs to be formed in an island-shaped independent shape, and is not formed so as to cover the entire field oxide film adjacent to the gate electrode. Further, in this case, since the gate electrode is formed after forming the n-type diffusion region and the upper electrode, it is considered that the upper electrode hardly contributes to prevention of thinning at the time of forming the gate electrode.

In Japanese Patent Application Laid-Open No. 3-257861, a gate electrode is formed in a substantially U shape so as to extend from an element region to a field region, and a source region is formed inside the gate electrode and a drain region is formed outside the gate region. A disclosed MOSFET is disclosed. However, even in this case, it is difficult to prevent the thinning at the time of forming the gate electrode because there is a part where the gate electrode and the field region are closely adjacent to each other.

Japanese Unexamined Patent Publication (Kokai) No. 6-177328 discloses a MISFET having a wiring material connected to a gate electrode on an end of a field region in contact with a drain diffusion layer. However, even in this case, since there is no wiring material on the end of the field region in contact with the source diffusion layer, it is difficult to prevent thinning when forming the gate electrode.

Further, when comparing the increase in the signal propagation delay time caused by the increase in the electric resistance value of the source diffusion layer with the increase in the signal propagation delay time caused by the increase in the electric resistance value of the drain diffusion layer, The source diffusion layer having a lower value has a greater effect. Therefore, it is important to reduce the electrical resistance of the source diffusion layer in preference to reducing the electrical resistance of the drain diffusion layer.

However, reducing the electric resistance of the source diffusion layer causes a problem that the noise margin is reduced and the malfunction of the sense amplifier is likely to occur. That is, as described above, there is a method suitable for reducing the electric resistance value of the source diffusion layer (and the drain diffusion layer) to suppress the delay of signal propagation, but it causes a serious problem of lowering a noise margin. Becomes Further, in a substantial part of the semiconductor device, there is a method of reducing the absolute value of the threshold voltage in order to obtain a large driving current, which is generally adopted. Can not be suppressed.

Therefore, an object of the present invention is to form a plurality of gate electrodes without impairing the element isolation function when a field shield element isolation structure that does not cause inconvenience such as bird's beak is used as the element isolation structure. An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can achieve the miniaturization of the gate electrode accompanying the reduction in the element size without causing an abnormal shape of the gate electrode.

Still another object of the present invention is to provide a semiconductor device capable of performing a high-speed operation while ensuring a sufficient noise margin, and a method of manufacturing the same.

[0021]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor device comprising: a transistor having a gate electrode in a device active region defined by a device isolation structure on a semiconductor substrate; and a pair of impurity diffusion layers functioning as a source / drain on both sides of the gate electrode. A first conductive film patterned on the device active region in a band shape with a gate insulating film interposed therebetween and functioning as the gate electrode; and a first conductive film of a boundary portion between the device isolation structure and the device active region. A strip-shaped pattern is formed so as to cover at least the element active region in which the impurity diffusion layer is formed at a portion opposed to and close to the conductive film, and the lower impurity diffusion layer is interposed via the gate insulating film. And a second conductive film that is capacitively coupled in opposition to the first conductive film, wherein the first conductive film and the second conductive film are integrally formed.

In one embodiment of the semiconductor device according to the present invention, the element isolation structure is a field shield element isolation structure in which a shield plate electrode is embedded in an insulating film.

In one embodiment of the semiconductor device of the present invention, the potential of the shield plate electrode and the potential of the conductive film are set to different values.

In one embodiment of the semiconductor device according to the present invention, the element isolation structure is a trench-type element isolation structure in which an insulating film is embedded in a groove formed in the semiconductor substrate.

In one embodiment of the semiconductor device of the present invention, the first and second conductive films are connected at one end thereof.

In one embodiment of the semiconductor device of the present invention, the first and second conductive films have a two-layer conductive film structure.

The semiconductor device according to the present invention is a semiconductor device having an element isolation structure for defining an element active region on a semiconductor substrate, wherein at least one strip-shaped conductive film is provided on the element active region via an insulating film. Is patterned, and at least a portion of the boundary between the element isolation structure and the element active region, which is a portion opposed to and close to the conductive film formed in the element active region, on the element active region. Another conductive film is formed so as to cover with the insulating film interposed therebetween.

In one embodiment of the semiconductor device of the present invention, the conductive film formed in the element active region and the conductive film formed in the boundary portion are electrically connected at one end thereof. And both are set to the same potential.

In one embodiment of the semiconductor device according to the present invention, the element isolation structure is a field shield element isolation structure in which a shield plate electrode is embedded in an insulating layer.

In one embodiment of the semiconductor device of the present invention, the element isolation structure is a trench-type element isolation structure in which an insulating film is buried in a groove formed in the semiconductor substrate.

In one embodiment of the semiconductor device of the present invention, the potential of the shield plate electrode and the potential of the conductive film formed at the boundary are set to different values.

In one embodiment of the semiconductor device of the present invention, the second conductive film formed in the element active region is a gate electrode of a transistor, and a surface region of the semiconductor substrate on both sides of the gate electrode. A source diffusion layer and a drain diffusion layer, wherein the source diffusion layer is formed in the surface region of the semiconductor substrate in the element active region where the boundary region exists, and is located at the boundary region connected to the gate electrode. At least a part of the conductive film faces the source diffusion layer via the insulating film and is capacitively coupled to each other, so that the source diffusion layer and the drain diffusion layer have the same potential.

In one embodiment of the semiconductor device according to the present invention, two conductive films are formed in the element active region with the insulating film interposed therebetween, and one of the conductive films is formed of the conductive film. A film and the conductive film formed at the boundary portion adjacent to the film are connected,
The other conductive film is connected to the conductive film formed at the boundary portion adjacent to the other conductive film.

In one embodiment of the semiconductor device of the present invention, the semiconductor device has a pair of impurity diffusion layers in which impurities are introduced into a surface region of the semiconductor substrate on both sides of the conductive film formed in the element active region. At least one of the impurity diffusion layers is formed in a surface region of the semiconductor substrate between the conductive film and the conductive film formed at the boundary portion adjacent to the conductive film.

In one embodiment of the semiconductor device of the present invention, the conductive film has a two-layer structure.

In a method of manufacturing a semiconductor device according to the present invention, a field shield element isolation structure in which a first conductive film is buried in a first insulating film is formed in an element isolation region on a semiconductor substrate. First defining the device active area on top
And a second step of forming a second insulating film in the element active region; and a third step of forming a second conductive film on the field shield element isolation structure and on the second insulating film.
And patterning the second conductive film and the second insulating film to form a pattern on at least the device active region on the device active region and at a boundary portion between the device active region and the field shield device isolation structure. Processing the second conductive film and the second insulating film into a band-shaped pattern;
Forming each pattern such that another pattern of the second conductive film extends in the vicinity of the pattern of the second conductive film formed on the element active region along the longitudinal direction;
And the step of

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the potential of the first conductive film and the potential of the second conductive film at the boundary are set to different values.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the fourth step, a pattern of the second conductive film formed on the element active region, A pattern of the second conductive film formed at least in the element active region of the adjacent boundary portion is integrally formed at one end thereof, and both are set to the same potential.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the second conductive film formed in the element active region is used as a gate electrode of a transistor, and the gate electrode is formed after the fourth step. Forming a source diffusion layer and a drain diffusion layer in a surface region of the semiconductor substrate on both sides of the semiconductor substrate, wherein the source diffusion layer is formed in a surface region of the semiconductor substrate in the element active region where the boundary region exists. Forming at least a part of the second conductive film at the boundary portion connected to the gate electrode to face the source diffusion layer with the second insulating film interposed therebetween; The diffusion layer and the drain diffusion layer have the same potential.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the fourth step, two patterns of the second conductive film with the second insulating film interposed therebetween are formed in the element active region. At the same time, the pattern of each of the second conductive films and the pattern of the second conductive film at the boundary portion adjacent thereto are integrally formed.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the third step, the second conductive film, the third insulating film, and the third conductive film are formed on the second insulating film. Films are sequentially formed, and in the fourth step, the third conductive film, the third insulating film, the second conductive film, and the second insulating film are patterned.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the fourth step, the patterns of the second and third conductive films formed on the element active region, and the second and third conductive films are formed. A third conductive film and a pattern of the second and third conductive films formed at least in the element active region at the boundary portion adjacent to the third conductive film are integrally formed, and both are set to the same potential.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the fourth step, two patterns of the second and third conductive films are formed in the element active region, The pattern of the second and third conductive films and the pattern of the second and third conductive films at the boundary portion adjacent thereto are integrally formed.

In the method of manufacturing a semiconductor device according to the present invention, after forming a groove in an element isolation region on a semiconductor substrate, a first insulating film is buried in the groove to form a trench-type element isolation structure. A first step of defining an element active region on the substrate, a second step of forming a second insulating film in the element active region, and a step of forming a second insulating film on the trench type element isolation structure and the second insulating film. A third step of forming a conductive film, and patterning the conductive film and the second insulating film to form at least the element active region and at least the boundary region between the element active region and the trench-type element isolation structure. A fourth step of processing the conductive film and the second insulating film into a band-shaped pattern in an element active region, and a pair of impurity diffusion in a surface region of the semiconductor substrate on both sides of the conductive film on the element active region. Form a layer , Having a fifth step of facing and at least a portion between the impurity diffusion layers of the conductive layer existing in the boundary portion via the second insulating film.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the fourth step, the pattern of the conductive film formed on the element active region and the boundary portion adjacent to the conductive film are formed. At least one end of the conductive film pattern formed in the element active region is integrally formed with the conductive film pattern, and both are set to the same potential.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the conductive film formed in the element active region is used as a gate electrode of a transistor, and a source diffusion layer which is one of the pair of impurity diffusion layers is formed. The device is formed in the surface region of the semiconductor substrate in the element active region where the boundary portion exists, and at least a part of the conductive film at the boundary portion connected to the gate electrode is connected to the source through the second insulating film. The two are capacitively coupled to face the diffusion layer, and the source diffusion layer and the drain diffusion layer, which is the other of the pair of impurity diffusion layers, have the same potential.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the fourth step, two patterns of the conductive film are formed in the element active region via the second insulating film. Forming a pattern of each of the conductive films and a pattern of the conductive film at the boundary portion close to the conductive film.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the third step, the conductive film, the third insulating film, and the upper conductive film are sequentially formed on the second insulating film. In the fourth step, the upper conductive film, the third insulating film, the conductive film, and the second insulating film are patterned.

In one embodiment of the method for manufacturing a semiconductor device according to the present invention, in the fourth step, the upper conductive film and the pattern of the conductive film to be formed on the element active region; The conductive film and the pattern of the second and third conductive films formed in at least the element active region at the boundary portion close to the conductive film are integrally formed, and both are set to the same potential.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the fourth step, two patterns of the upper conductive film and the conductive film are formed in the element active region, and each of the patterns is formed. The upper conductive film and the pattern of the conductive film and the pattern of the upper conductive film and the pattern of the conductive film at the boundary portion adjacent thereto are integrally formed.

A semiconductor device according to the present invention is a semiconductor device having an element isolation structure for defining an element active region on a semiconductor substrate, comprising: a first insulating film formed in the element active region; An impurity diffusion layer formed on the semiconductor substrate in a boundary region between a structure and the element active region;
A first conductive film formed on the first insulating film, wherein the first conductive film and the impurity diffusion layer are opposed to each other via the first insulating film in the boundary region. Have been.

In one embodiment of the semiconductor device of the present invention, the element isolation structure is a field shield element isolation structure in which a shield plate electrode is embedded in a second insulating film.

In one embodiment of the semiconductor device according to the present invention, the first conductive film is formed on at least a part of a boundary region between the element isolation structure and the element active region on the second insulating film and on the second insulating film. It is formed on one insulating film.

In one embodiment of the semiconductor device of the present invention, the element active region further includes a second conductive film formed on the first insulating film, and both sides of the second conductive film. A source diffusion layer and a drain diffusion layer formed on the semiconductor substrate, the second conductive film is connected to the first conductive film, and the first conductive film is connected to the source diffusion layer. It is formed in the boundary area on the layer side.

In one embodiment of the semiconductor device of the present invention, the source diffusion layer and the drain diffusion layer are in contact in the semiconductor substrate.

In one embodiment of the semiconductor device of the present invention, the element isolation structure is a trench type element isolation structure in which a third insulating film is embedded in a groove formed in an element isolation region of the semiconductor substrate. It is.

In one embodiment of the semiconductor device of the present invention, the first conductive film is formed on at least a part of the third insulating film in a boundary region between the element isolation structure and the element active region and the first conductive film. It is formed on one insulating film.

In one embodiment of the semiconductor device of the present invention, the element active region further includes a second conductive film formed on the first insulating film, and both sides of the second conductive film. A source diffusion layer and a drain diffusion layer formed on the semiconductor substrate, the second conductive film is connected to the first conductive film, and the first conductive film is connected to the source diffusion layer. It is formed in the boundary area on the layer side.

A semiconductor device according to the present invention includes a conductive layer provided on a surface of the semiconductor substrate in an element active region defined on the semiconductor substrate via an insulating layer, and provided on the semiconductor substrate on both sides of the conductive layer. A source diffusion layer and a drain diffusion layer, which are a pair of impurity diffusion layers, a first wiring layer electrically connected to the source diffusion layer, and a second wiring capacitively coupled to the first wiring layer. And a layer.

In one embodiment of the semiconductor device of the present invention, the second wiring layer is a power supply wiring layer or a ground wiring layer.

In one embodiment of the semiconductor device according to the present invention, the semiconductor device includes a lower electrode layer electrically connected to the drain diffusion layer, and an upper electrode layer capacitively coupled to the lower electrode layer.

In one embodiment of the semiconductor device according to the present invention, the first wiring layer extends over an element isolation structure defining the element active region, and the first wiring layer and the second wiring layer are connected to each other.
Are disposed on the element isolation structure with an insulating layer interposed therebetween.

In one embodiment of the semiconductor device of the present invention, the element isolation structure is a field shield element isolation structure having a shield plate electrode.

In one embodiment of the semiconductor device according to the present invention, the element isolation structure is a field oxide film formed by a LOCOS method.

In one embodiment of the semiconductor device of the present invention, the element isolation structure is a trench type element isolation structure in which an insulating film is buried in a groove formed in an element isolation region on the semiconductor substrate. .

A semiconductor device according to the present invention includes a field shield element isolation structure having a shield plate electrode formed on a semiconductor substrate, and an element active region defined by being surrounded by the field shield element isolation structure. A conductive layer provided on the surface of the semiconductor substrate via an insulating layer, a pair of impurity diffusion layers provided on the semiconductor substrate on both sides of the conductive layer, and electrically connected to one of the pair of impurity diffusion layers. And a wiring layer capacitively coupled to the shield plate electrode.

A method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming an element isolation structure in an element isolation region on a semiconductor substrate; and forming a first element on a surface of the semiconductor substrate in an element active region surrounded by the element isolation structure. Forming an insulating layer of
Forming a conductive layer of a predetermined pattern on the first insulating layer; and forming a pair of impurity diffusion layers by introducing impurities into the semiconductor substrate on both sides of the conductive layer using the conductive layer as a mask. Forming a recess by anisotropically etching the semiconductor substrate in a region where at least one of the pair of impurity diffusion layers is present, and leaving a part of the one impurity diffusion layer only on a side wall surface of the recess. A step of forming a second insulating layer only on the bottom surface of the concave portion; and depositing a semiconductor material in the concave portion to form a part of the one impurity diffusion layer existing only on the side wall surface of the concave portion. Embedding a second insulating layer.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the pair of impurity diffusion layers are a source diffusion layer and a drain diffusion layer of a transistor having the conductive layer as a gate electrode, and the source diffusion layer is formed in the source diffusion layer. A second insulating layer is buried.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the element isolation structure is a field shield element isolation structure having a shield plate electrode.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the element isolation structure is a field oxide film formed by a LOCOS method.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the element isolation structure is a trench type element isolation in which an insulating film is buried in a groove formed in an element isolation region on the semiconductor substrate. Structure.

A semiconductor device according to the present invention is characterized in that an element active region defined by an element isolation structure on a semiconductor substrate and a first region formed on the semiconductor substrate at a boundary region between the element isolation structure and the element active region. An impurity diffusion layer; a first insulating film formed on the first impurity diffusion layer in the boundary region; and a second insulating film formed on the first insulating film, and the first insulating film interposed therebetween. A first electrode formed to face the first impurity diffusion layer, a second insulating film formed on the element active region of the semiconductor substrate, and a second electrode formed on the second insulating film. A second electrode, and a pair of second impurity diffusion layers formed on the semiconductor substrate on both sides of the second electrode, wherein one of the pair of second impurity diffusion layers is Connected to the first impurity diffusion layer in the semiconductor substrate, First electrode and the second electrode are connected.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the element isolation structure is a field shield element isolation structure in which a shield plate electrode is embedded in an insulating film.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the element isolation structure is a trench-type element isolation structure in which an insulating film is embedded in a groove formed in the semiconductor substrate.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the potential of the shield plate electrode and the potential of the first electrode are set to different values.

According to a method of manufacturing a semiconductor device of the present invention, a field shield element isolation structure in which a first conductive film is embedded in a first insulating film is formed in an element isolation region on a semiconductor substrate. First defining the device active area on top
And a second step of forming a second insulating film in the element active region; and forming a second conductive film and a low etching rate on the field shield element isolation structure and the second insulating film. A third step of sequentially forming the third insulating film;
Patterning the third insulating film, the second conductive film, and the second insulating film to form at least the device on the device active region and at a boundary portion between the device active region and the field shield device isolation structure; The third insulating film, the second conductive film, and the second insulating film are processed into a band-like pattern in an active region, and a longitudinal direction of a pattern of the second conductive film formed on the element active region is formed. A fourth step of forming each pattern so that another pattern of the second conductive film extends in the vicinity of the second conductive film, and a fourth step having a low etching rate on at least a side surface of the second conductive film. And a fifth step of forming an insulating film.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the second conductive film formed in the element active region is used as a gate electrode of a transistor, and after the fifth step, the gate electrode is formed. A sixth step of forming a source diffusion layer and a drain diffusion layer in surface regions of the semiconductor substrate on both sides of the third insulating film, the third insulating film, the second conductive film, the second insulating film, and the fourth Further comprising: a seventh step of forming an interlayer insulating film so as to cover the insulating film; and an eighth step of forming a contact hole communicating with the source diffusion layer and / or the drain diffusion layer in the interlayer insulating film. .

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, in the eighth step, the third insulating film and / or the fourth insulating film is partially exposed so as to be partially exposed. A contact hole is formed.

In one embodiment of the method of manufacturing a semiconductor device according to the present invention, the source diffusion layer is formed in a surface region of the semiconductor substrate in the element active region where the boundary region exists, and is connected to the gate electrode. At least a portion of the second conductive film at the boundary portion is opposed to the source diffusion layer via the second insulating film to capacitively couple the two,
The source diffusion layer and the drain diffusion layer have the same potential.

[0080]

In the semiconductor device of the present invention, for example, at least one strip-shaped conductive film functioning as a gate electrode is provided in the element active region, and at least a part of the boundary between the element isolation structure and the element active region. Also, a band-shaped conductive film is formed via a second insulating film (gate insulating film). When attention is paid to one conductive film (gate electrode) formed in the element active region, the semiconductor device exists near the conductive film in a boundary portion between the element isolation structure and the element active region. Further, another conductive film is configured to extend at least in the element active region at a boundary portion along the longitudinal direction of the conductive film. Here, when there are a plurality of conductive films serving as gate electrodes, the other conductive films may be gate electrodes.

When a conductive film (gate electrode) is formed in the element active region, the reflected light from the step portion of the element isolation structure adversely affects the formation of the gate electrode in the photolithography step, but has a direct adverse effect. The light is emitted from a step located at a boundary portion between the gate electrode and the element isolation structure along the longitudinal direction. Therefore, if the above-mentioned second conductive film is formed such that the photoresist pattern also exists at this boundary portion, an element isolation structure having a high step portion such as a field shield element isolation structure can be obtained. Also in a semiconductor device, a gate electrode can be efficiently formed into a desired shape without thinning or constriction.

Further, in the semiconductor device of the present invention, the first wiring layer electrically connected to the source diffusion layer of the pair of impurity diffusion layers, and the second wiring layer capacitively coupled to the first wiring layer. With this wiring layer, a capacitor having a large facing area and thus a large load capacitance is formed.

Here, even when the resistance value of the source diffusion layer is relatively high, since the capacitance of the capacitor is large, the large electric capacitance governs the impedance between the semiconductor substrate portion and the source diffusion layer. However, when viewed from a DC point of view, despite the presence of a large electric resistance of the source diffusion layer, when an AC current flows, a voltage drop due to the electric resistance of the source diffusion layer does not occur and the load capacitance is reduced. Discharge is performed in a short time. That is, according to the method of manufacturing a semiconductor device of the present invention, a sufficient noise margin is ensured because the electric resistance value of the source diffusion layer is relatively large, and a delay in signal propagation time is suppressed, so that a logic operation is suppressed. Higher speed is realized.

In the method for manufacturing a semiconductor device according to the present invention, the second insulating layer is formed so as to be embedded in the bottom of the impurity diffusion layer, and the impurity diffusion layer and the second insulating layer are formed. And a semiconductor substrate through which a capacitor having a large electric capacitance is formed.

Here, even when the resistance value of the impurity diffusion layer is relatively high, since the electric capacity of the capacitor is large, this large electric capacity controls the impedance between the semiconductor substrate portion and the impurity diffusion layer. However, when viewed from a DC point of view, despite the presence of a large electric resistance of the impurity diffusion layer, a voltage drop due to the electric resistance of the impurity diffusion layer does not occur when an AC current flows. Discharge is performed in a short time. That is, according to the semiconductor device of the present invention, a sufficient noise margin is secured because the electric resistance value of the impurity diffusion layer is relatively large, and a delay in signal propagation time is suppressed, thereby realizing high-speed logic operation. Is done.

[0086]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Some preferred embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to the drawings.

(First Embodiment) First, a first embodiment of the present invention will be described. In the first embodiment, a MOS transistor having a gate electrode and a source / drain diffusion layer will be exemplified as a semiconductor device. FIG.
FIG. 2 is a schematic plan view of the MOS transistor according to the first embodiment, and FIG. 2 is a schematic sectional view taken along a broken line AA ′ in FIG. In FIG. 1, illustration of various insulating films covering each electrode film described later is omitted.

This MOS transistor is a cascade-connected two-input device having two gate electrodes in an element active region, and is formed in an element isolation region on a p-type silicon semiconductor substrate 1 to define an element active region. Field shield element isolation structure 2 and a substantially U-shaped electrode film 11 partially including the gate electrode 3 existing in the element active region.
And a substantially inverted U-shaped electrode film 12 partially including the gate electrode 4 existing adjacent to the gate electrode 3 in the element active region.
And impurity diffusion layers 5 formed in the surface region of the silicon semiconductor substrate 1 on both sides of (part of) the gate electrode 3 and the gate electrode 4.

The field shield element isolation structure 2 is formed so as to surround an element active region as shown in FIG. 1, and as shown in FIG.
An element isolation structure in which a shield plate electrode 22 made of a polycrystalline silicon film is buried and formed in c, and a silicon oxide film 21a below the shield plate electrode 22 functions as a gate insulating film. By fixing the potential of the shield plate electrode 22, each element active region is electrically separated from other element active regions.

The impurity diffusion layer 5 is formed by ion-implanting n-type impurities into the surface region of the silicon semiconductor substrate 1 in the element active region surrounded by the field shield element isolation structure 2 using the electrode films 11 and 12 as a mask. One is a source diffusion layer, the other is a drain diffusion layer, and the surface region of the silicon semiconductor substrate 1 immediately below the gate electrodes 3 and 4 sandwiched between the adjacent impurity diffusion layers 5 is the channel of the gate electrodes 3 and 4, respectively. Department. However, the gate electrode 4 is
One part near the tip is located near the boundary between the field shield element isolation structure 2 and the element active region,
No channel portion is formed in this portion.

The electrode film 11 is a polycrystalline silicon film formed in a substantially U shape on the silicon semiconductor substrate 1 with the gate oxide film 8 interposed therebetween. A gate electrode 3 extending over the field shield element isolation structure 2 and the element active region at the boundary between the field shield element isolation structure 2 and the element active area.
And a side electrode 6 pattern-formed along the longitudinal direction is integrally formed at one end thereof. Book first
In the embodiment, the side electrode 6 is formed via the gate oxide film 8 above the element active region in which the impurity diffusion layer 5 serving as the source diffusion layer is formed, that is, the side electrode 6 is connected to the source diffusion layer. The electrode film 11 is opposed to the impurity diffusion layer 5 with the gate oxide film 8 interposed therebetween, and the electrode film 11 is formed by the side electrode 6 with the gate oxide film 8 as a dielectric film and the impurity diffusion layer 5 serving as a source diffusion layer. Are combined.

The electrode film 11 is formed such that side wall insulating films 13 are formed on both side surfaces thereof and a cap insulating film 14 is formed thereon, and these are covered with these insulating films. A potential different from the potential (for example, 0 (V)) applied to the shield plate electrode 22 of the field shield element isolation structure 2 is applied to the electrode film 11, and the potential of the side electrode 6 is increased as described above. Since the portion is capacitively coupled to the impurity diffusion layer 5 serving as a source diffusion layer, the impurity diffusion layer 5 serving as a source diffusion layer and the impurity diffusion layer 5 serving as a drain diffusion layer have completely the same potential.

The electrode film 12 is a polycrystalline silicon film formed in a substantially inverted U-shape on the silicon semiconductor substrate 1 with the gate oxide film 8 interposed therebetween. A gate electrode 4 patterned in a strip shape so as to cover the vicinity of the boundary between the isolation structure 2 and the element active region; and the gate electrode 4 in the longitudinal direction of the gate electrode 4 near the boundary between the field shield device isolation structure 2 and the element active region. Along with the side electrodes 7 pattern-formed along one end, each is integrally formed at one end. The electrode film 12 has a sidewall insulating film 13 formed on both side surfaces thereof and a cap insulating film 14 formed thereon, and is covered with these insulating films. Here, the electrode film 11
Similarly, the side electrode 7 has a gate oxide film 8 on the element active region where the impurity diffusion layer 5 serving as a source diffusion layer is formed.
In other words, the side electrode 7 is opposed to the impurity diffusion layer 5 serving as a source diffusion layer via the gate oxide film 8, and the electrode film 12 is formed by the side electrode 7 at the gate oxide film 8. Is capacitively coupled to the impurity diffusion layer 5 serving as a source diffusion layer as a dielectric film.

Then, like the electrode film 11, the potential (for example, 0 V) applied to the shield plate electrode 22 of the field shield element isolation structure 2 is applied to the electrode film 12.
(V), a potential different from that of (V) is applied, and the portion of the side electrode 7 is capacitively coupled with the impurity diffusion layer 5 serving as a source diffusion layer, thereby forming the impurity diffusion layer 5 serving as a source diffusion layer and the drain diffusion layer. The potential of the impurity diffusion layer 5 is completely the same as that of the impurity diffusion layer 5.

Then, an interlayer insulating film 15 is formed on the entire surface including the field shield element isolation structure 2 and the electrode films 11 and 12, and the interlayer insulating film 15 is formed between the gate electrode 3 and the side electrode 6. Each contact hole 16 for exposing a part of each surface of the impurity diffusion layer 5 formed and the impurity diffusion layer 5 formed between the gate electrode 4 and the side electrode 7 is formed.

Further, a wiring layer 17 made of an aluminum alloy film is formed on the interlayer insulating film 15 including the inside of each contact hole 16 by patterning.
Are electrically connected to the impurity diffusion layer 5 through the MOS transistor to form a MOS transistor.

According to the MOS transistor according to the first embodiment, when attention is paid to one gate electrode formed in the element active region, this MOS transistor is included in the boundary between the field shield element isolation structure 2 and the element active region. Another gate electrode or side electrode is configured to extend at least in the element active region near the gate electrode and at a boundary portion along the longitudinal direction of the gate electrode. Specifically,
Focusing on the gate electrode 3, the side electrode 6 extends at a boundary portion with the field shield element isolation structure 2 in the longitudinal direction in the vicinity of the right side of the gate electrode 3 in FIG. A part of the gate electrode 4 (near the front end part) extends to the boundary part. Also, focusing on the gate electrode 4, the boundary portion, that is, the field shield element isolation structure 2 does not exist on the right side of the gate electrode 4 in FIG. Extends.

Therefore, as described later, the gate electrodes 3 and
In the photolithography process for forming 4,
The gate electrodes 3 and 4 are not adversely affected by halation. Even if the width of the gate electrodes 3 and 4 is on the order of 0.5 μm, the gate electrodes 3 and 4 are formed in a desired shape without constriction or the like. Have been.

Further, since the gate electrode 3 is formed integrally with the side electrode 6 and the gate electrode 4 is formed integrally with the side electrode 7 to form the electrode films 11 and 12, the gate electrode 3, the side electrode 6 and the gate electrode are formed. The electrode 4 and the side electrode 7 have the same potential. Further, since a potential different from the potential applied to the shield plate electrode 22 of the field shield element isolation structure 2 is applied to the electrode films 11 and 12, reliable element isolation by the shield plate electrode 22 is realized, and MOS The withstand voltage of the transistor can be improved.

As shown in FIG. 3, for example, between the gate electrodes 3 and 4, between the gate electrode 3 and the side electrode 6, and between the gate electrode 4 and the side electrode 7, a side wall insulating film 13 and a cap insulating film 14 are formed. Through each pad polycrystalline silicon film 2 such that each is electrically connected to the lower impurity diffusion layer 5.
3 may be patterned to relax the aspect ratio of the contact hole 16.

Further, in the MOS transistor, for example, in the transistor portion having the gate electrode 3 of the electrode film 11, the source diffusion layer and the drain diffusion layer can be made completely at the same potential. It is possible to apply.

For example, as shown in FIG. 4A, a transistor portion having an electrode film 11 can be applied to a bootstrap circuit. This bootstrap circuit
As shown in FIG. 4B, a MOS transistor M including a gate electrode 3 and a source / drain (impurity diffusion layer 5), a side electrode 6 and a dielectric film (gate oxide film 8) are interposed. A parasitic capacitor C (shown in a circle in the figure) constituted by a source and a contact hole φ formed in the electrode film 11 and a drain are connected to each other to function as a switch.
And an S transistor S.

In this bootstrap circuit, M
Since the source and the drain of the OS transistor M have the same potential, the OS transistor M functions as an amplifier having an almost equal interest rate.
When the voltage Vpp is applied to the drain of the OS transistor M, the voltage Vpp is applied to, for example, the word line WL of the memory cell MC of the DRAM.

As shown in FIG. 5, in order to prevent the gate electrode 3 from being constricted, the side electrode 6 is also provided on the side of the impurity diffusion layer 5 functioning as a drain at the boundary with the field shield element isolation structure 2. May be formed.

For example, as shown in FIG. 6, an input protection circuit (ESD) for protecting a transistor portion having an electrode film 11 from a surge voltage exceeding a withstand voltage of a semiconductor circuit.
Protection circuit). In this case, the drain of the input protection circuit is connected between the input / output pad I / O and the internal circuit I, and the source is grounded. Here, even if a surge voltage exceeding the withstand voltage of the internal circuit I is applied to the input / output pad I / O, a charge is released by flowing a surge current between the input / output pad I / O and the source, No surge voltage is applied to the internal circuit I.

Hereinafter, the method for fabricating the MOS transistor according to the first embodiment will be described. 7 to 9 are schematic cross-sectional views illustrating a method of manufacturing the MOS transistor in the order of steps, and FIG. 10 is a schematic plan view illustrating a photolithography step when forming the electrode films 11 and 12.

First, as shown in FIG. 7A, a field shield element isolation structure 2 is formed on the surface of a silicon semiconductor substrate 1, and these field shield element isolation structures 2 are formed.
Respectively define element active regions.

That is, on the silicon semiconductor substrate 1, a silicon oxide film 21a, a polycrystalline silicon film 22, and a silicon oxide film 21b are sequentially formed.

Thereafter, the silicon oxide film 21a, the polycrystalline silicon film 22, and the silicon oxide film 22b are patterned by photolithography and subsequent dry etching, and selectively removed to define an element active region.

Thereafter, the remaining silicon oxide film 21
a, after a silicon oxide film is formed on the entire surface so as to cover the polycrystalline silicon film 22 and the silicon oxide film 21b, the entire surface of the silicon oxide film is anisotropically dry-etched by RIE or the like to form the silicon oxide film 21a. Silicon oxide is left on the side walls of the crystalline silicon film 22 and the silicon oxide film 21b to form a side wall protective film 21c.

Thus, the silicon oxide films 21a, 21
A field shield element isolation structure 2 having a shield plate electrode 22 made of a polycrystalline silicon film surrounded by a silicon oxide film made of b and 21c is formed.

Then, the surface of the silicon semiconductor substrate 1 is subjected to thermal oxidation or CVD in the element active region defined and surrounded by the field shield element isolation structure 2.
After forming a gate oxide film 8 having a thickness of about 10 nm by a method or the like, a polycrystalline silicon film 31 and a silicon oxide film 32 are sequentially deposited and formed on the entire surface including the field shield element isolation structure 2 by a low-pressure CVD method or the like.

Subsequently, a photoresist is applied and formed on the entire surface of the silicon oxide film 32, and then the photoresist is formed as shown in FIG.
As shown in (1), using a photomask (reticle) 41 in which a predetermined pattern 43 made of chromium is formed on a substrate 42 made of quartz, this photomask 41 is masked and set above the photoresist. And
Exposure or the like is performed from above the photomask 41 to leave a photoresist following the pattern 43 of the photomask 41, and a resist pattern 44 is formed at a portion where the electrode films 11 and 12 are to be formed.

Here, in the resist pattern 44, those where the gate electrodes 3 and 4 are to be formed are referred to as patterns 45 and 46. Assuming that the resist pattern 44 is the boundary portion between the field shield element isolation structure 2 and the element active region, Pattern 45,
A part of the resist pattern 44 is also formed near the boundary 46 and along the boundary between the patterns 45 and 46 in the longitudinal direction. Here, as shown in FIG. 10, a part of the resist pattern 44 includes not only the patterns 47 and 48 where the side electrodes 6 and 7 are to be formed but also a part 46 a of the pattern 46. That is, when attention is paid to the pattern 45, the pattern 47 extends at the boundary portion with the field shield element isolation structure 2 in the longitudinal direction near the right side of the pattern 45, and the boundary portion near the left side of the pattern 45. Has a part 46a of the pattern 46
Extends. Focusing on the pattern 46, the boundary portion, that is, the field shield element isolation structure 2 does not exist on the right side of the pattern 46, but the pattern 48 extends on the boundary portion on the left side of the pattern 46.

The reflected light which directly adversely affects the patterns 45 and 46 at the time of exposure is from a step portion near the patterns 45 and 46 and along the longitudinal direction at the boundary with the field shield element isolation structure 2. However, a resist pattern 44 is formed on all of the steps. Therefore, reflected light from the step does not occur, and a resist pattern 44 having patterns 45 and 46 without narrowing or constriction without halation is formed.

Then, using the resist pattern 44 as a mask, the silicon oxide film 32, the polycrystalline silicon film 31, and the gate oxide film 8 are dry-etched to obtain a structure shown in FIG.
As shown in FIG. 2A, an electrode film 11 having a shape following the resist pattern 44 and having a cap insulating film 14 on the upper portion.
(3, 6) and 12 (4, 7) are patterned. Here, of the formed electrode films 11 and 12, strip-shaped portions existing in the element active region become the gate electrodes 3 and 4, and strip-shaped portions along the boundary portions become the side electrodes 6 and 7.
As described above, since the patterns 45 and 46 of the resist pattern 44 for forming the gate electrodes 3 and 4 are not thinned or constricted, the gate electrodes 3 and 4 also follow the shape of the thinned or constricted parts. Will not be formed in the desired shape.

Subsequently, after the resist pattern 44 is removed by an ashing process or the like, the surface regions of the silicon semiconductor substrate 1 on both sides of the gate electrodes 3 and 4 are masked using the cap insulating films 14 on the gate electrodes 3 and 4 as masks. Then, an n-type impurity, here, phosphorus is ion-implanted, and a predetermined heat treatment is performed to form each impurity diffusion layer 5 serving as a source / drain. At this time, when the impurity diffusion layer 5 serving as the source diffusion layer is formed, oblique ion implantation is performed, for example, so that the formed impurity diffusion layer 5 and the side electrodes 6 and 7 face each other via the gate oxide film 8. It is preferable to form the impurity diffusion layer 5 serving as the source diffusion layer so as to be disposed.

Subsequently, as shown in FIG.
The electrode films 11 (3, 6), 12 (4,
7) A silicon oxide film is deposited and formed on the entire surface including the field shield element isolation structure 2, and this silicon oxide film is subjected to anisotropic dry etching to form a side wall insulating film 13 on each side surface of the electrode films 11 and 12. Form each.

Subsequently, the electrode film 1 is formed by a normal pressure CVD method or the like.
An interlayer insulating film 15 made of a BPSG film is deposited and formed on the entire surface including the first and second field shield element isolation structures 2 and the impurity diffusion formed between the gate electrode 3 and the side electrode 6 as shown in FIG. Each contact hole 16 for exposing a part of each surface of the layer 5 and the impurity diffusion layer 5 formed between the gate electrode 4 and the side electrode 7 is formed.

When the contact holes 16 are formed in the interlayer insulating film 15, there is a problem that the aspect ratio of the contact holes 16 increases as the chip size is reduced. Since the contact holes 16 are provided, for example, as shown in FIG.
The side electrodes 6 and 7 (here, the side electrodes 7) serve as stoppers when the contact holes 16 are opened even when the aspect ratio is reduced and the formed portions are displaced.
Therefore, the required accuracy for the position where the contact hole 16 is formed is eased.

Then, an aluminum alloy film is deposited and formed on the entire surface of the interlayer insulating film 15 including the inside of each contact hole 16 by a sputtering method or the like, and the aluminum alloy film is subjected to photolithography and subsequent dry etching, etc. The inside of the contact hole 16 is filled and the impurity diffusion layer 5
Patterning a wiring layer 17 electrically connected to
The OS transistor is completed.

Note that a pad polycrystalline silicon film 23 for relaxing the aspect ratio of the contact hole 16 (FIG. 3)
Is formed, first, when the impurity diffusion layer 5 is formed, ions are implanted under the conditions of, for example, an acceleration energy of 60 (keV) and a dose of 3 × 10 ¹² (/ cm ² ).
^- forming an impurity diffusion layer. Then, after forming the sidewall insulating film 13 as shown in FIG. 8B and before forming the interlayer insulating film 15 as shown in FIG. 9, non-doped polycrystalline silicon is entirely formed by CVD or the like. A film is deposited and formed. Next, pattern this polycrystalline silicon film,
The space between the gate electrodes 3 and 4, the space between the gate electrode 3 and the side electrode 6, and the space between the gate electrode 4 and the side electrode 7 are filled via the side wall insulating film 13 and the cap insulating film 14, each of which is a lower n ⁻ impurity diffusion region. Each pad polycrystalline silicon film 23 is formed so as to be electrically connected to the layer. Thereafter, arsenic is ion-implanted into each of the pad polycrystalline silicon films 23 under the conditions of an acceleration energy of 75 (keV) and a dose of 1 × 10 ¹⁶ (/ cm ² ) to form an n ⁺ impurity diffusion layer 5. Form.

-Modification- Here, a modification of the first embodiment will be described. In this modification, as in the first embodiment, an M semiconductor having a gate electrode and source / drain diffusion layers as a semiconductor device is provided.
An OS transistor is exemplified, but is different in that a cap insulating film and a sidewall insulating film of a gate electrode are different. FIG.
FIG. 13 is a schematic plan view of a MOS transistor of this modified example, and FIGS.
FIG. 2 is a schematic cross-sectional view corresponding to a cross section taken along a broken line AA ′ in FIG. The same components as those of the MOS transistor of the first embodiment are denoted by the same reference numerals.

This MOS transistor is a two-input cascade-connected MOS transistor having two gate electrodes in the element active region, as in the first embodiment. A field shield element isolation structure 2 formed in the isolation region to define an element active region, a substantially U-shaped including a gate electrode 3 existing in the element active region and a side electrode 6 formed integrally with the gate electrode 3 A substantially inverted U-shaped electrode film 12 including an electrode film 11, a gate electrode 4 existing adjacent to the gate electrode 3 in the element active region, and a side electrode 7 formed integrally with the gate electrode 4; 3 and each impurity diffusion layer 5 formed in the surface region of the silicon semiconductor substrate 1 on both sides of (a part of) the gate electrode 4.

In the MOS transistor of this modification, the side wall insulating film 96 covering the electrode films 11, 12 and both side surfaces thereof, and the cap insulating film 97 covering the upper portion are formed of a silicon nitride film. Then, an interlayer insulating film 15 is formed on the entire surface including the field shield element isolation structure 2 and the electrode films 11 and 12. The interlayer insulating film 15 has an impurity diffusion layer formed between the gate electrode 3 and the side electrode 6. Layer 5
Each contact hole 98 for exposing a part of each surface of the impurity diffusion layer 5 formed between the gate electrode 4 and the side electrode 7 is formed. In this modification, a case where the sidewall insulating film 96 is exposed on the side surface of the contact hole 98 will be exemplified in order to cope with further miniaturization of the MOS transistor.

The wiring layer 17 made of an aluminum alloy film is formed on the interlayer insulating film 15 including the inside of each contact hole 98.
Are formed in a pattern, and the wiring layer 17 is
MOS transistor 8 is electrically connected to impurity diffusion layer 5 through
A transistor is configured.

According to the MOS transistor according to the modified example of the first embodiment, when attention is paid to one gate electrode formed in the element active region, a boundary portion between the field shield element isolation structure 2 and the element active region is formed. Among them, another gate electrode or a side electrode is configured to extend at least in the element active region at a boundary portion in the vicinity of the gate electrode and along the longitudinal direction of the gate electrode. Specifically, focusing on the gate electrode 3, the side electrode 6 extends at the boundary between the gate electrode 3 and the field shield element isolation structure 2 in the longitudinal direction near the right side of the gate electrode 3 in FIG. A part of the gate electrode 4 (near the front end part) extends to the boundary part on the left side of 3. Focusing on the gate electrode 4, the boundary portion, that is, the field shield element isolation structure 2 does not exist on the right side of the gate electrode 4 in FIG. Extends.

Therefore, as described later, the gate electrodes 3 and
In the photolithography process for forming 4,
The gate electrodes 3 and 4 are not adversely affected by halation. Even if the width of the gate electrodes 3 and 4 is on the order of 0.5 μm, the gate electrodes 3 and 4 are formed in a desired shape without constriction or the like. Have been.

Further, since the gate electrode 3 and the side electrode 7 are formed integrally with the side electrode 6 to form the electrode films 11 and 12, respectively, the gate electrode 3, the side electrode 6 and the gate electrode are formed. The electrode 4 and the side electrode 7 have the same potential. Further, since a potential different from the potential applied to the shield plate electrode 22 of the field shield element isolation structure 2 is applied to the electrode films 11 and 12, reliable element isolation by the shield plate electrode 22 is realized, and MOS The withstand voltage of the transistor can be improved.

Further, according to the MOS transistor of this modification, when the contact hole 98 is formed, even when the contact hole 98 is formed on the side wall insulating film 96 or the cap insulating film 97, as described later, Since the etching rate of the silicon nitride film is extremely lower than that of the silicon oxide film or the like, the side electrodes 6, 7 are formed when the contact holes 98 are formed.
The gate electrodes 3 and 4 are not exposed, and the required accuracy for the formation position of the contact hole 98 is relaxed, and the contact hole 98 is formed almost as designed.

Hereinafter, a MOS transistor according to a modification of the first embodiment will be described.
A method for manufacturing a transistor will be described. 13 to 15 are schematic cross-sectional views showing the manufacturing method of the MOS transistor in the order of steps, and FIG. 16 is a schematic plan view showing a photolithography step when forming the electrode films 11 and 12.

First, as shown in FIG. 13A, a field shield element isolation structure 2 is formed on the surface of a silicon semiconductor substrate 1, and an element active region is defined by each of the field shield element isolation structures 2.

That is, on the silicon semiconductor substrate 1, a silicon oxide film 21a, a polycrystalline silicon film 22, and a silicon oxide film 21b are sequentially formed.

Thereafter, the silicon oxide film 21a, the polycrystalline silicon film 22, and the silicon oxide film 22b are patterned by photolithography and subsequent dry etching, and selectively removed to define an element active region.

Thereafter, the remaining silicon oxide film 21
a, after a silicon oxide film is formed on the entire surface so as to cover the polycrystalline silicon film 22 and the silicon oxide film 21b, the entire surface of the silicon oxide film is anisotropically dry-etched by RIE or the like to form the silicon oxide film 21a. Silicon oxide is left on the side walls of the crystalline silicon film 22 and the silicon oxide film 21b to form a side wall protective film 21c.

As a result, the silicon oxide films 21a, 21
A field shield element isolation structure 2 having a shield plate electrode 22 made of a polycrystalline silicon film surrounded by a silicon oxide film made of b and 21c is formed.

Next, in the device active region defined and surrounded by the field shield device isolation structure 2, the surface of the silicon semiconductor substrate 1 is subjected to thermal oxidation or CVD.
After a gate oxide film 8 having a thickness of about 10 nm is formed by a method or the like, a polycrystalline silicon film 31 and a silicon nitride film 99 are sequentially deposited and formed on the entire surface including the field shield element isolation structure 2 by a low-pressure CVD method or the like.

Subsequently, after a photoresist is applied and formed on the entire surface of the silicon nitride film 99, FIG. 13B and FIG.
As shown in FIG. 6, using a photomask (reticle) 41 in which a predetermined pattern 43 made of chromium is formed on a substrate 42 made of quartz, the photomask 41 is placed above the photoresist so as to be aligned with the mask. . Then, exposure or the like is performed from above the photomask 41 to leave a photoresist following the pattern 43 of the photomask 41, and a resist pattern 44 is formed in a region where the electrode films 11 and 12 are to be formed.

Here, in the resist pattern 44, the portions where the gate electrodes 3 and 4 are to be formed are referred to as patterns 45 and 46. Assuming that the resist pattern 44 is the boundary portion between the field shield element isolation structure 2 and the element active region, Pattern 45,
A part of the resist pattern 44 is also formed near the boundary 46 and along the boundary between the patterns 45 and 46 in the longitudinal direction. Here, as shown in FIG. 16, a part of the resist pattern 44 includes not only the patterns 47 and 48 where the side electrodes 6 and 7 are to be formed, but also a part 46a of the pattern 46. That is, when attention is paid to the pattern 45, the pattern 47 extends at the boundary portion with the field shield element isolation structure 2 in the longitudinal direction near the right side of the pattern 45, and the boundary portion near the left side of the pattern 45. Has a part 46a of the pattern 46
Extends. Focusing on the pattern 46, the boundary portion, that is, the field shield element isolation structure 2 does not exist on the right side of the pattern 46, but the pattern 48 extends on the boundary portion on the left side of the pattern 46.

The reflected light which directly adversely affects the patterns 45 and 46 at the time of exposure is from the step near the patterns 45 and 46 and along the longitudinal direction at the boundary with the field shield element isolation structure 2. However, a resist pattern 44 is formed on all of the steps. Therefore, reflected light from the step does not occur, and a resist pattern 44 having patterns 45 and 46 without narrowing or constriction without halation is formed.

Subsequently, dry etching is performed on the silicon nitride film 99, the polycrystalline silicon film 31, and the gate oxide film 8 by using the resist pattern 44 as a mask, and FIG.
As shown in (a), the electrode films 11 (3, 6) and 12 (4, 7) having a shape following the resist pattern 44 and having a cap insulating film 97 made of a silicon nitride film on the upper side are patterned. . Here, the formed electrode films 11 and 12 are formed.
Of these, the strip-shaped portions existing in the element active region become the gate electrodes 3 and 4, and the strip-shaped portions along the boundary portions become the side electrodes 6 and 7. The gate electrodes 3 and 4 are formed as described above. 45 of the resist pattern 44 for performing
Since there is no thinning or constriction in 46, the gate electrodes 3 and 4 are also formed in a desired shape without any thinning or constriction according to these shapes.

Subsequently, after the resist pattern 44 is removed by ashing or the like, the surface regions of the silicon semiconductor substrate 1 on both sides of the gate electrodes 3 and 4 are masked using the cap insulating films 97 on the gate electrodes 3 and 4 as masks. Then, an n-type impurity, here, phosphorus is ion-implanted, and a predetermined heat treatment is performed to form each impurity diffusion layer 5 serving as a source / drain. At this time, when the impurity diffusion layer 5 serving as the source diffusion layer is formed, oblique ion implantation is performed, for example, so that the formed impurity diffusion layer 5 and the side electrodes 6 and 7 face each other via the gate oxide film 8. It is preferable to form the impurity diffusion layer 5 serving as the source diffusion layer so as to be disposed.

Subsequently, as shown in FIG. 14B, the electrode films 11 (3, 6), 12 (4,
7) A silicon nitride film is deposited and formed on the entire surface including the field shield element isolation structure 2, and the silicon nitride film is subjected to anisotropic dry etching to form a side wall insulating film 96 on each side surface of the electrode films 11 and 12. Form each.

Subsequently, the electrode film 1 is formed by a normal pressure CVD method or the like.
An interlayer insulating film 15 made of a BPSG film is deposited and formed on the entire surface including the first and second field shield element isolation structures 2, and the gate electrode 3 and the side electrode 6 are formed as shown in FIG.
Each contact hole 98 for exposing a part of each surface of the impurity diffusion layer 5 formed therebetween and the impurity diffusion layer 5 formed between the gate electrode 4 and the side electrode 7 is formed. .

In this modification, in order to cope with further miniaturization of the MOS transistor, the hole diameter of the contact hole 98 is formed to be relatively larger than the distance between the side wall insulating film 96 and the side wall protective film 21c. An example will be described. That is, as shown in FIG. 15, when the contact hole 98 is formed, a part of the side wall protective film 96 and the cap insulating film 97 are also etched. However, the side wall insulating film 96 and the cap insulating film 97 are made of a silicon nitride film. B
The etching rate is extremely lower than that of the interlayer insulating film 15 made of a PSG film, and the etching is hardly performed.
Therefore, the side electrodes 6 and 7 and the gate electrodes 3 and 4 are not exposed, so that the required accuracy for the formation position of the contact hole 98 is relaxed and the contact hole 98 is formed almost as designed. become.

Then, an aluminum alloy film is deposited and formed on the entire surface of the interlayer insulating film 15 including the inside of each contact hole 98 by a sputtering method or the like, and this aluminum alloy film is subjected to photolithography and subsequent dry etching, etc. Filling the inside of the contact hole 98 to form the impurity diffusion layer 5
Patterning a wiring layer 17 electrically connected to
The OS transistor is completed.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described. In the second embodiment, a MOS transistor having a gate electrode and a source / drain diffusion layer is exemplified as a semiconductor device as in the first embodiment, but is different in that the element isolation structure is different. FIG. 17 is a schematic plan view of the MOS transistor according to the second embodiment, and FIG. 18 is a schematic cross-sectional view along the broken line BB ′ in FIG. The MO of the first embodiment
The same components as those of the S transistor are denoted by the same reference numerals. In FIG. 17, illustration of various insulating films covering the electrode films is omitted.

This MOS transistor is, similarly to the MOS transistor of the first embodiment, a cascade-connected two-input device having two gate electrodes in the element active region. A trench-type element isolation structure 90 formed in the element isolation region to define an element active region; a substantially U-shaped electrode film 11 partially including the gate electrode 3 existing in the element active region; A substantially inverted U-shaped electrode film 12 partially including the gate electrode 4 existing adjacent to the gate electrode 3;
And impurity diffusion layers 5 formed in the surface region of the silicon semiconductor substrate 1 on both sides of (a part of) the gate electrode 4.

The trench type element isolation structure 90 is formed so as to surround the element active region as shown in FIG. 17, and is formed in the element isolation region on the silicon semiconductor substrate 1 as shown in FIG. The trench 91 is formed by filling a silicon oxide film 93 with a thermal oxide film 92 interposed therebetween.
Each element active region is electrically separated from other element active regions by the silicon oxide film 93. Here, in order to secure a sufficient element isolation function, the groove 9
Preferably, the depth of 1 is about 0.3 μm to 0.4 μm.

The impurity diffusion layer 5 is formed by ion-implanting n-type impurities into the surface region of the silicon semiconductor substrate 1 in the element active region surrounded by the trench-type element isolation structure 90 using the electrode films 11 and 12 as a mask. One is a source diffusion layer and the other is a drain diffusion layer. The surface regions of the silicon semiconductor substrate 1 immediately below the gate electrodes 3 and 4 sandwiched between the adjacent impurity diffusion layers 5 are gate electrodes 3 and 4, respectively.
4 channel section. However, one portion of the gate electrode 4 near its tip extends over the vicinity of the boundary between the trench-type device isolation structure 90 and the device active region, and no channel portion is formed in this portion.

The electrode film 11 is a polycrystalline silicon film formed in a substantially U shape on the silicon semiconductor substrate 1 with the gate oxide film 8 interposed therebetween. At the boundary between the trench type element isolation structure 90 and the element active region, the trench type element isolation structure 9 is formed.
A side electrode 6 is formed integrally at one end with a pattern formed along the longitudinal direction of the gate electrode 3 over the 0 and element active regions. In the second embodiment, the side electrode 6 is formed via the gate oxide film 8 above the element active region in which the impurity diffusion layer 5 serving as the source diffusion layer is formed. The electrode film 11 is opposed to the impurity diffusion layer 5 serving as a layer with the gate oxide film 8 interposed therebetween. The electrode film 11 is formed by the side electrode 6 with the gate oxide film 8 serving as a dielectric film and the impurity diffusion layer 5 serving as a source diffusion layer. And capacitive coupling.

The electrode film 11 is formed such that sidewall insulating films 13 are formed on both side surfaces thereof, and a cap insulating film 14 is formed thereon, and these are covered with these insulating films. The electrode film 11 includes the impurity diffusion layer 5 serving as a source diffusion layer because the portion of the side electrode 6 is capacitively coupled to the impurity diffusion layer 5 serving as a source diffusion layer as described above.
And the impurity diffusion layer 5 serving as a drain diffusion layer are completely at the same potential.

The electrode film 12 is a polycrystalline silicon film formed in a substantially inverted U-shape on the silicon semiconductor substrate 1 with the gate oxide film 8 interposed therebetween. The gate electrode 4 is formed in a strip pattern so as to extend near the boundary between the isolation structure 90 and the element active region, and in the longitudinal direction of the gate electrode 4 near the boundary between the trench type element isolation structure 90 and the element active region. Along with the side electrodes 7 pattern-formed along one end, each is integrally formed at one end. The electrode film 12 has a sidewall insulating film 13 formed on both side surfaces thereof and a cap insulating film 14 formed thereon, and is covered with these insulating films. Here, similarly to the electrode film 11, the side electrode 7 is formed via the gate oxide film 8 above the element active region in which the impurity diffusion layer 5 serving as the source diffusion layer is formed. The electrode diffusion layer 5 is opposed to the impurity diffusion layer 5 serving as a source diffusion layer with a gate oxide film 8 interposed therebetween. It is capacitively coupled with the layer 5.

As in the case of the electrode film 11, in the electrode film 12, the portion of the side electrode 7 is capacitively coupled to the impurity diffusion layer 5 serving as the source diffusion layer, and the impurity diffusion layer 5 serving as the source diffusion layer is formed. And impurity diffusion layer 5 serving as a drain diffusion layer
Are completely at the same potential.

Then, an interlayer insulating film 15 is formed on the entire surface including the trench type element isolation structure 90 and the electrode films 11 and 12, and the interlayer insulating film 15 is formed between the gate electrode 3 and the side electrode 6. Each contact hole 16 for exposing a part of each surface of the impurity diffusion layer 5 formed and the impurity diffusion layer 5 formed between the gate electrode 4 and the side electrode 7 is formed.

Further, a wiring layer 17 made of an aluminum alloy film is formed on the interlayer insulating film 15 including the inside of each contact hole 16 by patterning.
Are electrically connected to the impurity diffusion layer 5 through the MOS transistor to form a MOS transistor.

According to the MOS transistor according to the second embodiment, when attention is paid to one gate electrode formed in an element active region, the MOS transistor in the boundary portion between the trench type element isolation structure 90 and the element active region is Another gate electrode or side electrode is configured to extend at least in the element active region near the gate electrode and at a boundary portion along the longitudinal direction of the gate electrode. Specifically, focusing on the gate electrode 3, the side electrode 6 extends in the vicinity of the right side of the gate electrode 3 in FIG. 17 and at the boundary with the trench-type element isolation structure 90 in the longitudinal direction. 3
A part of the gate electrode 4 (near the front end portion) extends to the boundary portion on the left side of FIG. Focusing on the gate electrode 4, the boundary portion is located on the right side of the gate electrode 4 in FIG.
That is, the trench type element isolation structure 90 does not exist, but the side electrode 7 extends to the boundary portion on the left side of the gate electrode 4.

This trench-type element isolation structure 90 has the first
Field Shield Element Separation Structure 2 in Third Embodiment
Although it does not have such a large step, the silicon oxide film 93 is used to surely prevent leakage current and the like.
Are formed so as to slightly protrude outward. In the MOS transistor of the second embodiment, in the photolithography process for forming the gate electrodes 3 and 4, the gate electrodes 3 and 4 are not adversely affected by halation and the width of the gate electrodes 3 and 4 is reduced. The gate electrodes 3 and 4 are formed in a desired shape without constriction or the like even in the order of 0.5 μm.

As shown in FIG. 19, for example, between the gate electrodes 3 and 4, between the gate electrode 3 and the side electrode 6, and between the gate electrode 4 and the side electrode 7, a side wall insulating film 13 and a cap insulating film 14 are formed. And each is filled with a lower impurity diffusion layer 5.
The pad polycrystalline silicon film 23 may be patterned so as to be electrically connected to the contact hole 16 so as to reduce the aspect ratio of the contact hole 16.

Further, in the MOS transistor, for example, in the transistor portion having the gate electrode 3 of the electrode film 11, the source diffusion layer and the drain diffusion layer can be made completely at the same potential. MOS
Like the transistor, the present invention can be applied to various semiconductor circuits such as a bootstrap circuit and an input protection circuit.

Hereinafter, the method of manufacturing the MOS transistor according to the second embodiment will be described. 20 to 23
FIG. 24 is a schematic cross-sectional view showing a method of manufacturing the MOS transistor in the order of steps, and FIG. 24 is a schematic plan view showing a photolithography step when forming the electrode films 11 and 12 in FIG.

First, a trench type element isolation structure 90 is formed in an element isolation region on a silicon semiconductor substrate 1, and an element active region is defined on the silicon semiconductor substrate.

That is, as shown in FIG. 20A, the surface of the silicon semiconductor substrate 1 is thermally oxidized to form a pad thermal oxide film 94, and the pad thermal oxide film 94 is formed on the pad thermal oxide film 94 by a CVD method or the like. A nitride film 95 is formed.

Subsequently, as shown in FIG. 20B, the silicon nitride film 95, the pad thermal oxide film 94 and the silicon semiconductor substrate 1 are patterned to form a groove 91 in the element isolation region on the silicon semiconductor substrate 1. 0.3 μm to 0.4 μm
Formed to the extent.

Subsequently, as shown in FIG.
After performing a heat treatment on the inner wall of No. 1 to form a thermal oxide film 92,
A silicon oxide film 93 is deposited and formed on the entire surface by a CVD method or the like, and the inside of the groove 91 is filled with the silicon oxide film 93.

Subsequently, as shown in FIG. 21A, a silicon oxide film 93 is formed using the silicon nitride film 95 as a stopper.
Is planarized by CMP (Chemical Mechanical Polishing) or the like.

Thereafter, as shown in FIG. 21B, the trench type element isolation structure 90 is completed by removing the silicon nitride film 95 and the pad thermal oxide film 94 thereunder.

Next, as shown in FIG. 21C, the surface of the silicon semiconductor substrate 1 is subjected to thermal oxidation in a device active region defined by being surrounded by the trench type device isolation structure 90, or a CVD method or the like. After forming a gate oxide film 8 having a film thickness of about 10 nm, a polycrystalline silicon film 31 and a silicon oxide film 32 are sequentially deposited on the entire surface including the trench type element isolation structure 90 by a low pressure CVD method or the like.

Subsequently, after a photoresist is applied to the entire surface of the silicon oxide film 32 by coating, the photoresist shown in FIG.
As shown in FIG. 4, using a photomask (reticle) 41 in which a predetermined pattern 43 made of chromium is formed on a substrate 42 made of quartz, the photomask 41 is placed above the photoresist by masking. . Then, exposure or the like is performed from above the photomask 41 to leave a photoresist following the pattern 43 of the photomask 41, and a resist pattern 44 is formed in a region where the electrode films 11 and 12 are to be formed.

Here, in the resist pattern 44, the portions where the gate electrodes 3 and 4 are to be formed are referred to as patterns 45 and 46. Assuming that the resist pattern 44 is the boundary portion between the trench type element isolation structure 90 and the element active region, A part of the resist pattern 44 is formed near the patterns 45 and 46 and also at a boundary portion along the longitudinal direction of the patterns 45 and 46. Here, as shown in FIG. 24, as a part of the resist pattern 44, not only the patterns 47 and 48 where the side electrodes 6 and 7 are to be formed, but also the pattern 46.
Also includes a part 46a. That is, when attention is paid to the pattern 45, the pattern 47 is located near the right side of the pattern 45 at the boundary with the trench-type element isolation structure 90 in the longitudinal direction.
Is extended, and a part 46a of the pattern 46 extends to the boundary portion near the left side of the pattern 45. When focusing on the pattern 46, the boundary portion, that is, the trench-type element isolation structure 90 does not exist on the right side of the pattern 46 in FIG. 24, but the pattern 48 extends on the boundary portion on the left side of the pattern 46. I have.

The reflected light that directly adversely affects the patterns 45 and 46 during exposure is near the patterns 45 and 46 and extends along the longitudinal direction of the trench type element isolation structure 90.
The resist pattern 44 is formed in all of the steps at the boundary between the steps. Therefore, reflected light from the step does not occur, and a resist pattern 44 having patterns 45 and 46 without narrowing or constriction without halation is formed.

Subsequently, using the resist pattern 44 as a mask, the silicon oxide film 32, the polycrystalline silicon film 31, and the gate oxide film 8 are dry-etched to obtain a structure shown in FIG.
As shown in (b), the electrode film 11 has a shape following the resist pattern 44 and has the cap insulating film 14 on the upper portion.
(3, 6) and 12 (4, 7) are patterned. Here, of the formed electrode films 11 and 12, strip-shaped portions existing in the element active region become the gate electrodes 3 and 4, and strip-shaped portions along the boundary portions become the side electrodes 6 and 7.
As described above, since the patterns 45 and 46 of the resist pattern 44 for forming the gate electrodes 3 and 4 are not thinned or constricted, the gate electrodes 3 and 4 also follow the shape of the thinned or constricted parts. Will not be formed in the desired shape.

Subsequently, after the resist pattern 44 is removed by ashing or the like, the surface regions of the silicon semiconductor substrate 1 on both sides of the gate electrodes 3 and 4 are masked using the cap insulating films 14 on the gate electrodes 3 and 4 as masks. Then, an n-type impurity, here, phosphorus is ion-implanted, and a predetermined heat treatment is performed to form each impurity diffusion layer 5 serving as a source / drain. At this time, when the impurity diffusion layer 5 serving as the source diffusion layer is formed, oblique ion implantation is performed, for example, so that the formed impurity diffusion layer 5 and the side electrodes 6 and 7 face each other via the gate oxide film 8. It is preferable to form the impurity diffusion layer 5 serving as the source diffusion layer so as to be disposed.

Subsequently, as shown in FIG. 23A, the electrode films 11 (3, 6), 12 (4,
7) A silicon oxide film is deposited and formed on the entire surface including the trench type element isolation structure 90, and the silicon oxide film is subjected to anisotropic dry etching to form a side wall insulating film 13 on each side surface of the electrode films 11 and 12. Form each.

Subsequently, the electrode film 1 is formed by a normal pressure CVD method or the like.
An interlayer insulating film 15 made of a BPSG film is deposited and formed on the entire surface including the trenches 1 and 12 and the trench type element isolation structure 90.
As shown in FIG. 3B, each of an impurity diffusion layer 5 formed between the gate electrode 3 and the side electrode 6 and an impurity diffusion layer 5 formed between the gate electrode 4 and the side electrode 7 are formed. Each contact hole 16 for exposing a part of the surface is formed.

When the contact hole 16 is formed in the interlayer insulating film 15, there is a problem that the aspect ratio of the contact hole 16 increases as the chip size is reduced. Since the contact holes 16 are provided, the side electrodes 6 and 7 serve as stoppers when the contact holes 16 are opened, for example, even when the contact holes 16 are formed with a small aspect ratio and the formed portions are displaced. Therefore, the required accuracy for the position where the contact hole 16 is formed is eased.

Then, an aluminum alloy film is deposited and formed on the entire surface of the interlayer insulating film 15 including the inside of each contact hole 16 by a sputtering method or the like, and the aluminum alloy film is subjected to photolithography and subsequent dry etching to obtain an aluminum alloy film. The inside of the contact hole 16 is filled and the impurity diffusion layer 5 is formed.
Patterning a wiring layer 17 electrically connected to
The OS transistor is completed.

When the pad polycrystalline silicon film 23 for relaxing the aspect ratio of the contact hole 16 is formed, first, when the impurity diffusion layer 5 is formed, for example, the acceleration energy is 60 (keV). 3 × dose
Ions are implanted under the condition of 10 ¹² (/ cm ² ) to form an n ⁻ impurity diffusion layer. Then, after forming the side wall insulating film 13 as shown in FIG. 23A, before forming the interlayer insulating film 15 as shown in FIG. A polycrystalline silicon film is deposited and formed. Subsequently, the polycrystalline silicon film is patterned, and the gate electrode 3 and the gate electrode 4, the gate electrode 3 and the side electrode 6, and the gate electrode 4 and the side electrode 7 are interposed via the side wall protective film 13 and the cap insulating film 14. filling Te, each of the lower n ^-
Each pad polycrystalline silicon film 23 is formed so as to be electrically connected to the impurity diffusion layer. Thereafter, the acceleration energy of 75 (ke) is applied to each pad polycrystalline silicon film 23.
V), arsenic is ion-implanted under the conditions of a dose of 1 × 10 ¹⁶ (/ cm ² ) to form an n ⁺ impurity diffusion layer 5.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described. In the third embodiment, a silicon signature such as an EEPROM is exemplified as the semiconductor device. FIG. 25 is a schematic plan view of a silicon signature according to the third embodiment, and FIG.
FIG. 5 is a schematic sectional view taken along a broken line CC ′ in FIG.

This silicon signature is an EEPROM
Is a semiconductor device that encodes and stores settings of a program / erase voltage, time, and the like instructed to a program device in advance during a write / erase operation, and is usually arranged at an end of a memory cell. One word line is shared at the lower end of the memory array, and functions as a so-called "mask ROM" in which code information is stored depending on the presence or absence of an element active region of each transistor.

This silicon signature is formed in the element isolation region on the p-type silicon semiconductor substrate 51 to define the element active region.
And gate electrodes 53 and 54 formed in a strip pattern on the silicon semiconductor substrate 51 including on the field shield element isolation structure 52; and a field shield element isolation structure 52 that is adjacent to the gate electrode 53 and extends in the longitudinal direction. A side electrode 56 pattern-formed substantially parallel to the longitudinal direction at a boundary portion with the element active region;
3, 54, and each impurity diffusion layer 55 formed in the surface region of the silicon semiconductor substrate 1 on both sides.

The field shield element isolation structure 52 is
Similarly to the field shield element isolation structure 2 of the MOS transistor according to the first embodiment, the silicon oxide film 61
This is an element isolation structure in which a shield plate electrode 62 made of a polycrystalline silicon film is buried in a to 61c, and a silicon oxide film 61a below the shield plate electrode 62 functions as a gate insulating film. By fixing the potential of the shield plate electrode 62, each element active region is electrically separated from other element active regions.

As in the case of the second embodiment, instead of the field shield element isolation structure 52, silicon oxide is formed in a groove formed in an element isolation region on the silicon semiconductor substrate 51 as in the second embodiment. A trench-type element isolation structure in which a film is embedded may be formed.

The gate electrodes 53 and 54 are formed in a band shape via a gate oxide film 58 formed on each element active region. Here, the gate electrode 53 is constituted by two layers of polycrystalline silicon films 64 and 65, and the gate electrode 54
Is a two-layer polycrystalline silicon film 6 via a dielectric film 63
4,65. This gate electrode 54
Are formed of the same material as the floating gate, dielectric film and control gate of the memory cell.

The side electrode 56 is formed by laminating two layers of polycrystalline silicon films 64 and 65 and forming a pattern. The side electrode 56 is formed substantially in parallel with the gate electrode 53, and has a gate oxide film 58 interposed therebetween. It is arranged to face a part of the impurity diffusion layer 55. The side electrode 56 has the same potential as the gate electrode 53, and this potential has a value different from the potential (for example, 0 (V)) applied to the shield plate electrode 62 of the field shield element isolation structure 52. Is done.

The gate electrodes 53 and 54 and the side electrode 56 are formed with a sidewall insulating film 66 on both sides and a cap insulating film 67 on the upper portion, respectively, and are covered with these insulating films. It has been.

The impurity diffusion layer 55 is formed by the gate electrodes 53 and 5
An n-type impurity is ion-implanted into the surface region of the silicon semiconductor substrate 51 in the element active region partitioned by the field shield element isolation structure 52 with the mask 4 and the side electrode 56 as masks. 55
The surface regions of the silicon semiconductor substrate 51 immediately below the gate electrodes 53 and 54 sandwiched between the gate electrodes 53 and 54
Channel section.

Further, the space between the gate electrodes 53 and 54, the space between the gate electrode 53 and the side electrode 56, and the like are filled via the side wall insulating film 66 and the cap insulating film 67, and each of them is electrically connected to the lower impurity diffusion layer 55. Each pad polycrystalline silicon film 71 is formed so as to be connected.

Then, an interlayer insulating film 68 is formed on the entire surface including each pad polycrystalline silicon film 71 and the field shield element isolation structure 52. The interlayer polycrystalline silicon film 68 has pad polycrystalline silicon between the gate electrodes 53 and 54. Each contact hole 69 exposing a part of the surface of the film 71 is formed.

Further, each wiring layer 70 made of an aluminum alloy film is formed on the interlayer insulating film 68 including the inside of each contact hole 69.
Are formed so as to be substantially perpendicular to the gate electrodes 53 and 54 and the side electrodes 56 and to be substantially parallel to each other.
Are electrically connected to each other to form a silicon signature.

Here, as shown in FIG. 26, for example, the intersections between the gate electrode 53 and each wiring layer 70 are sequentially determined as Q _j−1 , Q
_j , Q _{j + 1} , Q _{j + 2} , Q _{j + 3} ..., field shield element isolation structures 52 are provided on both sides of the gate electrode 53 at a portion corresponding to Q _{j + 1.} Is located,
Since there is no element active region, the impurity diffusion layer 55 is not formed. Therefore, in this silicon signature, when the gate electrode 53 functioning as a word line is selected, only the portion at Q _{j + 1} is programmed to be non-conductive.

According to the silicon signature of the third embodiment, for example, when attention is paid to the gate electrode 53, FIG.
The side electrode 56 extends at a boundary portion with the field shield element isolation structure 52 in the longitudinal direction near the lower side of the gate electrode 53. Therefore, as will be described later, in the photolithography process for forming the gate electrode 53, the gate electrode 53 is not adversely affected by halation, and even if the width of the gate electrode 53 is on the order of 0.5 μm. The gate electrode 53 is formed in a desired shape without constriction or the like.

Further, the side electrode 56 has the same potential as the gate electrode 53, and this potential is different from the potential applied to the shield plate electrode 62 of the field shield element isolation structure 52. Therefore, reliable element isolation by the shield plate electrode 62 is realized, and even when a high voltage (approximately 20 (V)) is applied to the impurity diffusion layer 55, a decrease in breakdown voltage can be reduced.

Hereinafter, a method for manufacturing a silicon signature according to the third embodiment will be described. 27 to 29
FIG. 30 is a schematic cross-sectional view showing a method of manufacturing the silicon signature in the order of steps, and FIG.
FIG. 9 is a schematic plan view showing a photolithography step at the time of forming 3, 54 and side electrodes 56.

First, as shown in FIG. 27A, the MOS semiconductor according to the first embodiment is formed on the surface of a silicon semiconductor substrate 51.
Similar to the field shield element isolation structure 2 of the transistor, a field shield element isolation structure 52 in which a shield plate electrode 62 is buried in a silicon oxide film 61 composed of silicon oxide films 61a, 61b, 61c.
Are formed, and these field shield element isolation structures 52 are formed.
Respectively define element active regions.

Subsequently, in each element active region defined by being partitioned by the field shield element isolation structure 52,
After a thermal oxidation is performed on the surface of the silicon semiconductor substrate 51 or a gate oxide film 58 having a thickness of about 10 nm is formed by a CVD method or the like, a step of forming a floating gate and a dielectric film in a memory cell region (not shown) is performed. Utilizing low pressure CVD over the entire surface including the field shield element isolation structure 52
A polycrystalline silicon film 72 and a dielectric film 73 are sequentially deposited by a method or the like.

Subsequently, after the dielectric film 73 near the field shield element isolation structure 52 is removed by dry etching or the like, the process of forming a control gate in the memory cell region is used to form the dielectric film 73 and the multi-layer. Polycrystalline silicon film 74 and silicon oxide film 75 on crystalline silicon film 72
Are sequentially deposited.

Subsequently, after a photoresist is applied and formed on the entire surface of the silicon oxide film 75, a predetermined pattern 83 made of chromium is formed on a substrate 82 made of quartz, as shown in FIG. Photomask (reticle)
Using 81, the photomask 81 is mask-aligned and installed above the photoresist. Then, exposure or the like is performed from above the photomask 81 to leave a photoresist following the pattern 83 of the photomask 81, and a resist pattern 84 is formed at a portion where the gate electrodes 53 and 54 and the side electrode 56 are to be formed. I do.

Here, as shown in FIG. 30, when the pattern 85 is a portion of the resist pattern 84 where the gate electrode 53 is to be formed, a boundary portion between the field shield element isolation structure 52 and the element active region is formed. Of which
A pattern 86 in which the side electrode 56 is to be formed is formed near the pattern 85 and at a boundary portion along the longitudinal direction of the pattern 85. That is, when attention is paid to the pattern 85, the pattern 86 extends at the boundary portion with the field shield element isolation structure 52 in the longitudinal direction near the lower side of the pattern 85.

The reflected light which directly adversely affects the pattern 85 at the time of exposure is from the step near the pattern 85 and at the boundary with the field shield isolation structure 52 along the longitudinal direction. A resist pattern 86 is formed on this step. Therefore, reflected light from the step does not occur, and a resist pattern 84 having a pattern 85 without thinning or constriction without halation is formed.

Subsequently, using resist pattern 84 as a mask, silicon oxide film 75, polycrystalline silicon film 74, dielectric film 73, polycrystalline silicon film 72 and gate oxide film 5
8 is subjected to dry etching, and as shown in FIG. 28 (a), gate electrodes 53 and 54 and a side electrode 56 having a shape following the resist pattern 84 and having a cap insulating film 67 on the upper side are patterned. . In this case, the gate electrode 53 is composed of two layers of polycrystalline silicon films 64 and 65, and the gate electrode 54 is composed of two layers of polycrystalline silicon films 64 and 65 via a dielectric film 63.
Here, as described above, the pattern 85 of the resist pattern 84 for forming the gate electrode 53 does not have any narrowing or constriction or the like, so that the gate electrode 53 follows the desired shape without any thinning or constriction. Will be formed.

Subsequently, after the resist pattern 84 is removed by ashing or the like, the silicon semiconductor on both sides of the gate electrodes 53 and 54 is masked using the cap insulating films 67 on the gate electrodes 53 and 54 and the side electrodes 56 as masks. An n-type impurity, here, phosphorus is ion-implanted into a surface region of the substrate 51,
to form an n ^- the impurity diffusion layer.

Subsequently, as shown in FIG. 28B, a silicon oxide film is deposited and formed on the entire surface including the gate electrodes 53 and 54, the side electrodes 56 and the field shield element isolation structure 2 by a low pressure CVD method or the like. The silicon oxide film is subjected to anisotropic dry etching to form a gate electrode 53,
A side wall insulating film 66 is formed on each side surface of the side electrode 54 and the side electrode 56.

Subsequently, a non-doped polycrystalline silicon film is deposited and formed on the entire surface, and the polycrystalline silicon film is patterned to form a sidewall insulating film between the gate electrodes 53 and 54, between the gate electrode 53 and the side electrode 56, and the like. 66 and cap insulating film 6
, And each pad polycrystalline silicon film 71 is filled so as to be electrically connected to the lower n ⁻ impurity diffusion layer.
To form

Then, arsenic is ion-implanted into each pad polycrystalline silicon film 71 to form an n ⁺ impurity diffusion layer 55.

Subsequently, an interlayer insulating film 68 made of a BPSG film is deposited and formed on the entire surface including the field shield element isolation structure 2 by a normal pressure CVD method or the like, and as shown in FIG. Each contact hole 69 for exposing a part of the surface of the pad polycrystalline silicon film 71 is formed.

Then, an aluminum alloy film is deposited and formed on the entire surface of the interlayer insulating film 68 including the inside of each contact hole 69 by a sputtering method or the like, and this aluminum alloy film is subjected to photolithography and subsequent dry etching, etc. Filling the contact hole 69 with the impurity diffusion layer 5
Patterning a wiring layer 70 electrically connected to 5,
Complete the silicon signature.

(Fourth Embodiment) Next, a fourth embodiment will be described. In the fourth embodiment, a CMOS inverter is exemplified as a semiconductor device. FIG.
FIG. 1 is a schematic sectional view showing the CMOS inverter.

In this CMOS inverter, p-type and n-type well diffusion layers 111 and 112 are formed on a p-type silicon semiconductor substrate 101, and each element active region is defined by a field shield element isolation structure 102.
The element active region on the p-type well diffusion layer 111 has an nMOS
In the FET 131, a pMOSFET 132 is formed in an element active region on the n-type well diffusion layer 112.

Here, the field shield element isolation structure 102 is formed of silicon oxide films 102a, 102c, 102
This is an element isolation structure in which a shield plate electrode 102b made of a conductive film is buried in d. Each element active region is electrically separated from other element active regions by the shield plate electrode 102b.

Further, a gate oxide film 103 is formed on the entire surface of the silicon semiconductor substrate 101 including each element active region, and a gate electrode of a predetermined pattern made of polycrystalline silicon is formed on the gate oxide film 103 of each element active region. 104
Are formed. Further, a cap insulating film 113 is formed on the upper surface of the gate electrode 104, and a side wall insulating film 114, which is an insulating film, is formed on the side surface, and the gate electrode 104 is covered with the cap insulating film 113 and the side wall insulating film 114. Have been.

Then, the p-type and n-type well diffusion layers 111,
An n-type impurity is introduced into the p-type well diffusion layer 111 side and a p-type impurity is introduced into the n-type well diffusion layer 112 on both sides of each gate electrode 104 in the pair 112. A source diffusion layer 105 and a drain diffusion layer 106, which are layers, are formed.

Further, a source wiring layer 107 is formed in a predetermined pattern on the field shield element isolation structure 102 near each source diffusion layer 105, and a cap is formed on the entire surface of the silicon semiconductor substrate 101 including each element active region. An interlayer insulating film 108 is formed to cover the insulating film 113, the side wall insulating film 114, and the source wiring layer 107.

On the source diffusion layer 105 and the drain diffusion layer 106, contact holes 109 and 110 are formed to expose the surfaces of the source diffusion layer 105 and the drain diffusion layer 106 by piercing the interlayer insulating film 108. Similarly, a contact hole 121 is formed on the source wiring layer 107 to expose the surface of the source wiring layer 107 by piercing the interlayer insulating film 108. Then, the source diffusion layer 105
In the vicinity of the contact hole 109 and the contact hole 121, a metal wiring layer 122 extending from the contact hole 109 to the contact hole 121 on the interlayer insulating film 108 is formed in a predetermined pattern. On the other hand, in the vicinity of the drain diffusion layer 106, the contact hole 1
10 and the nMOSFET 131 on the interlayer insulating film 8
A metal wiring layer 123 extending from the contact hole 110 to the contact hole 110 of the pMOSFET 132 is formed in a predetermined pattern.

That is, one end of the metal wiring layer 122 is electrically connected to the source diffusion layer 105, and the other end is electrically connected to the source wiring layer 107. Therefore, the source diffusion layer 105 is connected to the source diffusion layer 105 via the metal wiring layer 122. The wiring layer 107 is electrically connected. On the other hand, one end of the metal wiring layer 123 is n
The drain diffusion layer 106 of the MOSFET 131 and the other end are electrically connected to the drain diffusion layer 106 of the pMOSFET 132, and the nMOSFET 131 and the pMOSFE
T132 is connected in series.

Further, an interlayer insulating film 124 is formed on the entire surface of silicon semiconductor substrate 101 including each element active region so as to cover metal wiring layers 122 and 123, and source diffusion layer 1 is formed.
Field Shield Element Isolation Structure 1 in the Neighborhood Area 05
02, a metal wiring layer 125 is formed on the interlayer insulating film 124.
Are formed in a predetermined pattern so as to face the source wiring layer 107 via the interlayer insulating films 108 and 124. Here, in the nMOSFET 131, the metal wiring layer 1
Reference numeral 25 denotes a negative power supply potential (Vbb) or a ground potential (GND). In the pMOSFET 132, the metal wiring layer 125 has a positive power supply potential (Vdd).

That is, on the field shield element isolation structure 102 near the source diffusion layer 105, the source wiring layer 107 and the metal wiring layer 125 are arranged to face each other with the interlayer insulating films 108 and 124 interposed therebetween. A capacitor C is constituted by the source wiring layer 107 and the metal wiring layer 125 sandwiching the layers 108 and 124. Here, the metal wiring layer 125 is formed by extending the power supply wiring on the field shield element isolation structure 102 or extending the wiring for making a well contact. This capacitor C has a large electric capacity because the metal wiring layer 125 is formed as wide as possible on the source wiring layer 107 via the interlayer insulating films 108 and 124 having a large area.

Then, an insulating film 126 is formed on the entire surface of the silicon semiconductor substrate 101 including each element active region so as to cover the metal wiring layer 125, and the CMOS according to the first embodiment is formed.
An inverter is configured.

FIG. 32A shows an equivalent circuit of the CMOS inverter according to the fourth embodiment. Thus, the nMOSF
The ET 131 and the pMOSFET 132 are connected in series to form a CMOS inverter.

Now, consider the operation of a CMOS inverter to which a logic signal has been input. Here, when a rising logic signal is input to the CMOS inverter, nMO
Since the operation of the SFET 131 is dominant, here n
The operation of the MOSFET 131 will be described. This nM
FIG. 32B shows an equivalent circuit of the OSFET 131. Here, Rs indicates the electric resistance of the source diffusion layer 105, Rd indicates the electric resistance of the drain diffusion layer 106, and Cgs
Is the electric capacitance between the gate electrode 104 and the source diffusion layer 105, Cbs is the electric capacitance between the silicon semiconductor substrate 101 (p-type well diffusion layer 111) and the source diffusion layer 105, Cg
d is the electric capacity between the gate electrode 104 and the drain diffusion layer 106, Cbd is the electric capacity between the silicon semiconductor substrate 101 (p-type well diffusion layer 111) and the drain diffusion layer 106,
Cgb is the gate electrode 104-the silicon semiconductor substrate 101
The electric capacitance between the (p-type well diffusion layers 111) is shown.

When a logic signal is input from gate electrode 104, the voltage between gate electrode 104 and drain diffusion layer 106 increases.
A current flows through the ET 131, releases the load capacitance, and the logic signal is propagated to the next stage.

What is important here is that the source diffusion layer 10
5 is the potential Vnvs of the node Nvs grounded through the electric resistance value Rs. The ground impedance Zs at the node Nvs is, as shown in FIG.
bs in parallel. The absolute value | Zs | of the ground impedance Zs has a frequency characteristic shown in FIG.
And the frequency fc = 1 / (2π · Rs · C
At frequencies sufficiently lower than bs), Rs becomes dominant and has a constant value Rs. On the other hand, at a frequency sufficiently higher than the frequency fc, Cbs becomes dominant and | Zs | ≒ 1 / (2π · f
Cbs).

That is, if the frequency fr of the rising (or falling) of the logic signal is higher than fc, | Zs
Is approximately 1 / (2π · f · Cbs), which is smaller than Rs. Ideally, the rising waveform of the logic signal is often treated as a ramp waveform as shown in FIG. 34A, but the actual waveform should be a gentle curve as shown in FIG. It is customary. Then, as shown in FIG. 34 (c), by fitting half of the sine wave to this waveform, a frequency fr corresponding to the rising can be obtained.

Here, by increasing the electric capacitance Cbs between the p-type well diffusion layer 111 and the source diffusion layer 105, that is, by providing the capacitor C having a large electric capacitance,
The increase in the potential Vnvs of the node Nvs is suppressed, and the signal propagation delay time is reduced. In addition, a large electric resistance Rs of the source diffusion layer 105 exists from a DC viewpoint, so that a sufficient noise margin is secured.

As described above, the CMO according to the fourth embodiment
According to the S inverter, a sufficient noise margin is secured because the electric resistance value of the source diffusion layer 105 is relatively large, and at the same time, the p-type well diffusion layer 111 and the n-type well diffusion layer 112- Source diffusion layer 1
Since the capacitors C having a large electric capacity are formed between the capacitors 05, the delay of the signal propagation time is suppressed, and the speed of the logic operation is increased.

In the fourth embodiment, the field shield element isolation structure 102 has been exemplified as the element isolation structure.
Instead of the so-called LOCO, as shown in FIG.
The field oxide film 133 may be formed by the S method.

As in the second embodiment, a trench-type element isolation structure in which the inside of the groove formed in the element isolation region on the silicon semiconductor substrate 101 is filled with a silicon oxide film is formed as in the second embodiment. May be.

Hereinafter, a method for manufacturing the CMOS inverter according to the fourth embodiment will be described. 36 to 41
31 is a schematic cross-sectional view showing a process of forming the CMOS inverter in the order of steps, and the reference numerals shown in FIGS. 36 to 41 are described so as to correspond to the reference numerals shown in FIG.

First, as shown in FIG. 36, p-type and n-type well diffusion layers 111 and 112 are formed in a p-type silicon semiconductor substrate 101 by an ion implantation method. Subsequently, a field shield element isolation structure 102 is formed on the surface of each of the p-type and n-type well diffusion layers 111 and 112, and each element active region is defined by the field shield element isolation structure 102.

That is, a silicon oxide film 102c and a polycrystalline silicon film 102 are formed on a silicon semiconductor substrate 101.
b and a silicon oxide film 102a are sequentially formed, and the silicon oxide film 102c, the polycrystalline silicon film 102b and the silicon oxide film 102a are selectively removed by patterning by photolithography and subsequent dry etching or the like, thereby selectively removing the element active region. Is defined. Thereafter, after a silicon oxide film is formed on the entire surface so as to cover the remaining silicon oxide film 102c, polycrystalline silicon film 102b, and silicon oxide film 102a, the entire surface of the silicon oxide film is anisotropically dry-etched by RIE or the like. To form a silicon oxide film 102c and a polycrystalline silicon film 102b.
The silicon oxide is left only on the side walls of the silicon oxide film 102a, and the side wall protective film 102d is formed. As a result, a field shield element isolation structure 102 including a shield plate electrode 102b made of a polycrystalline silicon film surrounded by the silicon oxide films 102a, 102c, and 102d is formed.

Next, as shown in FIG. 37, the surface of silicon semiconductor substrate 101 is subjected to thermal oxidation to form gate oxide film 1.
03 is formed. Further, after a polycrystalline silicon film is deposited and formed on the entire surface of the gate oxide film 103 by a vacuum evaporation method such as CVD, the film is patterned by photolithography and subsequent dry etching to obtain a p-type, n-type.
Oxide film 103 on type well diffusion layers 111 and 112
A gate electrode 4 is formed on the gate electrode 4 and the source wiring layer 107 is left only on the field shield element isolation structure 102 near the portion to become each source diffusion layer 105 while leaving the polycrystalline silicon film in a predetermined pattern. Form each.

Next, as shown in FIG. 38, a silicon oxide film is deposited on the entire surface by a vacuum deposition method such as CVD so as to cover the gate electrode 104, and then the entire surface of the silicon oxide film is anisotropically formed by RIE or the like. By dry etching, a cap insulating film 113 and a side wall insulating film 114 are formed to cover the gate electrode 104 while leaving the silicon oxide film only on the upper surface and side surfaces of the gate electrode 104.

Subsequently, arsenic (A) is applied to the p-type well diffusion layer 111 using the cap insulating film 113 of the gate electrode 104 formed on the p-type well diffusion layer 111 as a mask.
s) is performed to form the source diffusion layer 105 and the drain diffusion layer 106 of the nMOSFET 131, and further, using the cap insulating film 113 of the gate electrode 104 formed on the n-type well diffusion layer 112 as a mask,
(B) ions are implanted into the p-type well diffusion layer 112 to form the source diffusion layer 105 of the pMOSFET 132.
And a drain diffusion layer 106 is formed.

Next, as shown in FIG. 39, a silicon oxide film is deposited on the entire surface including the source wiring layer 107 by a vacuum deposition method such as CVD to form an interlayer insulating film.
Subsequently, photolithography and subsequent dry etching are performed on the interlayer insulating film 108 to form the interlayer insulating film 108 on the source diffusion layer 105 and the drain diffusion layer 108, thereby forming the source diffusion layer 105 and the drain diffusion layer. Contact holes 109 and 11 for exposing the surface of
Then, a contact hole 121 for exposing the surface of the source wiring layer 107 is also formed on the source wiring layer 107 by forming an interlayer insulating film 108 in the same manner.

Next, as shown in FIG. 40, a metal film made of aluminum is formed on the entire surface including the contact holes 109, 110, and 121 by a vacuum deposition method such as a sputtering method. The contact holes 109 and 121 are filled by performing subsequent dry etching or the like, and the contact holes 109 are removed from the contact holes 109 on the interlayer insulating film 108.
Metal wiring layer 122 extending to the contact hole 1
10, and the nMOSFET 1 is
Metal wiring layer 123 extending from contact hole 110 of contact 31 to contact hole 110 of pMOSFET 132
Are formed in a predetermined pattern.

At this time, one end of the metal wiring layer 122 is electrically connected to the source diffusion layer 105 and the other end is electrically connected to the source wiring layer 107. Therefore, the source diffusion layer 105 and the source wiring are connected via the metal wiring layer 122. The layer 107 is electrically connected. On the other hand, one end of the metal wiring layer 123 is nMOSFE
The drain diffusion layer 106 of T131 and the other end are pMOS
The pMOSFET 131 and the nMOSFET 132 are electrically connected to the drain diffusion layer 106 of the FET 132, and are connected in series.

Next, as shown in FIG. 41, a silicon oxide film is deposited on the entire surface by a vacuum deposition method such as CVD so as to cover the metal wiring layers 122 and 123, thereby forming an interlayer insulating film 124.
To form

Subsequently, a metal film made of aluminum is formed on the interlayer insulating film 124 by a vacuum deposition method such as a sputtering method, and the metal film is subjected to photolithography and subsequent dry etching to form a metal wiring layer. A metal wiring layer 125 having a predetermined pattern is formed on the metal wiring layer 122 so as to face the source wiring layer 107 with an interlayer insulating film 124 interposed therebetween. At this time, the capacitor C is configured by the source wiring layer 107 and the metal wiring layer 125 which are arranged to face each other with the interlayer insulating films 108 and 124 interposed therebetween.

Thereafter, a silicon oxide film and a silicon nitride film are sequentially deposited on the entire surface including the metal wiring layer 125 by a vacuum evaporation method to form an insulating film 126, and a predetermined post-processing is performed to thereby perform the fourth embodiment. The CMOS inverter of the form is completed.

(Fifth Embodiment) Hereinafter, a fifth embodiment of the present invention will be described. In the fifth embodiment, as in the fourth embodiment, a CMO
The S inverter will be exemplified. CMO of the fifth embodiment
The S-inverter differs from that of the fourth embodiment in that the S-inverter does not have the metal wiring layer 125 and has a slightly different field shield element isolation structure near the source diffusion layer 105. FIG. 42 is a schematic sectional view showing this CMOS inverter. Here, C exemplified in the fourth embodiment
Components corresponding to the components of the MOS inverter are denoted by the same reference numerals and description thereof is omitted.

In this CMOS inverter, p-type and n-type well diffusion layers 1 are formed on p-type silicon semiconductor substrate 101.
11 and 112 are formed. The field shield element isolation structure 141 is provided near the source diffusion layer 105, and the field shield element isolation structure 10 is provided in other areas.
Each element active region is defined by 2, and an nMOSFET 131 is provided in the element active region on the p-type well diffusion layer 111.
The pMOS is used for the element active region on the n-type well diffusion layer 112.
FETs 132 are respectively formed.

The field shield element isolation structure 141 has a silicon oxide film 141 similar to the field shield element isolation structure 102 shown in the fourth embodiment.
a, 141c, and 141d have a shield plate electrode 141b made of a conductive film embedded therein. The silicon oxide film 141a on the shield plate electrode 141b has a film thickness of silicon of the field shield element isolation structure 102. The oxide film 102a is formed thinner than the film thickness. Here, the shield plate electrode 14
1b is formed so that its film thickness is larger than the film thickness of shield plate electrode 102b, and as a result, the film thickness of silicon oxide film 141a on shield plate electrode 141b becomes larger on shield plate electrode 102b. The thickness is made smaller than the thickness of the silicon oxide film 102a.

Incidentally, in order to form the field shield element isolation structures 102 and 141, the following method can be considered.

First, as a first method, after a polycrystalline silicon film serving as the shield plate electrodes 102b and 141b is formed thin (that is, the thickness of the shield plate electrode 102b), a portion serving as the field shield element isolation structure 141 is formed. Then, a mask is formed, a polycrystalline silicon film is further formed, and the shield plate electrode 141b is formed to have a larger thickness than the shield plate electrode 102b. In this case, the silicon oxide film 141a deposited and formed on the shield plate electrode 141b becomes the silicon oxide film 102 deposited and formed on the shield plate electrode 102b.
It is formed thinner than a.

Next, as a second method, the thickness of the polycrystalline silicon film to be the shield plate electrodes 102b and 141b is increased (that is, the thickness of the shield plate electrode 141b is increased).
After the formation, the field shield element isolation structure 102
Then, a mask is formed except for a portion to be formed, and the polycrystalline silicon film is etched to form the shield plate electrode 102b with a smaller thickness than the shield plate electrode 141b. Also in this case, the silicon oxide film 141a deposited and formed on the shield plate electrode 141b is formed thinner than the silicon oxide film 102a deposited and formed on the shield plate electrode 102b.

As in the CMOS inverter according to the fourth embodiment, a source wiring layer 107 is formed in a predetermined pattern on a field shield element isolation structure 141 near each source diffusion layer 105. An interlayer insulating film 108 is formed on the entire surface of the silicon semiconductor substrate 101 including the element active region so as to cover the cap insulating film 113, the sidewall insulating film 114, and the source wiring layer 107.

Further, contact holes 109 and 110 are formed on the source diffusion layer 105 and the drain diffusion layer 106 to expose the surfaces of the source diffusion layer 105 and the drain diffusion layer 106 by piercing the interlayer insulating film 108. The interlayer insulating film 10 is similarly formed on the source wiring layer 107.
8, a contact hole 121 for exposing the surface of the source wiring layer 107 is formed. In the vicinity of the source diffusion layer 105, the contact hole 109 and the contact hole 121 are filled, and a metal wiring layer 122 extending from the contact hole 109 to the contact hole 121 on the interlayer insulating film 108 is formed in a predetermined pattern. Have been.
On the other hand, in the vicinity of the drain diffusion layer 106, the contact hole 110 is filled, and the nMOS
From the contact hole 110 of the FET 131 to the pMOSFET
A metal wiring layer 123 extending to the contact hole 110 of 132 is formed in a predetermined pattern.

That is, one end of the metal wiring layer 122 is electrically connected to the source diffusion layer 105, and the other end is connected to the source wiring layer 107. Therefore, the source diffusion layer 5 and the source diffusion layer 105 are connected via the metal wiring layer 122. The wiring layer 7 is electrically connected. On the other hand, one end of the metal wiring layer 123 is nMOSF
The drain diffusion layer 106 of ET131 and the other end are pMO
The nMOSFET 131 and the pMOSFET 132 are electrically connected to the drain diffusion layer 106 of the SFET 132.
And are connected in series.

Here, near the field shield element isolation structure 141, the shield plate electrode 141b of the field shield element isolation structure 141 and the source wiring layer 107 are opposed to each other via the silicon oxide film 141a on the shield plate electrode 141b. And the shield plate electrode 141 via the silicon oxide film 141a.
b and the source wiring layer 107 constitute a capacitor C ′. That is, on the p-type well diffusion layer 111, the p-type well diffusion layer 111 is set to the negative power supply potential (Vbb), and the source diffusion layer 105 and the shield plate electrode 141b are set to the ground potential (GND), respectively. Diffusion layer 105 and shield plate electrode 141
b is capacitively coupled, the n-type well diffusion layer 112 has a positive power supply potential (Vdd) on the n-type well diffusion layer 112, and the source diffusion layer 105 and the shield plate electrode 141b also have a positive power supply potential. The source diffusion layer 105 and the shield plate electrode 14 are set to a potential (Vdd).
1b is capacitively coupled. This capacitor C 'has the same function as the capacitor C shown in the fourth embodiment.

Then, an insulating film 126 is formed on the entire surface of the silicon semiconductor substrate 101 including each element active region so as to cover the metal wiring layers 122 and 123, and the C film of the fifth embodiment is formed.
A MOS inverter is configured.

As described above, the CMO according to the fifth embodiment
According to the S inverter, a sufficient noise margin is secured because the electric resistance value of the source diffusion layer 105 is relatively large, and at the same time, between the p-type well diffusion layer 111 and the source diffusion layer 105 and between the n-type well diffusion layer 112 and Source diffusion layer 1
Since the capacitors C 'having large electric capacitances are formed between the capacitors 05, the delay of the signal propagation time is suppressed and the speed of the logic operation is increased.

(Sixth Embodiment) Hereinafter, a sixth embodiment of the present invention will be described. In the sixth embodiment, a method for manufacturing a CMOS inverter will be described. 43 to 49 are schematic cross-sectional views showing steps of forming the CMOS inverter in the order of steps.

First, as shown in FIG. 43, p-type and n-type well diffusion layers 111 and 112 are formed in a p-type silicon semiconductor substrate 101 by an ion implantation method. Subsequently, a field shield element isolation structure 102 is formed on the surface of each of the p-type and n-type well diffusion layers 111 and 112, and each element active region is defined by the field shield element isolation structure 102.

That is, a silicon oxide film 102c and a polycrystalline silicon film 102 are formed on a silicon semiconductor substrate 101.
b and a silicon oxide film 102a are sequentially formed, and the silicon oxide film 102c, the polycrystalline silicon film 102b, and the silicon oxide film 102a are selectively removed by patterning by photolithography and subsequent dry etching or the like to selectively remove the element active region. Is defined. Thereafter, after a silicon oxide film is formed on the entire surface so as to cover the remaining silicon oxide film 102c, polycrystalline silicon film 102b, and silicon oxide film 102a, the entire surface of the silicon oxide film is anisotropically dry-etched by RIE or the like. To form a silicon oxide film 102c and a polycrystalline silicon film 102b.
The silicon oxide is left only on the side walls of the silicon oxide film 102a, and the side wall protective film 102d is formed. As a result, a field shield element isolation structure 2 including a shield plate electrode 102b made of a polycrystalline silicon film surrounded by the silicon oxide films 102a, 102c, and 102d is formed.

Next, thermal oxidation is performed on the surface of silicon semiconductor substrate 101 to form gate oxide film 103. Further, after a polycrystalline silicon film is formed on the entire surface of the gate oxide film 103 by a vacuum evaporation method, the polycrystalline silicon film is patterned by photolithography and subsequent dry etching or the like to form p-type and n-type well diffusion layers 111 and 112. A gate electrode 104 is formed on the gate oxide film 103.

Next, a silicon oxide film is deposited and formed on the entire surface by a vacuum evaporation method so as to cover the gate electrode 104. Subsequently, the entire surface of the silicon oxide film is anisotropically dry-etched by RIE or the like. The gate electrode 104 is left while leaving the silicon oxide film only on the top and side surfaces.
Forming a cap insulating film 113 and a side wall insulating film 114 covering the semiconductor substrate.

Subsequently, arsenic (A) is applied to the p-type well diffusion layer 111 using the cap insulating film 113 of the gate electrode 104 formed on the p-type well diffusion layer 111 as a mask.
s) is performed to form the source diffusion layer 105 and the drain diffusion layer 106 of the nMOSFET 131, and further, the n-type well diffusion layer 112 is formed by using the cap insulating film 113 of the gate electrode 104 formed on the n-type well diffusion layer 112 as a mask. The source diffusion layer 105 and the drain diffusion layer 106 of the pMOSFET 132 are formed by implanting boron (B) ions into the type well diffusion layer 112.

Next, as shown in FIG.
Each of the source diffusion layers 105 of the ET 131 and the pMOSFET 132 is subjected to anisotropic etching using an etching solution such as an aqueous solution of potassium hydroxide to form a recess 143, and only one side surface of the source diffusion layer 105 is formed inside the recess 143. Part (side wall part 142) is left.

Here, in performing the anisotropic etching using an aqueous solution of potassium hydroxide as an etching solution, etching to the interface between the source diffusion layer 105 and the silicon semiconductor substrate 101 with good controllability is performed under the following conditions. It is preferable to perform etching at

First, when forming the recess 143 in the source diffusion layer 105 of the p-type well diffusion layer 111, the potential of the p-type well diffusion layer 111 is set to −0.5 V or more with respect to the potential of the aqueous potassium hydroxide solution. , N-type well diffusion layer 112
With reference to the potential of the aqueous solution of potassium hydroxide.
1.2V or less. On the other hand, when forming the concave portion 143 in the source diffusion layer 105 of the n-type well diffusion layer 112, n
The potential of the p-type well diffusion layer 112 is set to −1 V or more with respect to the potential of the aqueous potassium hydroxide solution,
The potential of No. 11 is in a floating state.

Next, as shown in FIG. 45, the silicon semiconductor substrate 101 anisotropically etched is subjected to thermal oxidation to form a silicon oxide film having a thickness substantially equal to that of the gate oxide film 103. The oxide film is patterned by subjecting it to photolithography and subsequent dry etching, etc., to form a bottom insulating film 144 while leaving the silicon oxide film only on the bottom surface of the concave portion 143.

Subsequently, as shown in FIG. 46, polycrystalline silicon is deposited on the silicon semiconductor substrate 101 by a vacuum deposition method to fill the recess 143, and patterning is performed by photolithography and subsequent dry etching. At the same time, the surface of the polycrystalline silicon raised on the concave portion 143 is polished,
P) is applied to flatten the surface. This CMP polishing method
This is a polishing method that uses a slurry of a predetermined chemical solution and an abrasive, and has the advantage that even steps on the order of millimeters can be eliminated and high-precision flattening, for example, the step on the surface can be suppressed to about 0.05 μm. Have.

Next, as shown in FIG. 47, a silicon oxide film is deposited on the entire surface by vacuum evaporation to form an interlayer insulating film 1.
08, the interlayer insulating film 108 is subjected to photolithography and subsequent dry etching or the like, so that the interlayer insulating film 108 is formed on the source diffusion layer 105 and the drain diffusion layer 106 to form the source diffusion layer 105 and Contact holes 109 and 110 for exposing the surface of the drain diffusion layer 106 are formed.

Next, as shown in FIG. 48, a metal film made of aluminum is formed on the entire surface including the contact holes 109 and 110 by a vacuum evaporation method, and the metal film is subjected to photolithography and subsequent dry etching. To fill the contact hole 109,
The metal wiring layer 122 extending from the contact hole 109 to the field shield element isolation structure 102 and the contact hole 110 are filled, and the field shield element isolation structure 1
Each of the metal wiring layers 123 extending to 02 is formed in a predetermined pattern.

Thereafter, as shown in FIG. 49, a silicon oxide film and a silicon nitride film are sequentially deposited on the entire surface including the metal wiring layers 122 and 123 by a vacuum deposition method to form an insulating film 1.
The CMOS inverter according to the sixth embodiment is completed by forming 26 and performing predetermined post-processing.

The C manufactured in the sixth embodiment
In the MOS inverter, a bottom insulating film 144 made of a silicon oxide film is formed at the bottom of source diffusion layer 105. In the MOS transistor, the side wall portion of the source diffusion layer needs to be made of a semiconductor material in order to perform its function, but the bottom portion is not required. In the sixth embodiment, by providing the bottom insulating film 144 on the bottom, the p-type well diffusion layer 111 and the source diffusion layer 105 in the nMOSFET 131 are
In No. 2, the n-type well diffusion layer 112 and the source diffusion layer 105 each constitute a capacitor via the bottom insulating film 144, and the electric capacity is about 30 to 40 times that of the case where the bottom insulating film 144 does not exist. Become.

As described above, the CMO according to the third embodiment
According to the S inverter, a sufficient noise margin is secured because the electric resistance value of the source diffusion layer 105 is relatively large, and at the same time, between the p-type well diffusion layer 111 and the source diffusion layer 105 and between the n-type well diffusion layer 112 and Source diffusion layer 1
Since capacitors each having a large electric capacity are formed between the capacitors 05, the delay of the signal propagation time is suppressed, and the speed of the logic operation is increased.

(Seventh Embodiment) Hereinafter, a seventh embodiment will be described. In the seventh embodiment, a method for manufacturing a DRAM as a semiconductor device will be described. FIG.
FIG. 51 to FIG. 51 are schematic sectional views showing the process of forming the DRAM in the order of steps.

First, as shown in FIG. 50A, a field shield element isolation structure 102 is formed on the surface of a p-type silicon semiconductor substrate 101, and each element active region is defined by the field shield element isolation structure 102. I do.

That is, a silicon oxide film 102c and a polycrystalline silicon film 102 are formed on a silicon semiconductor substrate 101.
b and a silicon oxide film 102a are sequentially formed, and the silicon oxide film 102c, the polycrystalline silicon film 102b, and the silicon oxide film 102a are selectively removed by patterning by photolithography and subsequent dry etching or the like to selectively remove the element active region. Is defined. Thereafter, after a silicon oxide film is formed on the entire surface so as to cover the remaining silicon oxide film 102c, polycrystalline silicon film 102b, and silicon oxide film 102a, the entire surface of the silicon oxide film is anisotropically dry-etched by RIE or the like. To form a silicon oxide film 102c and a polycrystalline silicon film 102b.
The silicon oxide is left only on the side walls of the silicon oxide film 102a, and the side wall protective film 102d is formed. As a result, a field shield element isolation structure 102 including a shield plate electrode 102b made of a polycrystalline silicon film surrounded by the silicon oxide films 102a, 102c, and 102d is formed.

Next, thermal oxidation is performed on the surface of silicon semiconductor substrate 101 to form gate oxide film 103. Further, a polycrystalline silicon film is deposited and formed on the entire surface of the gate oxide film 103 by a vacuum deposition method such as CVD, and then patterned by photolithography and subsequent dry etching to form a gate electrode on the gate oxide film 103. 104, and each source diffusion layer 10
5 and the source wiring layer 10 while leaving the polycrystalline silicon film in a predetermined pattern on the field shield element isolation structure 102 in the vicinity of the part to be each drain diffusion layer 106.
7 and the drain electrode layer 151 are formed.

Next, C is applied to cover the gate electrode 104.
A silicon oxide film is deposited and formed on the entire surface by a vacuum evaporation method such as VD, and then the entire surface of the silicon oxide film is anisotropically dry-etched by RIE or the like, so that the silicon oxide film is formed only on the upper surface and side surfaces of the gate electrode 104. A cap insulating film 113 and a sidewall insulating film 114 are formed to cover the gate electrode 104 except for the above.

Subsequently, arsenic (As) ions are implanted into the silicon semiconductor substrate 101 by using the cap insulating film 113 of the gate electrode 104 as a mask to form nMOSFE.
Source diffusion layer 105 and drain diffusion layer 10 of T161
6 is formed.

Next, as shown in FIG. 50B, a silicon oxide film is deposited on the entire surface including the source wiring layer 107 and the drain electrode layer 151 by a vacuum deposition method such as CVD to form an interlayer insulating film. Subsequently, the interlayer insulating film 1
08 is subjected to photolithography and subsequent dry etching or the like to expose the surfaces of the source diffusion layer 105 and the drain diffusion layer 106 by piercing the interlayer insulating film 108 on the source diffusion layer 105 and the drain diffusion layer 106. The contact holes 109 and 110 are formed, and the interlayer insulating film 108 is similarly formed on the source wiring layer 107 and the drain electrode layer 151 to expose the surfaces of the source wiring layer 107 and the drain electrode layer 151.
21 and 152 are respectively formed.

Next, as shown in FIG. 51A, a metal film made of aluminum is formed on the entire surface including the contact holes 109, 110, 121, and 152 by a vacuum deposition method such as a sputtering method. By subjecting the film to photolithography and subsequent dry etching or the like, the contact hole 109 and the contact hole 121 are filled, and a metal wiring layer 122 extending from the contact hole 19 to the contact hole 121 on the interlayer insulating film 108 is formed. The hole 110 and the contact hole 152 are filled, and a metal wiring layer 153 extending from the contact hole 110 to the contact hole 152 is formed in a predetermined pattern on the interlayer insulating film 108.

At this time, one end of the metal wiring layer 122 is electrically connected to the source diffusion layer 105 and the other end is connected to the source wiring layer 107. Therefore, the source diffusion layer 105 is connected to the source wiring layer 107 via the metal wiring layer 122. The layer 107 is electrically connected. On the other hand, one end of the metal wiring layer 153 is electrically connected to the drain diffusion layer 106, and the other end is electrically connected to the drain electrode layer 151. Therefore, the drain diffusion layer 106 and the drain electrode layer 151 are connected via the metal wiring layer 153. Electrically connected.

Next, as shown in FIG. 51B, an interlayer insulating film 124 is formed by depositing a silicon oxide film on the entire surface by a vacuum deposition method such as CVD so as to cover the metal wiring layer 122 and the metal wiring layer 153. I do.

Subsequently, a metal film made of aluminum is formed on the interlayer insulating film 124 by a vacuum deposition method such as a sputtering method, and the metal film is subjected to photolithography and subsequent dry etching to form a metal wiring layer. A metal wiring layer 125 having a predetermined pattern is formed on the metal wiring layer 153 so as to face the source wiring layer 107 with the interlayer insulating film 124 interposed therebetween.
A metal electrode layer 154 having a predetermined pattern is formed so as to face the drain electrode layer 151 with the interposition therebetween. At this time, the capacitor C is constituted by the source wiring layer 107 and the metal wiring layer 125 which are opposed to each other via the interlayer insulating films 108 and 124, and the drain electrode layer which is opposed to the source wiring layer 107 and the interlayer insulating films 108 and 124. 151 and the metal electrode layer 154 form a capacitor 162 of the DRAM. Here, in the capacitor 162, the drain electrode layer 151 functions as a storage node electrode, and the metal electrode layer 154 functions as a cell plate electrode.

Thereafter, a silicon oxide film and a silicon nitride film are sequentially deposited on the entire surface including the metal wiring layer 125 and the metal electrode layer 154 by a vacuum evaporation method to form an insulating film 126, and a predetermined post-processing is performed. Then, the DRAM of the seventh embodiment is completed.

As described above, the DR according to the seventh embodiment is described.
According to the AM manufacturing method, a sufficient noise margin is secured because the electric resistance value of the source diffusion layer 105 is relatively large, and a capacitor C having a large electric capacitance is provided between the silicon semiconductor substrate 101 and the source diffusion layer 105. As a result, the delay of the signal propagation time is suppressed, and the speed of the logic operation is increased.

In addition, since the layers of the capacitor C and the capacitor 162 of the DRAM are simultaneously formed with good matching,
The number of manufacturing steps can be reduced.

(Eighth Embodiment) Hereinafter, an eighth embodiment will be described. In the eighth embodiment, a method for manufacturing a DRAM as a semiconductor device will be described. FIG.
FIG. 52 is a schematic plan view of the DRAM, and FIG. 52 is a schematic sectional view corresponding to a section taken along line AA ′ of FIG. Incidentally, in the method of manufacturing the DRAM according to the eighth embodiment, first, in the seventh embodiment, FIG.
0 (a), the same steps as those described with reference to FIG. 50 (b) and FIG. 51 (a) are performed.

That is, first, as shown in FIG. 50A, field shield element isolation structures 102 are respectively formed on the surface of a p-type silicon semiconductor substrate 101, and each element active region is formed by these field shield element isolation structures 102. Define.

Next, thermal oxidation is performed on the surface of silicon semiconductor substrate 101 to form gate oxide film 103. Further, a polycrystalline silicon film is deposited and formed on the entire surface of the gate oxide film 103 by a vacuum deposition method such as CVD, and then patterned by photolithography and subsequent dry etching to form a gate electrode on the gate oxide film 103. 104, and each source diffusion layer 10
5 and the source wiring layer 10 while leaving the polycrystalline silicon film in a predetermined pattern on the field shield element isolation structure 102 in the vicinity of the part to be each drain diffusion layer 106.
7 and the drain electrode layer 151 are formed.

Next, C is applied to cover the gate electrode 104.
A silicon oxide film is deposited and formed on the entire surface by a vacuum evaporation method such as VD, and then the entire surface of the silicon oxide film is anisotropically dry-etched by RIE or the like, so that the silicon oxide film is formed only on the upper surface and side surfaces of the gate electrode 104. A cap insulating film 113 and a sidewall insulating film 114 are formed to cover the gate electrode 104 except for the above.

Subsequently, arsenic (As) ions are implanted into the silicon semiconductor substrate 101 by using the cap insulating film 113 of the gate electrode 104 as a mask to form nMOSFE.
Source diffusion layer 105 and drain diffusion layer 10 of T161
6 is formed.

Next, as shown in FIG. 50B, a silicon oxide film is deposited on the entire surface including the source wiring layer 107 and the drain electrode layer 151 by a vacuum deposition method such as CVD to form an interlayer insulating film. Subsequently, the interlayer insulating film 1
08 is subjected to photolithography and subsequent dry etching or the like to expose the surfaces of the source diffusion layer 105 and the drain diffusion layer 106 by piercing the interlayer insulating film 108 on the source diffusion layer 105 and the drain diffusion layer 106. The contact holes 109 and 110 are formed, and the interlayer insulating film 108 is similarly formed on the source wiring layer 107 and the drain electrode layer 151 to expose the surfaces of the source wiring layer 107 and the drain electrode layer 151.
21 and 152 are respectively formed.

Next, as shown in FIG. 51A, a metal film made of aluminum is formed on the entire surface including the contact holes 109, 110, 121, and 152 by a vacuum deposition method such as a sputtering method. By performing photolithography and subsequent dry etching on the film, the contact hole 109 and the contact hole 121 are filled, and a metal wiring layer 122 extending from the contact hole 109 to the contact hole 121 on the interlayer insulating film 108;
Filling the contact hole 110 and the contact hole 152,
On the interlayer insulating film 108, a metal wiring layer 153 extending from the contact hole 110 to the contact hole 152 is formed in a predetermined pattern.

At this time, one end of the metal wiring layer 122 is electrically connected to the source diffusion layer 105 and the other end is electrically connected to the source wiring layer 107. Therefore, the source diffusion layer 105 and the source wiring are connected via the metal wiring layer 122. The layer 107 is electrically connected. On the other hand, one end of the metal wiring layer 153 is electrically connected to the drain diffusion layer 106, and the other end is electrically connected to the drain electrode layer 151. Therefore, the drain diffusion layer 105 and the drain electrode layer 151 are connected via the metal wiring layer 153. Electrically connected.

Next, as shown in FIG. 52A, an interlayer insulating film 124 is formed by depositing a silicon oxide film over the entire surface by a vacuum deposition method such as CVD so as to cover the metal wiring layer 122 and the metal wiring layer 153. I do.

Subsequently, a polycrystalline silicon film 163 is formed on the interlayer insulating film 124 by the CVD method, and a photoresist 164 is applied on the polycrystalline silicon. continue,
This photoresist 164 corresponds to a region R indicated by oblique lines in FIG.
Photoresist 1 of other parts so that it remains only in
Remove 64. Then, using this photoresist 164 as a mask, the polycrystalline silicon film 1 is formed by ion implantation.
Impurities such as phosphorus, boron and arsenic are introduced into 63 so as to impart conductivity to the portion of the polycrystalline silicon film 163 where ions are implanted, that is, the portion excluding the region R.

At this time, the polycrystalline silicon film 163 has
Two island-shaped conductive regions which are electrically separated from each other by the region R are formed. That is, as shown in FIG. X, one of these island-shaped conductive regions becomes a wiring pattern 125 ′ of a predetermined pattern facing the source wiring layer 107 via the interlayer insulating film 124 on the metal wiring layer 122. The other is on the metal wiring layer 153 and the interlayer insulating film 124 is formed.
The electrode layer 154 'has a predetermined pattern facing the drain electrode layer 151 through the electrode layer 154'. Thus, the wiring layer 125 '
And the electrode layer 154 'are the same layer (polycrystalline silicon layer 16).
3), the patterned metal wiring layers 125 and metal electrode layers 15 shown in the seventh embodiment are formed.
4 plays a role of reducing the level difference portion.

Here, the source wiring layer 107 and the wiring layer 12 opposed to each other via the interlayer insulating films 108 and 124 are provided.
The capacitor C is constituted by 5 ', and the capacitor 162 of the DRAM is constituted by the drain electrode layer 151 and the electrode layer 154' opposed to each other via the interlayer insulating films 108 and 124. Here, in the capacitor 162, the drain electrode layer 151 functions as a storage node electrode, and the electrode layer 154 'functions as a cell plate electrode.

Thereafter, as shown in FIG. 52B, the photoresist 164 is removed, and a silicon oxide film and a silicon nitride film are sequentially deposited on the entire surface including the wiring layer 125 'and the electrode layer 154' by a vacuum deposition method. In this way, an insulating film 126 is formed, and a predetermined post-process is performed to complete the DRAM of the eighth embodiment.

As described above, the DR according to the eighth embodiment is described.
According to the AM manufacturing method, a sufficient noise margin is secured because the electric resistance value of the source diffusion layer 105 is relatively large, and a capacitor C having a large electric capacitance is provided between the silicon semiconductor substrate 101 and the source diffusion layer 105. As a result, the delay of the signal propagation time is suppressed, and the speed of the logic operation is increased.

[0296]

EXAMPLES Hereinafter, specific examples in which the effects are confirmed using the CMOS inverter according to the first embodiment and the CMOS inverter manufactured according to the sixth embodiment will be described.

Example 1 First, Example 1 will be described. Here, the CMOS inverter of the fourth embodiment was examined.

Specifically, the nM of this CMOS inverter
For the OSFET 31, the width of the gate electrode 104 is set to 4
μm, the depth of the source diffusion layer 105 is 0.25 μm,
The resistivity was set to 0.01Ωcm and Rs ≒ 100Ω.
The rising frequency fr of the input logic signal is 1
It became about 0 GHz. For Cbs, Cbs>
Since it suffices if the value satisfies 0.16 pF, the area of the metal wiring layer 125 facing the metal wiring layer 122 on the field shield element isolation structure 102 is set to 30 μm ² .
This area can be easily secured.

[0299] Also, regarding the pMOSFET 132,
The width of the gate electrode 104 is 10 μm, and the source diffusion layer 1
05 was 0.4 μm, the resistivity was 0.03 Ωcm, and RsＲ75Ω. Further, the rising frequency fr of the input logical signal was about 12 GHz. Cbs
Since it suffices that the value satisfy Cbs> 0.18 pF, the area of the metal wiring layer 125 facing the metal wiring layer 122 on the field shield element isolation structure 102 is set to 34 μm ² . This area can be easily secured.

When a rising (or falling) logic signal was input using a CMOS inverter having the above specific conditions, the signal propagation delay time was longer than that of a conventional CMOS inverter having no capacitor C. It was confirmed that the operation was greatly reduced and the operation was performed at high speed. At this time, the presence of Rs, which is a large value from a DC point of view, did not show a decrease in the noise margin.

As described above, according to the CMOS inverter of the fourth embodiment, it has been found that the operation speed can be improved while securing a sufficient noise margin.

(Embodiment 2) Next, Embodiment 2 will be described. Here, the CM manufactured in the sixth embodiment is used.
The OS inverter was examined.

Specifically, the nM of this CMOS inverter
For the OSFET 31, the width of the gate electrode 104 is set to 4
μm, the depth of the source diffusion layer 105 is 0.25 μm,
The resistivity was set to 0.1 Ωcm and Rs ≒ 1 kΩ. The rising frequency fr of the input logic signal is 10
It became about GHz. For Cbs, Cbs> 0.
It is sufficient if the value satisfies 016 pF, and the area of the bottom insulating film 144 formed on the bottom of the source diffusion layer 105 is
It was m ^2. This area can be easily secured.

[0304] Also, regarding the pMOSFET 132,
The width of the gate electrode 104 is 10 μm, and the source diffusion layer 1
05 was 0.3 μm, the resistivity was 0.2 Ωcm, and Rs ≒ 670 Ω. Further, the rising frequency fr of the input logical signal was about 12 GHz. Cbs
Since it suffices that the value satisfy Cbs> 0.02 pF, the area of the bottom insulating film 144 formed on the bottom of the source diffusion layer 105 is set to 5 μm ² . This area can be easily secured.

When a rising (or falling) logic signal is inputted using a CMOS inverter having the above specific conditions, the signal propagation delay is shorter than that of a conventional CMOS inverter having no bottom insulating film 144. It was confirmed that time was greatly reduced and high-speed operation was performed. At this time, the presence of Rs, which is a large value from a DC point of view, did not show a decrease in the noise margin.

As described above, according to the CMOS inverter of the sixth embodiment, it has been found that the operation speed can be improved while securing a sufficient noise margin.

[0307]

According to the present invention, a plurality of gate electrodes can be formed without impairing the element isolation function when a field shield element isolation structure which does not cause inconvenience such as bird's beak is used as the element isolation structure. In this case, it is possible to achieve the miniaturization of the gate electrode accompanying the reduction in the element size without causing the shape abnormality of the gate electrode.

Further, according to the present invention, a semiconductor device which performs a high-speed operation while sufficiently securing a noise margin and reducing a signal propagation delay time while promoting further higher integration of the semiconductor device is realized. It is possible to do.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing a MOS transistor according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a MOS transistor according to the first embodiment of the present invention.

FIG. 3 is a schematic sectional view showing another example of the MOS transistor according to the first embodiment of the present invention.

FIG. 4 is a schematic plan view and a connection diagram illustrating an example in which the MOS transistor according to the first embodiment of the present invention is applied to a bootstrap circuit.

FIG. 5 is a schematic plan view and a connection diagram illustrating an example in which the MOS transistor according to the first embodiment of the present invention is applied to a bootstrap circuit.

FIG. 6 is a connection diagram illustrating an example in which a MOS transistor according to the first embodiment of the present invention is applied to an input protection circuit.

FIG. 7 is a schematic cross-sectional view showing a method for manufacturing the MOS transistor according to the first embodiment of the present invention in the order of steps.

FIG. 8 is a schematic cross-sectional view showing a method of manufacturing the MOS transistor according to the first embodiment of the present invention in the order of steps, following FIG. 7;

FIG. 9 is a schematic cross-sectional view showing a manufacturing method of the MOS transistor according to the first embodiment of the present invention in the order of steps, following FIG. 8;

FIG. 10 is a schematic plan view showing a photolithography step when forming an electrode film having a gate electrode as a component.

FIG. 11 is a schematic cross-sectional view showing a state where a formation portion is shifted when a contact hole for establishing conduction with an impurity diffusion layer is formed.

FIG. 12 shows M in a modification of the first embodiment of the present invention.
FIG. 3 is a schematic plan view showing an OS transistor.

FIG. 13 is a schematic cross-sectional view showing a method for manufacturing the MOS transistor according to the first embodiment of the present invention in the order of steps.

FIG. 14 is a schematic cross-sectional view showing a manufacturing method of the MOS transistor according to the first embodiment of the present invention in the order of steps, following FIG. 13;

FIG. 15 is a schematic cross-sectional view showing a method of manufacturing the MOS transistor according to the first embodiment of the present invention in the order of steps, following FIG. 14;

FIG. 16 is a schematic plan view showing a photolithography step when forming an electrode film having a gate electrode as a component.

FIG. 17 is a schematic plan view showing a MOS transistor according to a second embodiment of the present invention.

FIG. 18 is a schematic sectional view showing a MOS transistor according to a second embodiment of the present invention.

FIG. 19 is a schematic sectional view showing another example of the MOS transistor according to the second embodiment of the present invention.

FIG. 20 is a schematic cross-sectional view showing a method for manufacturing a MOS transistor according to the second embodiment of the present invention in the order of steps.

FIG. 21 is a schematic cross-sectional view showing a method of manufacturing the MOS transistor according to the second embodiment of the present invention in the order of steps, following FIG. 20;

FIG. 22 is a schematic cross-sectional view showing a manufacturing method of the MOS transistor according to the second embodiment of the present invention in the order of steps, following FIG. 21;

FIG. 23 is a schematic cross-sectional view showing a method of manufacturing the MOS transistor according to the second embodiment of the present invention in the order of steps, following FIG. 22;

FIG. 24 is a schematic plan view showing a photolithography step when forming an electrode film having a gate electrode as a constituent element.

FIG. 25 is a schematic plan view showing a silicon signature according to the third embodiment of the present invention.

FIG. 26 is a schematic cross-sectional view showing a silicon signature according to the third embodiment of the present invention.

FIG. 27 is a schematic cross-sectional view showing a method for manufacturing a silicon signature according to the third embodiment of the present invention in the order of steps.

FIG. 28 is a schematic cross-sectional view showing a method of manufacturing a silicon signature according to the third embodiment of the present invention in the order of steps, following FIG. 27;

FIG. 29 is a schematic cross-sectional view showing a method of manufacturing the silicon signature according to the third embodiment of the present invention in the order of steps, following FIG. 28;

FIG. 30 is a schematic plan view showing a photolithography step when forming a gate electrode and the like.

FIG. 31 is a schematic sectional view showing a CMOS inverter according to a fourth embodiment of the present invention.

FIG. 32 is an equivalent circuit diagram showing a CMOS inverter according to a fourth embodiment of the present invention and an nMOSFET which is a component thereof.

FIG. 33 is a characteristic diagram illustrating a frequency characteristic of a ground impedance Zs expressed as a parallel connection of Rs and Cbs.

FIG. 34 is a waveform diagram showing a rising waveform of a logic signal.

FIG. 35 is a schematic sectional view showing another example of the CMOS inverter according to the fourth embodiment of the present invention.

FIG. 36 is a schematic sectional view showing the method for manufacturing the CMOS inverter according to the fourth embodiment of the present invention.

FIG. 37 is a schematic sectional view, following FIG. 36, illustrating the method for manufacturing the CMOS inverter according to the fourth embodiment of the present invention.

FIG. 38 is a schematic sectional view, following FIG. 37, illustrating the method for manufacturing the CMOS inverter according to the fourth embodiment of the present invention.

FIG. 39 is a schematic cross-sectional view showing a method of manufacturing the CMOS inverter according to the fourth embodiment of the present invention, following FIG. 38;

FIG. 40 is a schematic sectional view, following FIG. 39, illustrating the method for manufacturing the CMOS inverter according to the fourth embodiment of the present invention.

FIG. 41 is a schematic cross-sectional view showing a method for manufacturing the CMOS inverter according to the fourth embodiment of the present invention, following FIG. 40;

FIG. 42 is a schematic sectional view showing a CMOS inverter according to a fifth embodiment of the present invention.

FIG. 43 is a schematic sectional view showing the method for manufacturing the CMOS inverter according to the sixth embodiment of the present invention.

FIG. 44 is a schematic cross-sectional view showing a method for manufacturing the CMOS inverter according to the sixth embodiment of the present invention, following FIG. 43;

FIG. 45 is a schematic cross-sectional view showing a method of manufacturing the CMOS inverter according to the sixth embodiment of the present invention, following FIG. 44;

FIG. 46 is a schematic sectional view, following FIG. 45, illustrating the method for manufacturing the CMOS inverter according to the sixth embodiment of the present invention.

FIG. 47 is a schematic cross-sectional view showing a method of manufacturing the CMOS inverter according to the sixth embodiment of the present invention, following FIG. 46;

FIG. 48 is a schematic cross-sectional view showing a method of manufacturing the CMOS inverter according to the sixth embodiment of the present invention, following FIG. 47;

FIG. 49 is a schematic cross-sectional view showing a method of manufacturing the CMOS inverter according to the sixth embodiment of the present invention, following FIG. 48;

FIG. 50 is a schematic cross-sectional view showing the method for manufacturing the DRAM according to the seventh embodiment of the present invention.

FIG. 51 is a schematic cross-sectional view showing a method of manufacturing the DRAM according to the seventh embodiment of the present invention, following FIG. 50;

FIG. 52 is a schematic sectional view showing the method for manufacturing the DRAM according to the eighth embodiment of the present invention;

FIG. 53 is a schematic plan view showing the method for manufacturing the DRAM according to the eighth embodiment of the present invention.

[Description of Signs] 1,51,101 Silicon semiconductor substrate 2,52,102,141 Field shield element isolation structure 3,4,53,54 104 Gate electrode 5,55 Impurity diffusion layer 6,7,56 Side electrode 8 , 58, 103 Gate oxide film 11, 12 Electrode film 13, 66, 96, 114 Side wall insulating film 14, 67, 97, 113 Cap insulating film 15, 68 Interlayer insulating film 16, 69, 98 Contact hole 17, 70 Wiring layer 21a to 21c, 32, 61, 75, 93 Silicon oxide film 22, 62, 102b, 141b Shield plate electrode 23, 71 Pad polycrystalline silicon film 31, 64, 65, 72, 74, 163 Polycrystalline silicon film 41, 81 Photomask 43, 45, 46, 47, 48, 83, 85, 86 Pattern 44, 84 Resist pattern 73 Dielectric film 90 Trench type element isolation structure 94 Thermal oxide film 99 Silicon nitride film 105 Source diffusion layer 106 Drain diffusion layer 107 Source wiring layer 108, 124 Interlayer insulation film 109, 110, 121, 152 Contact hole 111 P-type well Diffusion layer 112 N-type well diffusion layer 122, 123, 125, 153 Metal wiring layer 125 'Wiring layer 126 Insulating film 131 nMOSFET 132 pMOSFET 142 Side wall 143 Depression 144 Bottom insulating film 151 Drain electrode layer 154' Electrode layer 162 Capacitor 164 Photo Resist

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/78 H01L 29/78 301X 21/8247 301R 29/788 371 29/792

Claims (60)

[Claims] 1. A semiconductor comprising a transistor having a gate electrode in a device active region defined by a device isolation structure on a semiconductor substrate and a pair of impurity diffusion layers functioning as a source / drain on both sides of the gate electrode. In the device, a first conductive film which is patterned in a band shape on the element active region via a gate insulating film and functions as the gate electrode, and a boundary portion between the element isolation structure and the element active region, A band-shaped pattern is formed so as to cover at least a portion of the element active region where the impurity diffusion layer is formed at a portion opposed to and opposed to the first conductive film;
A second conductive film that is capacitively opposed to the lower impurity diffusion layer via the gate insulating film, wherein the first conductive film and the second conductive film are integrally formed; A semiconductor device characterized by the above-mentioned. 2. The semiconductor device according to claim 1, wherein the element isolation structure is a field shield element isolation structure in which a shield plate electrode is buried in an insulating film. 3. The semiconductor device according to claim 2, wherein a potential of said shield plate electrode and a potential of said conductive film are set to values different from each other. 4. The semiconductor device according to claim 1, wherein said element isolation structure is a trench-type element isolation structure in which an insulating film is buried in a groove formed in said semiconductor substrate. 5. The semiconductor device according to claim 1, wherein said first and second conductive films are connected at one end thereof. 6. The semiconductor device according to claim 1, wherein said first and second conductive films have a two-layer conductive film structure. 7. A semiconductor device having an element isolation structure for defining an element active region on a semiconductor substrate, wherein at least one strip-shaped conductive film is formed in a pattern on the element active region via an insulating film. Covering at least a portion of the boundary between the element isolation structure and the element active region, which is opposed to the conductive film formed in the element active region, at least over the element active region via the insulating film; A semiconductor device, wherein the other conductive film is formed as described above. 8. The conductive film formed in the element active region and the conductive film formed in the boundary portion are electrically connected at one end thereof, and both are set to the same potential. The semiconductor device according to claim 7, wherein: 9. The semiconductor device according to claim 7, wherein the element isolation structure is a field shield element isolation structure in which a shield plate electrode is embedded in an insulating layer. 10. The device isolation structure according to claim 7, wherein the device isolation structure is a trench-type device isolation structure in which an insulating film is buried in a groove formed in the semiconductor substrate.
3. The semiconductor device according to claim 1. 11. The semiconductor device according to claim 9, wherein a potential of said shield plate electrode and a potential of said conductive film formed at said boundary portion are set to values different from each other. 12. The second conductive film formed in the element active region is a gate electrode of a transistor, and has a source diffusion layer and a drain diffusion layer in a surface region of the semiconductor substrate on both sides of the gate electrode. The source diffusion layer is formed in a surface region of the semiconductor substrate in the element active region where the boundary region exists, and at least a part of the conductive film in the boundary region connected to the gate electrode is insulated from the insulating layer. 12. The semiconductor device according to claim 7, wherein the source diffusion layer and the source diffusion layer are capacitively coupled to each other through a film, and the source diffusion layer and the drain diffusion layer have the same potential. 13. The semiconductor device according to claim 1. 13. The conductive film having two patterns formed on the element active region with the insulating film interposed therebetween, wherein one of the conductive films and one of the conductive films and the boundary portion adjacent to the conductive film are formed. 13. The semiconductor device according to claim 7, wherein the formed conductive film is connected to the conductive film, and the other conductive film is connected to the conductive film formed at the boundary portion close to the conductive film. The semiconductor device according to claim 1. 14. A semiconductor device comprising: a pair of impurity diffusion layers in which impurities are introduced into a surface region of the semiconductor substrate on both sides of the conductive film formed in the element active region; at least one of the impurity diffusion layers is 14. The semiconductor device according to claim 7, wherein the conductive film is formed in a surface region of the semiconductor substrate between the conductive film and the conductive film formed at the boundary portion adjacent to the conductive film. Semiconductor device. 15. The semiconductor device according to claim 7, wherein said conductive film has a two-layer structure. 16. A field shield element isolation structure in which a first conductive film is embedded in a first insulating film is formed in an element isolation region on a semiconductor substrate, and an element active region is defined on the semiconductor substrate. A first step, a second step of forming a second insulating film in the element active region, and a second step of forming a second conductive film on the field shield element isolation structure and on the second insulating film. Step 3; patterning the second conductive film and the second insulating film to form at least the device active region on the device active region and at a boundary between the device active region and the field shield device isolation structure. The second conductive film and the second insulating film are processed into a band-shaped pattern, and the other conductive film and the other insulating film are formed near the longitudinal direction of the pattern of the second conductive film formed on the element active region. Second And a fourth step of forming each pattern so that the pattern of the conductive film extends. 17. The method according to claim 16, wherein the potential of the first conductive film and the potential of the second conductive film at the boundary portion are set to different values. . 18. The pattern of the second conductive film formed on the element active region in the fourth step, and a pattern formed on at least the element active region at the boundary portion close to the second conductive film. 18. The method of manufacturing a semiconductor device according to claim 16, wherein the pattern of the second conductive film to be formed is integrally formed at one end of each, and both are set to the same potential. 19. The method according to claim 19, wherein the second conductive film formed in the element active region is used as a gate electrode of a transistor. After the fourth step, a source diffusion layer is formed in a surface region of the semiconductor substrate on both sides of the gate electrode. And a fifth step of forming a drain diffusion layer, wherein the source diffusion layer is formed in a surface region of the semiconductor substrate in the element active region where the boundary part exists, and the boundary part connected to the gate electrode At least a portion of the second conductive film is opposed to the source diffusion layer via the second insulating film to capacitively couple the two, so that the source diffusion layer and the drain diffusion layer have the same potential. The method of manufacturing a semiconductor device according to claim 18, wherein: 20. In the fourth step, two patterns of the second conductive film are formed in the element active region with the second insulating film interposed therebetween, and each pattern of the second conductive films is formed. 20. The method of manufacturing a semiconductor device according to claim 18, wherein a pattern and a pattern of the second conductive film at the boundary portion adjacent to the pattern are integrally formed. 21. In the third step, the second conductive film, the third insulating film, and the third conductive film are sequentially formed on the second insulating film, and in the fourth step, The third conductive film, the third conductive film;
20. The method according to claim 18, wherein the insulating film, the second conductive film, and the second insulating film are patterned. 22. In the fourth step, at least the pattern of the second and third conductive films formed on the element active region and at least the boundary portion close to the second and third conductive films. 22. The method of manufacturing a semiconductor device according to claim 21, wherein the patterns of the second and third conductive films formed in the element active region are integrally formed, and both are set to the same potential. 23. In the fourth step, two patterns of the second and third conductive films are formed in the element active region, and the patterns of the second and third conductive films are respectively formed. The second at the boundary portion close to
22. The method of manufacturing a semiconductor device according to claim 21, wherein a pattern of the third conductive film is formed integrally with the third conductive film. 24. After forming a groove in an element isolation region on a semiconductor substrate, a first insulating film is buried in the groove to form a trench-type element isolation structure, and an element active region is defined on the semiconductor substrate. A second step of forming a second insulating film in the element active region; and a third step of forming a conductive film on the trench-type element isolation structure and on the second insulating film. Patterning the conductive film and the second insulating film,
A fourth step of processing the conductive film and the second insulating film into a band-shaped pattern on at least the element active region on the element active region and at a boundary portion between the element active region and the trench-type element isolation structure; Forming a pair of impurity diffusion layers in a surface region of the semiconductor substrate on both sides of the conductive film on the element active region, and forming at least a part of the conductive film and the impurity diffusion layer existing at the boundary portion by the second 5. A method of manufacturing a semiconductor device, comprising: a fifth step of facing the semiconductor device via the second insulating film. 25. A pattern of the conductive film formed on the element active region in the fourth step, and a pattern of the conductive film formed on at least the element active region at the boundary portion adjacent to the conductive film. 25. The method according to claim 24, wherein the semiconductor device and the semiconductor device are integrally formed at one end of the semiconductor device, and the semiconductor device and the semiconductor device have the same potential. 26. The semiconductor substrate of the element active region where the boundary region exists, wherein the conductive film formed in the element active region is used as a gate electrode of a transistor, and a source diffusion layer, which is one of the pair of impurity diffusion layers, has the boundary portion. Formed in the surface region of the conductive layer, at least a part of the conductive film at the boundary portion connected to the gate electrode is opposed to the source diffusion layer via the second insulating film, and both are capacitively coupled, 26. The method of manufacturing a semiconductor device according to claim 24, wherein the source diffusion layer and a drain diffusion layer that is the other of the pair of impurity diffusion layers have the same potential. 27. In the fourth step, two patterns of the conductive film are formed in the element active region with the second insulating film interposed therebetween, and each of the patterns of the conductive film is formed in close proximity to the pattern. 26. The pattern of the conductive film at the boundary portion is integrally formed.
Or a method for manufacturing a semiconductor device according to item 26. 28. In the third step, the conductive film, the third insulating film, and the upper conductive film are sequentially formed on the second insulating film. In the fourth step, the upper conductive film, 28. The semiconductor device according to claim 25, wherein the third insulating film, the conductive film, and the second insulating film are patterned.
13. The method for manufacturing a semiconductor device according to the above item. 29. In the fourth step, a pattern of the upper conductive film and the conductive film formed on the element active region, and at least the device at the boundary portion close to the upper conductive film and the conductive film. 29. The method of manufacturing a semiconductor device according to claim 28, wherein a pattern of the second and third conductive films formed in an active region is integrally formed, and both are set to the same potential. 30. In the fourth step, the pattern of the upper conductive film and the conductive film is formed in the element active region by two times.
29. The method according to claim 28, wherein each of the upper conductive film and the pattern of the conductive film and the pattern of the upper conductive film and the pattern of the conductive film at the boundary portion adjacent thereto are integrally formed. The manufacturing method of the semiconductor device described in the above. 31. A semiconductor device provided with an element isolation structure for defining an element active region on a semiconductor substrate, wherein: a first insulating film formed in the element active region; And an impurity diffusion layer formed on the semiconductor substrate in a boundary region of the semiconductor device, and a first conductive film formed on the first insulating film. A semiconductor device, wherein an impurity diffusion layer is disposed to face the first insulating film with the first insulating film interposed therebetween. 32. A field shield element isolation structure in which a shield plate electrode is buried in a second insulating film.
3. The semiconductor device according to claim 1. 33. The device according to claim 33, wherein the first conductive film is formed on at least a part of the second insulating film and on the first insulating film in a boundary region between the element isolation structure and the element active region. 33. The semiconductor device according to claim 31, wherein: 34. The device active region further includes a second conductive film formed on the first insulating film, and a source diffusion formed on the semiconductor substrate on both sides of the second conductive film. A layer and a drain diffusion layer are provided, the second conductive film is connected to the first conductive film, and the first conductive film is formed in the boundary region on the source diffusion layer side. Claims 3 to 3
4. The semiconductor device according to any one of 3. 35. The semiconductor device according to claim 34, wherein the source diffusion layer and the drain diffusion layer are in contact in the semiconductor substrate. 36. The device isolation structure according to claim 31, wherein the device isolation structure is a trench-type device isolation structure in which a third insulating film is embedded in a groove formed in an element isolation region of the semiconductor substrate. 3. The semiconductor device according to claim 1. 37. The first conductive film is formed on the third insulating film and at least a part of a boundary region between the element isolation structure and the element active region and on the first insulating film. 37. The semiconductor device according to claim 36, wherein: 38. The device active region further includes a second conductive film formed on the first insulating film, and a source diffusion formed on the semiconductor substrate on both sides of the second conductive film. A layer and a drain diffusion layer are provided, the second conductive film is connected to the first conductive film, and the first conductive film is formed in the boundary region on the source diffusion layer side. The semiconductor device according to claim 36 or 37, wherein 39. A conductive layer provided on a surface of the semiconductor substrate in an element active region defined on the semiconductor substrate via an insulating layer, and a pair of impurities provided on the semiconductor substrate on both sides of the conductive layer. Having a source diffusion layer and a drain diffusion layer that are diffusion layers, a first wiring layer electrically connected to the source diffusion layer, and a second wiring layer capacitively coupled to the first wiring layer A semiconductor device characterized by the above-mentioned. 40. The semiconductor device according to claim 39, wherein the second wiring layer is a power supply wiring layer or a ground wiring layer. 41. The semiconductor device according to claim 39, further comprising: a lower electrode layer electrically connected to the drain diffusion layer; and an upper electrode layer capacitively coupled to the lower electrode layer. . 42. The first wiring layer extends over an element isolation structure defining the element active region, and the first wiring layer and the second wiring layer are connected via an insulating layer. The semiconductor device according to any one of claims 39 to 41, wherein the semiconductor device is arranged to face the element isolation structure. 43. The semiconductor device according to claim 39, wherein said element isolation structure is a field shield element isolation structure having a shield plate electrode. 44. The semiconductor device according to claim 39, wherein said element isolation structure is a field oxide film formed by a LOCOS method. 45. The device isolation structure according to claim 39, wherein the device isolation structure is a trench-type device isolation structure in which an insulating film is buried in a groove formed in an element isolation region on the semiconductor substrate. The semiconductor device according to claim 1. 46. A field shield element isolation structure provided with a shield plate electrode formed on a semiconductor substrate, and an insulating layer on a surface of the semiconductor substrate in an element active region defined and surrounded by the field shield element isolation structure. A pair of impurity diffusion layers provided on the semiconductor substrate on both sides of the conductive layer; and a shield electrically connected to one of the pair of impurity diffusion layers. A semiconductor device having a wiring layer capacitively coupled to a plate electrode. 47. A semiconductor device according to claim 47, wherein the pair of impurity diffusion layers are a source diffusion layer and a drain diffusion layer of a transistor having the conductive layer as a gate electrode, and the wiring layer is electrically connected to the source diffusion layer. 47. The semiconductor device according to claim 46, wherein: 48. A step of forming an element isolation structure in an element isolation region on a semiconductor substrate; and a step of forming a first insulating layer on a surface of the semiconductor substrate in an element active region surrounded by the element isolation structure. Forming a conductive layer of a predetermined pattern on the first insulating layer; forming a pair of impurity diffusion layers by introducing impurities into the semiconductor substrate on both sides of the conductive layer using the conductive layer as a mask; Forming a recess by anisotropically etching the semiconductor substrate in a region where at least one of the pair of impurity diffusion layers is present, and forming a part of the one impurity diffusion layer only on a side wall surface of the recess. Leaving a step, forming a second insulating layer only on the bottom surface of the concave portion, depositing a semiconductor material in the concave portion, and part of the one impurity diffusion layer existing only on the side wall surface of the concave portion, The said Embedding the second insulating layer. 49. The transistor according to claim 49, wherein the pair of impurity diffusion layers are a source diffusion layer and a drain diffusion layer of a transistor having the conductive layer as a gate electrode, and the second insulating layer is buried in the source diffusion layer. 49. The method of manufacturing a semiconductor device according to claim 48. 50. The method according to claim 48, wherein the element isolation structure is a field shield element isolation structure having a shield plate electrode. 51. The method according to claim 48, wherein the element isolation structure is a field oxide film formed by a LOCOS method. 52. The device isolation structure according to claim 48, wherein the device isolation structure is a trench-type device isolation structure in which an insulating film is buried in a groove formed in an element isolation region on the semiconductor substrate. 13. The method for manufacturing a semiconductor device according to item 5. 53. An element active region defined on a semiconductor substrate by an element isolation structure, a first impurity diffusion layer formed on the semiconductor substrate at a boundary region between the element isolation structure and the element active region, A first insulating film formed on the first impurity diffusion layer in the boundary region; and a first insulating film formed on the first insulating film via the first insulating film. A first electrode formed so as to face the second electrode, and a second electrode formed on the element active region of the semiconductor substrate.
An insulating film, a second electrode formed on the second insulating film, and a pair of second impurity diffusion layers formed on the semiconductor substrate on both sides of the second electrode; One of the pair of second impurity diffusion layers is connected to the first impurity diffusion layer in the semiconductor substrate, and the first electrode and the second electrode are connected. A semiconductor device characterized by the above-mentioned. 54. The semiconductor device according to claim 53, wherein the element isolation structure is a field shield element isolation structure in which a shield plate electrode is embedded in an insulating film. 55. The semiconductor device according to claim 53, wherein the element isolation structure is a trench-type element isolation structure in which an insulating film is embedded in a groove formed in the semiconductor substrate. 56. The semiconductor device according to claim 54, wherein a potential of said shield plate electrode and a potential of said first electrode are set to values different from each other. 57. A field shield element isolation structure in which a first conductive film is embedded in a first insulating film is formed in an element isolation region on a semiconductor substrate, and an element active region is defined on the semiconductor substrate. A first step, a second step of forming a second insulating film in the element active region, and a second conductive film and a low etching rate on the field shield element isolation structure and the second insulating film. The third
A third step of sequentially forming an insulating film, and patterning the third insulating film, the second conductive film, and the second insulating film to form a pattern on the element active region and the element active region, The third insulating film, the second conductive film, and the second insulating film are processed into a band-shaped pattern at least in the element active region at a boundary portion with the field shield element isolation structure, and are formed on the element active region. A fourth step of forming each pattern so that another pattern of the second conductive film extends in the vicinity of the formed pattern of the second conductive film along the longitudinal direction; Forming a fourth insulating film having a low etching rate on the side surface of the conductive film. 58. The second conductive film formed in the element active region is used as a gate electrode of a transistor. After the fifth step, a source diffusion layer is formed in a surface region of the semiconductor substrate on both sides of the gate electrode. And a sixth step of forming a drain diffusion layer; and forming an interlayer insulating film so as to cover the third insulating film, the second conductive film, the second insulating film, and the fourth insulating film. 58. The semiconductor device according to claim 57, further comprising: a seventh step; and an eighth step of forming a contact hole communicating with the source diffusion layer and / or the drain diffusion layer in the interlayer insulating film. Manufacturing method. 59. The method according to claim 58, wherein in the eighth step, the contact hole is formed such that a part of the third insulating film and / or the fourth insulating film is exposed. 13. The method for manufacturing a semiconductor device according to item 5. 60. The source diffusion layer is formed in a surface region of the semiconductor substrate in the element active region where the boundary region exists, and at least one of the second conductive films at the boundary region connected to the gate electrode is provided. 60. A part is opposed to the source diffusion layer via the second insulating film to couple the two capacitively, so that the source diffusion layer and the drain diffusion layer have the same potential. 13. The method for manufacturing a semiconductor device according to item 5.