JPH10187767A - Parameterized hdl describing method, logic synthesizer, and medium recording logic synthesizing program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a parameterized HDL describing method reutilizable at the next time of design, and to hide described contents, by providing a step for setting a constant value and a step for describing processing for transforming constant values to a constant table. SOLUTION: An HDL description 401 sets the values of respective parameters through parameter sentences and respectively sets '7' to input bit width (InBits), '5' to constant coefficient bit width (CoefBits), '9' to output bit width (OutBits) and '23' to a constant coefficient value (CoefVal). In an HDL description 403, constant calculation processing for calculating CSD arrangement from the constant coefficient value is described. A first comment sentence 'constant-gen- begin' shows it is constant calculation processing to a final comment sentence 'constant-gen-end'. At the part of 'omisson' in the HDL description 403, an HDL description expressing a hardware with the constant coefficient value as its input and the constant table as its output is described.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a description method of a hardware description language (HDL) and a logic synthesis device for synthesizing a logic circuit from the HDL description, and more particularly to a logic having various functions and configurations by designating parameters. The present invention relates to a parameterized HDL description method capable of synthesizing a circuit, a logic synthesis device, and a medium recording a logic synthesis program.

[0002]

2. Description of the Related Art In recent years, as semiconductor integrated circuits have become denser and more multifunctional, the circuit scale has tended to increase, and the time required for circuit design has also increased. One of the methods for reducing the time required for the circuit design is to reuse an already designed circuit. The larger the circuit to be reused, the greater the effect of shortening the design period. However, each design always has its own structure and function, and the reusable circuit parts are only those having a common structure and function. Therefore, there is a problem that it is difficult to reuse the entire large scale circuit. As one of techniques for solving this problem, a parameterized HDL description has been developed.

The parameterized HDL description is an HDL description that expresses a variety of circuit configurations and functions as parameters, and by setting these parameters, it is possible to synthesize various circuits corresponding to the parameters. . If the variety of circuits is examined and the design is performed as a parameterized HDL description, the possibility of reusing the design can be greatly improved. At present, a parameterized HDL having parameters such as a bit width and the number of words has been developed and is actually used for circuits having regularity such as an arithmetic unit having a bit slice structure and a memory.

However, a parameterized HDL has not been created for a circuit having a structure that changes irregularly with parameters. Conventionally, a circuit having such a structure is processed in the following procedure.

(1) An HDL description corresponding to a general-purpose hardware configuration is prepared as a template.

(2) Randomly changing items are calculated by a program and converted into parameters that directly specify the hardware configuration (hereinafter, this conversion processing is referred to as constant calculation processing).

(3) A parameter for directly specifying a hardware configuration is embedded in an HDL description template and output as a final HDL description.

An HDL description generation program that performs the above-described processing generates an HDL description based on designated parameters.
A DL description has been generated.

FIG. 7 is a flowchart showing a design procedure when a conventional HDL description generation program is used. First, the parameters and the template of the HDL description are input to the HDL description generation program, and the generation program inserts the parameters into the HDL description template to generate the H
A DL description is generated (S301). The parameter is calculated by performing constant calculation processing on the constant value. This constant calculation process will be described later. In addition, a template corresponding to a general-purpose hardware configuration used when generating the HDL description is prepared in advance (S302).
For example, it is a template such as a constant coefficient multiplier described later. Then, the generated HDL description is stored in a file (S303).

Next, the user inputs the generated HDL description to the logic synthesizer and performs logic synthesis (S305).
The operator may find that the scale of the logic synthesized circuit is too large,
Or if there is a problem such as the circuit delay value is too large,
The HDL description is improved (S304). And again HD
Logic synthesis of the L description is performed (S305), and when the problem is eliminated, the logic circuit is stored in a file (S30).
6), end the process.

FIG. 8 is a CSD (Canonical Signed) which is an example of a circuit having a structure that changes irregularly depending on parameters.
FIG. 3 is a diagram illustrating a configuration of a constant coefficient multiplier. CSD
A constant coefficient multiplier is a circuit that realizes constant coefficient multiplication using a shifter, an adder, a subtractor, and a selector. FIG.
As shown in (1), the CSD constant coefficient multiplier is a unit circuit 80 ₀ to 80 _n including a shifter, an adder, a subtractor, and a selector.
Are connected in series. n is the bit width of the constant coefficient value.

When the CSD [0] to CSD [n] signals input to the unit circuits 80 ₀ to 80 _n are "1", the output signals of the adder are output by the selectors in the unit circuits 80 ₀ to 80 _n . Is selected. CSD [0] to CSD
When the [n] signal is "-1", the selector selects the output signal of the subtractor. In addition, CSD [0] to CS
When the D [n] signal is "0", the selector selects the output signal of the selector of the preceding unit circuit. CSD
The value of [0] to CSD [n] becomes a constant value according to the coefficient value as described later. Therefore, when "0" is set, the entire unit circuit is again "1" or "-".
For those for which 1 "is set, the unselected adder or subtractor and selector in the unit circuit become unnecessary circuits and are deleted. CSD array (CSD [0], C
SD [1], ..., CSD [n]) is C from the constant coefficient value.
The value converted to the SD expression is set. For example, when the constant coefficient value is 23 (decimal number), the values of the CSD array are -1, 0, 0, -1, 0, 1 in order from the lower element. ^{That, 2 0 × (-1) +2} 3 × (-1) +2 5 × 1 =
−1−8 + 32 = 23, which indicates that the constant coefficient value and the value in the CSD expression are equivalent. Further, when 23 (decimal number) is converted into a binary number, it becomes 10111H, and therefore it is necessary to add three times when multiplying the constant coefficient. However, by converting to the CSD representation, it is possible to reduce the number of operations because the operation can be performed by adding and subtracting twice when performing multiplication. In this way, by converting the constant coefficient value into the CSD array, the circuit scale can be reduced and the circuit delay can be shortened.

FIG. 9 is a diagram showing an example of an HDL description generated by a conventional HDL description generation program. The HDL description shown in FIG. 9 represents the CSD constant coefficient multiplier shown in FIG. 8. The parameter input bit width is 7, the constant coefficient bit width is 5, the output bit width is 9, and the constant coefficient value is 23. In this case, the dedicated circuit is shown.

The module statement in the first line is a circuit module Co up to the end module statement in the last line.
efMult (in, out). In the HDL description 901, the value of each parameter is set by the parameter statement and the input bit width (I
nBits) and the bit width of the constant coefficient (CoefBi)
5 is set to ts), and 9 is set to the output bit width (OutBits).

The HDL description 902 defines each variable. The input statement defines that the input data in is 7-bit data [6] to [0]. Output data out by output statement
Is defined as 9-bit data [8] to [0]. Also, the internal register outVal is [1
It is defined as a 12-bit register of 1] to [0]. In addition, the integer statement allows CSD
It is defined that the arrays CSD [5] to [0] and the variable i are integers. The last always statement indicates that the processing up to the end statement one level above the endmodule statement is performed each time the input data in changes.

The HDL description 903 defines the value of the CSD array. That is, respective values are set in CSD [0] to [5].

HDL description 904 defines a CSD constant coefficient multiplier. First, 0 is set to the output value outVal. Then, i is set to 5, and the following processes (1) and (2) are performed until the value becomes 0 while decrementing i.

(1) The input data in is shifted i times and assigned to shiftVal. (2) When CSD [i] is 1, outVal is set to o.
The value of utVal + shiftVal is substituted. CSD
When [i] is -1, outVal-outVal-
Substitute the value of shiftVal. When CSD [i] is 0, the value of outVal is not changed.

Finally, outVal is added to the output data out.
9 bits of [11] to [3] are substituted. This process is o
Unnecessary lower 3 bits of utVal [2] to [0] are truncated.

In the HDL description shown in FIG. 9, descriptions 901 and 903 surrounded by dotted lines are descriptions inserted by the HDL description generation program. Therefore, other descriptions are provided as templates for the CSD constant coefficient multiplier.

[0021]

As described above, when generating a circuit having a structure that changes irregularly depending on parameters, it is necessary to generate an HDL description using a generation program. Therefore, when the generated HDL description is manually improved, the result of the improvement cannot be used in the next design. The generated program may be changed to reflect the manual improvement. However, since the user of the improved HDL description and the creator of the generated program are often different, it is necessary to change the generated program each time. Is not realistic. Therefore, there is a problem that the already-designed HDL description having been improved is not reused in the next design.

Further, since the HDL description includes know-how regarding a description method and a circuit configuration, a provider of the HDL description may want to hide the description content. The logic synthesis tool has a function of encrypting and decrypting the HDL description, and a provider of the HDL description can encrypt and provide the HDL description. However, since this encryption function is a function unique to the logic synthesis tool, an equivalent encryption / decryption function cannot be added to the generation program.
Therefore, when the provider of the HDL description provides the HDL description and the generation program, the HDL description cannot be encrypted and provided. That is, there is a problem that the contents of the HDL description cannot be kept secret.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a parameterization method that can be reused at the next design and that can conceal the contents of description. It is to provide an HDL description method.

An object of the present invention is to provide a logic synthesizing apparatus capable of shortening the time of the logic synthesizing process.

An object of the invention described in claim 3 is, in addition to the object of claim 2, to provide a logic synthesizer capable of inputting a description format for speeding up a logic simulation of a parameterized HDL description. .

It is an object of the present invention to provide a medium recording a logic synthesis program capable of reusing the previous parameterized HDL description at the time of logic synthesis of the next design.

[0027]

A parameterized HDL description method according to claim 1 includes a step of setting a constant value and a step of describing a process of converting the constant value into a constant table.

By including the process of converting a constant value into a constant table in the parameterized HDL description, a program for generating the HDL description is not required.

According to another aspect of the logic synthesis apparatus of the present invention, an extracting unit for extracting a process of converting a constant value into a constant table from the parameterized HDL description and a process extracted by the extracting unit are executed. A calculating means for calculating the constant table and a logic synthesizing means for synthesizing logic based on the constant table calculated by the calculating means are included.

The calculating means calculates a constant table required at the time of logic synthesis of the parameterized HDL by executing the processing extracted from the parameterized HDL description by the extracting means.

The logic synthesizing device according to claim 3 is the logic synthesizing device according to claim 2, wherein the extracting means performs the calculation of the constant table from the HDL description sentence executed only once when the HDL description is verified. Also extract.

Since the process of calculating the constant table can be described in an HDL description sentence that is executed only once when the HDL description is verified, the calculation of the constant table is executed only once. Therefore, it is possible to shorten the logic simulation time.

A medium storing the logic synthesis program according to claim 4 includes a step of extracting a process for converting a constant value into a constant table from the parameterized HDL description;
The method includes the steps of executing the extracted processing to calculate a constant table, and synthesizing logic based on the calculated constant table.

By executing the process extracted from the parameterized HDL description, the constant table necessary for the logic synthesis of the parameterized HDL is calculated.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing an appearance of a logic synthesis device according to the present invention. The logic synthesis device includes a computer main body 101, a graphic display device 102, a magnetic tape device 103, a magnetic tape 104, a keyboard 10
5. Mouse 106, CD-ROM (Compact Disk-Read
Only Memory) device 107, CD-ROM 108, and communication modem 109. The logic synthesis program is supplied by a recording medium such as the magnetic tape 104 or the CD-ROM 108. The logic synthesis program is executed by the computer main body 101, and the operator performs logic synthesis by operating the keyboard 105 or the mouse 106 while looking at the graphic display device 102. The logic synthesis program may be supplied from another computer to the computer main body 101 via the communication line and the communication modem 109.

FIG. 2 is a block diagram showing the configuration of the logic synthesizer of the present invention. Computer main body 10 shown in FIG.
1 is a CPU (Central Processing Unit) 201, R
OM (Read Only Memory) 202, RAM (Random Acc
ess Memory) 203 and hard disk 204. The CPU 201 is the graphic display device 1
02, magnetic tape device 103, keyboard 105, mouse 106, CD-ROM device 107, communication modem 10
9. Process while inputting / outputting data to / from ROM 202, RAM 203 or hard disk 204.
The logic synthesis program recorded on the magnetic tape 104 or the CD-ROM 108 is temporarily stored on the hard disk 204 by the CPU 201 via the magnetic tape device 103 or the CD-ROM device 107. CPU201
The logic synthesis is performed by appropriately loading the logic synthesis program from the hard disk 204 into the RAM 203 and executing it.

The logic synthesizer in each embodiment of the present invention will be described below. The appearance of the logic synthesizer shown in FIG. 1 and the configuration block diagram of the logic synthesizer shown in FIG. 2 are common to each embodiment. is there.

[First Embodiment] FIG. 3 is a flowchart showing a design procedure using a parameterized HDL description in the first embodiment of the present invention. First, the operator is HDL
Parameterized HD incorporating constant calculation processing in description
An L description is created (S101). As described in the related art, the constant calculation process is to convert a parameter used when performing logic synthesis of a circuit having a structure that changes irregularly by a parameter (constant table) such as a CSD constant coefficient multiplier from a constant value. This is a process for calculating.
The operator manually improves the parameterized HDL description incorporating the constant calculation process (S102).

The operator is manually parameterized HDL.
When the description is improved, the improved parameterized HDL description is input to the logic synthesizer to perform logic synthesis (S1).
03). The logic synthesizer can be Verilog HDL or V
A description in HDL hardware description language (HDL) is input. These HDL descriptions have a grammar equivalent to a high-level software language (such as C language), and constant calculation processing can also be described in HDL. That is, if hardware that inputs a constant coefficient and outputs a constant table is described in HDL, and the HDL description of a template corresponding to a general-purpose hardware configuration is combined,
A parameterized HDL description that can be directly input to the logic synthesis device can be created. Also, the logic synthesizer is HD
There is a function for separately changing a parameter value specified by a parameter statement in the L description, and a constant coefficient value that is a parameter value can be input to the logic synthesis device.

Finally, the gate circuit logically synthesized by the logical synthesizing device is stored in the file, and the processing is terminated (S104).

FIG. 4 is a diagram showing an example of the parameterized HDL description according to the first embodiment of the present invention. Since HDL descriptions 402 and 404 have the same description contents as conventional HDL descriptions 902 and 904 shown in FIG. 9, detailed description will not be repeated. HDL description 401 is paramet
The value of each parameter is set by the er statement. The input bit width (InBits) is 7, the constant coefficient bit width (CoefBits) is 5, and the output bit width (OutBi).
ts) is set to 9, and the constant coefficient value (CoefVal) is set to 23.

The HDL description 403 includes C
A constant calculation process for calculating an SD array is described. The first comment, "constant_gen_begi
n ”is the last comment sentence“ constant_gen ”
_End "indicates a constant calculation process. The <omitted> portion in the HDL description 403 indicates hardware that receives a constant coefficient value as an input and outputs a constant table as described above. The HDL description is described, that is, a constant coefficient value CoefVal is input,
Values of CSD array CSD [0] to CSD [CoefBit
s] is described.
However, this HDL description is omitted because it is a huge description.

As described above, according to the parameterized HDL description method in the present embodiment, the constant calculation process for calculating the constant table from the constant coefficient value is included in the parameterized HDL description to generate the HDL description. Makes programs unnecessary. Further, by using the encryption function provided in the logic synthesis apparatus, when providing the parameterized HDL description to the user, the encrypted parameterized HDL description can be provided, and the description content can be hidden. Becomes

[Second Embodiment] FIG. 5 is a flowchart showing a processing procedure of a logic synthesis apparatus according to a second embodiment of the present invention. First, a parameterized HDL description incorporating the constant calculation processing described in the first embodiment is created and stored in a file (S201). Since the constant coefficient value is defined by the parameter statement, the constant coefficient value can be changed separately.

Next, the description of the constant calculation process and the description for logic synthesis are separated from the parameterized HDL description. At the time of this separation, the logic synthesis device, for example, from the parameterized HDL description shown in FIG. 4, “constant_gen_” described as a comment statement in the HDL description 403.
begin ”to“ constant_gen_end ”
Can be separated by extracting as a constant calculation process (S202).

The conventional logic synthesis apparatus of the type that does not perform separation performs the following logic synthesis processing on the description of the constant calculation processing. That is, when a logic circuit corresponding to the operation of the HDL description is combined and there is an input pin fixed to a constant value, the part of the combined logic circuit that has the fixed value is detected and set to the fixed value. Eliminate wasteful logic gates.

As can be seen from the HDL description 403 in the first embodiment shown in FIG. 4, a circuit corresponding to the description of the constant calculation processing is a circuit that receives a constant value and outputs a constant table value. Therefore, all the gates of this circuit are fixed values, and all the circuits are removed except for the constant table value which is the output. The time required for the process of synthesizing the logic circuits once and removing all the circuits while leaving the constant table value is a length that cannot be ignored in the entire logic synthesis process.

In the logic synthesizer in this embodiment,
The conventional logic synthesis processing as described above is not performed for the separated constant calculation processing unit, and a constant table value is obtained by performing a logic simulation of the HDL description (S204). Since it is not necessary to synthesize the logic synthesis circuit once, the constant value can be obtained at high speed and the overall logic synthesis time can be shortened.

The constant table calculated in step S204 and the logic synthesis description (S205) separated in step S202 are combined to newly create a parameterized HDL description including the constant table (S206). . Then, normal logic synthesis is performed on the newly created parameterized HDL description (S20).
7) The logic-combined gate circuit is stored in the file (S208).

As described above, the logic synthesizing apparatus according to the present embodiment separates the constant calculation processing and performs the logic synthesis of the parameterized HDL description including the constant calculation processing. Therefore, it becomes possible to reuse the parameterized HDL description improved at the previous design.

[Third Embodiment] FIG. 6 is a diagram showing an example of a parameterized HDL description which is an input to a logic synthesizer according to a third embodiment of the present invention. Compared to the parameterized HDL description shown in FIG. 4, the description contents of the HDL descriptions 403 and 601 of the constant calculation processing are different, and FIG.
In FIG. 6, the always statement before the constant calculation process 403 is different from the constant calculation process 601 only in FIG. Therefore, detailed description will not be repeated for overlapping descriptions.

The initial statement in the HDL description 601 is a description for setting an initial value of a circuit at the time of a simulation, and is a description that is ignored in a conventional logic synthesizer. Verification of the HDL description for synthesis is performed by logic simulation. Al in logic simulation
The blocks of the ways statement are executed as many times as necessary. As shown in FIG. 4, the always statement is a constant calculation processing 4
If it is before 03, processing for calculating the same constant table many times during simulation occurs, and the simulation time becomes longer.

However, as shown in FIG.
By writing the l statement at the beginning of the constant calculation process, it is executed only once at the beginning of the simulation.
Therefore, the simulation time can be shortened if the always statement is described not before but before the constant calculation processing 601, and the initial statement is described in the constant calculation processing 601.

The logic synthesizing apparatus according to the present embodiment has the constant written in the alwayss statement in the processing (S202) for separating the description of the constant calculation processing and the logic synthesizing description in the logic synthesizing apparatus shown in the second embodiment. In addition to extracting the calculation process, the constant calculation process written in the initial sentence is also extracted. According to the present logic synthesizer, an HDL description with a high simulation speed at the time of verification can be created by using an initial statement which is a description ignored by the conventional logic synthesizer.

[0055]

According to the parameterized HDL description method according to the first aspect, the description can be reused at the next design, and the description content can be hidden.

According to the logic synthesizing apparatus of the second aspect, it is possible to shorten the time of the logic synthesizing process.

According to the logic synthesizing device of the third aspect, in addition to the effect of the second aspect, the parameterized HDL
It became possible to input a description format that speeds up the logic simulation of the description.

According to the medium storing the logic synthesis program according to the fourth aspect, it is possible to reuse the previous parameterized HDL description at the time of the next logic synthesis of the design.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an appearance of a logic synthesis device according to the present invention.

FIG. 2 is a block diagram illustrating a configuration of a logic synthesis device according to the present invention.

FIG. 3 is a flowchart showing a design procedure using a parameterized HDL description according to the first embodiment of the present invention.

FIG. 4 is a diagram showing an example of a parameterized HDL description in the first embodiment of the present invention.

FIG. 5 is a flowchart showing a processing procedure of the logic synthesis device according to the second embodiment of the present invention.

FIG. 6 is a diagram showing an example of a parameterized HDL description according to Embodiment 3 of the present invention.

FIG. 7 is a flowchart showing a design procedure when a conventional HDL description generation program is used.

FIG. 8 is a diagram showing a configuration of a CSD constant coefficient multiplier which is an example of a circuit having a structure that changes irregularly according to parameters.

FIG. 9 is a diagram showing an example of an HDL description generated by a conventional HDL description generation program.

[Explanation of symbols]

101 computer main body, 102 graphic display device, 103 magnetic tape device, 104 magnetic tape, 105 keyboard, 106 mouse, 107
CD-ROM device, 108 CD-ROM, 109 communication modem, 201 CPU, 202 ROM, 203
RAM, 204 Hard disk drive.

Claims (4)

[Claims] 1. A parameterized HDL description method comprising: setting a constant value; and describing a process of converting the constant value into a constant table. 2. Extraction means for extracting a process of converting a constant value into a constant table from the parameterized HDL description, and calculation for executing the process extracted by the extraction means to calculate a constant table. And a logic synthesizing means for synthesizing logic based on the constant table calculated by the calculating means. 3. The extracting unit executes the process of calculating the constant table only once when the HDL description is verified.
The logic synthesis device according to claim 2, wherein the logic synthesis device extracts the DL description sentence. 4. A step of extracting a process of converting a constant value into a constant table from the parameterized HDL description; a step of executing the extracted process to calculate a constant table; And a logic synthesizing program recorded on the medium.