JP3113594B2 - Logic design optimization apparatus and method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital LSI.
In particular, the present invention relates to a functional design method for designing a circuit function using a function macro in a signal processing data path or the like, and an improvement in a logic design method for designing a gate level circuit.

[0002]

2. Description of the Related Art Conventionally, digital LSI using a computer
In a circuit DA (Design Automation) system, a function level circuit using a function macro is used in designing a function level circuit using an arithmetic circuit such as an addition circuit and a multiplication circuit, which is called a function macro, and in designing a gate level circuit. A logic circuit is designed by designing and then generating a logic circuit for each parameterized function macro to obtain a gate-level circuit.

FIG. 13 shows a configuration of a conventional logic design apparatus, and FIG. 14 shows a conventional logic design method. This conventional example illustrates a method of performing soft macro synthesis.

In the conventional logic design apparatus of FIG. 13, connection information of each function macro is extracted by function macro connection information extraction means 2 from function level circuit information 1 described by connection of parameterized function macros. The function macro connection information 3 is output. The function macro connection information 3 is input to the soft macro synthesizing means 4. On the other hand, a soft macro library 7 including a soft macro core 6 for each function macro is provided. Using the function macro connection information 3 and the soft macro core 6 of the soft macro library 7, the soft macro synthesizing means 4 generates a gate level circuit 5 for each function macro based on the parameters set in the function macro. I do.

In the conventional logic design method shown in FIG. 14, a function level circuit described by connection of parameterized function macros is input, and parameters are extracted from this function level circuit in units of function macros. Step 600 is a step of performing soft macro synthesis in units and outputting a gate level circuit in function macro units.

[0006]

However, in the above-described conventional logic design apparatus and logic design method, a soft macro synthesis is performed for each function macro describing an input function level circuit to obtain a gate level circuit. However, soft macro synthesis cannot be performed in units other than the function macro unit. As a result, for example, if macro synthesis is performed in units other than the function macro unit describing the function level circuit, even if the optimal gate level circuit can be generated in terms of speed or area, the function macro can be uniformly generated. Since macro synthesis is performed in units, there is a disadvantage that a gate level circuit having poor performance in terms of speed or area is generated.

[0007] The present invention focuses on the above-mentioned problem, and its object is to generate a gate level circuit from a function level circuit using a function macro, as compared with a case where macro synthesis is performed in units of function macros describing the function level circuit. Therefore, when it is possible to generate an optimal gate level circuit in terms of speed or area,
An object of the present invention is to generate a gate level circuit optimal in terms of speed or area by performing macro synthesis in units other than the function macro unit in place of the function macro.

[0008]

In order to achieve the above object, according to the present invention, a macro other than a function macro unit describing a function level circuit and a function macro unit describing a function level circuit is provided. A unit capable of generating an optimal gate level circuit in terms of speed or area as compared with the case of synthesis is registered in advance, and a function macro or a combination of a plurality of function macros to be replaced with this unit is input. Extracted from the function level circuit, and macro synthesized.

That is, the logic design optimizing device according to the first aspect of the present invention inputs function level circuit information described by connection of parameterized function macros, and executes logic of a digital LSI based on the function level circuit information. A logic design optimization device for optimizing a design, wherein the function macro is a special macro or another function macro different from the function macro describing the input function level circuit information, the function macro describing the function level circuit information. A macro that can generate a gate level circuit superior in speed or area compared to the macro,
A list of function macros or combination of function macros to be replaced with this special macro or another function macro is provided in advance, and in the input function level circuit information,
Search and extract the connection relation of the function macro corresponding to the function macro or the combination of the function macros included in the list, and replace the connection relation of the extracted function macro with the special macro or another function macro based on the list. The information processing apparatus further comprises connection information extracting means for generating connection information between the replaced special macro or another function macro and a function macro connected thereto.

According to a second aspect of the present invention, in the logic design optimizing apparatus according to the first aspect, the list includes:
A replacement priority for replacing a function macro or a combination of function macros with a special macro or another function macro is included, and the connection information extracting means sets the connection relationship of the extracted function macros to a special macro or a special macro in the order of the replacement priority. It is characterized in that it is replaced with another function macro.

Further, according to a third aspect of the present invention, in the logic design optimizing apparatus according to the first or second aspect, the list includes a composite macro in which at least two function macros connected to each other are composited. , And a combination of the at least two function macros to be replaced with the composite macro.

According to a fourth aspect of the present invention, in the logic design optimizing apparatus according to the first or second aspect,
The list includes special macros or other function macros, and function macros that receive a plurality of signals and are distinguished for each combination of the bit widths of the plurality of input signals, and are replaced with the special macros or other function macros. And a function macro to be executed.

According to a fifth aspect of the present invention, in the logic design optimizing apparatus according to the first or second aspect, the list includes a special macro or another function macro and a specific constant as an input signal. And a function macro replaced with the special macro or another function macro.

According to a sixth aspect of the present invention, in the logic design optimizing apparatus according to the first or second aspect, the list includes a special macro or another function macro and a plurality of signals, It is characterized by having a function macro distinguished for each combination of the plurality of input signals, the function macro being replaced with the special macro or another function macro.

Further, in the logic design optimization method according to the present invention, the function level circuit information described by the connection of the parameterized function macros is inputted, and the logic of the digital LSI based on the function level circuit information is inputted. A logic design optimization method for optimizing a design, wherein a gate level which is superior in speed or area as compared with a function macro describing the function level circuit information from the input function level circuit information is provided. A first step of searching for and extracting a connection relationship of a function macro or a combination of function macros that can be replaced with a special macro or another function macro capable of generating a circuit, and a function macro or a function macro extracted in the first step Is replaced with the special macro or another function macro, and the replaced special macro or other function macro is connected to the special macro or another function macro. And having a second step of generating connection information and function macros.

According to an eighth aspect of the present invention, in the logic design optimizing method according to the seventh aspect, in the second step, the connection relation of the extracted function macros or the combination of the function macros is replaced by a predetermined replacement. It is characterized in that it is replaced with a special macro or another function macro in the order of priority.

According to a ninth aspect of the present invention, in the logic design optimizing method according to the seventh or eighth aspect, in the first step, each of the input function level circuit information includes It is characterized in that a connection relation of a combination of function macros that can be replaced with a composite macro in which at least two connected function macros are composited is retrieved and extracted.

According to a tenth aspect of the present invention, in the logic design optimizing method according to the seventh or eighth aspect,
In the first step, a connection relation of a function macro that receives a plurality of signals and is distinguished for each combination of the bit widths of the plurality of input signals is searched for and extracted from the input function level circuit information. It is characterized by.

Further, the invention according to claim 11 is the logic design optimization method according to claim 7 or claim 8, wherein
In the first step, a connection relation of a function macro having a specific constant as an input signal is searched and extracted from the input function level circuit information.

According to a twelfth aspect of the present invention, in the logic design optimizing method according to the seventh or eighth aspect, in the first step, a plurality of function level circuit information are inputted from among the inputted function level circuit information. The present invention is characterized in that a connection relation of a function macro which receives a signal and is distinguished for each combination of the plurality of input signals is searched and extracted.

With the above arrangement, according to the first to twelfth aspects of the present invention, after inputting the function level circuit information described by the connection of the function macro, the function macro describing the function level circuit information, or a plurality of function macros, If the area or speed of the generated gate level circuit is not excellent with the combination of the function macros of the above, this is replaced with a special macro or another function macro, and macro synthesis is performed in units of this special macro or another function macro. Therefore, a gate level circuit excellent in area or speed is generated.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows an overall configuration of a logic design optimizing apparatus according to a first embodiment of the present invention. In the present embodiment, a case where a logic circuit is generated by soft macro synthesis will be described as an example.

As shown in FIG. 1, the logic design optimizing device includes a connection information extracting unit 21 and a soft macro synthesizing unit 4.
1 and a soft macro library 71.

The soft macro library 71 includes a combination of at least two function macros connected to each other,
A list 8 of replacement combinations corresponding to these and one replaceable composite macro, a replacement priority 9 thereof, a soft macro core 6 of a functional macro unit, and a soft macro core 10 of the composite macro unit Become. The composite macro has a function in which at least two function macros are composited, and it is possible to obtain a high-quality gate-level circuit in terms of area or speed as compared with a case where each function macro is used for soft macro synthesis. Things.

The connection information extracting means 21 inputs the function level circuit information 1 described by the connection of the parameterized function macros, and the connection of the function macros included in the combination list 8 in the circuit information 1. A search is performed to determine whether or not there is a relationship. If there is a connection of the corresponding function macro, the connection of the corresponding function macro is replaced with the composite macro according to the replacement priority 9 for the composite macro. The connection information 31 between the function macros before and after that is generated.

The soft macro synthesizing means 41 comprises:
From the connection information 31 between the function macro and the composite macro, the soft macro core 6 in the function macro unit and the soft macro core 10 in the composite macro unit in the soft macro library 71, each function macro unit and the composite macro unit The gate level circuit 51 is generated by performing soft macro synthesis.

Next, a specific example of the present embodiment is shown in FIG. FIG. 3 shows a specific example of generating a gate level circuit from function level circuit information 1 described using a multiplier function macro 201 and an adder function macro 202.

In the figure, the connection information extracting means 21
From the composite combination list (replacement list) 8 of the function macro, the case where the connection between the adder output and the adder input is replaced with a three-input adder, and the connection between the multiplier output and the adder input is replaced with the product-sum operation unit Find when to replace. The above two permutations cannot be performed simultaneously because the adder function macros overlap, and the connection between the multiplier output and the adder input having a higher priority than the permutation priority 9 is replaced with the product-sum operation unit. Choose when to do. Then, the connection between the multiplier and the adder is replaced with a product-sum calculator, and connection information 31 consisting of a connection between the product-sum calculator macro 311 as a composite macro and the adder function macro 202 is output.

The soft macro synthesizing means 41 derives the corresponding product-sum calculator soft macro core 10 from the connection information 31.
2 and the adder soft level core 511 and the adder gate level circuit 5
12 is generated.

Therefore, even if the designer does not specify the composite macro, the composite macro is automatically replaced with the composite macro, and a high-quality gate-level circuit netlist in area or speed can be obtained.

(Second Embodiment) FIG. 2 shows the overall configuration of a logic design optimization apparatus according to a second embodiment of the present invention. Note that, in the present embodiment and thereafter, as in the first embodiment, a case where a logic circuit is generated by soft macro synthesis will be described as an example.

As shown in FIG. 2, the logic design optimizing device includes a connection information extracting unit 22 and a soft macro synthesizing unit 4.
2 and a soft macro library 72.

The soft macro library 72 includes a list 11 of combinations of input bit widths of function macros that can be replaced with special macros or other function macros, a replacement priority 12 thereof, a soft macro core 6 for each function macro, and And a soft macro core 13 in a special macro unit.

The special macro has the same function as that of a function macro having a specific input signal bit width, and has a higher area or speed in terms of area and speed than a function macro unit. Can be obtained. If the function macro has a specific input signal bit width, it can be replaced with another function macro having the same function. In this case, it is better to combine the soft macro with another function macro in terms of area or speed. In some cases, a high-quality gate level circuit can be obtained.

The connection information extracting means 22 inputs the function level circuit information 1 described in the connection of the parameterized function macros, and in the circuit information 1, the function level circuit information 1 of the function macro included in the combination list 11 is entered. A search is performed to determine whether or not there is an input signal bit width combination. If there is a function macro having a corresponding input signal bit width, the function macro is extracted, and the function macro is replaced with the special macro or another function according to the replacement priority 12. Macro, and then the connection information 3 between this special macro or another function macro and the function macros before and after it.
Generate 2.

The soft macro synthesizing means 42 obtains the connection information 32 between the special macro or another function macro and the function macro, the soft macro core 6 for each function macro, and the soft macro core 13 for each special macro. The soft macro synthesis is performed for each functional macro unit and special macro unit, and the gate level circuit 52 is generated.

Next, a specific example of FIG. 10 will be described. When generating a gate level circuit from the function level circuit information 1 described using the multiplier function macro 201 and the adder function macro 202, the multiplier function macro 201
5 bit input signal line 203 and 1 bit input signal line 2
04. When one input signal line of the multiplier has one bit, the possible value of the one-bit input signal line is “0” or “1”, and the output of the multiplier is “0” or the other input signal line. The value of the signal line remains unchanged.

The connection information extracting means 22 outputs the combination list 11
Thus, a case where a multiplier having an arbitrary-bit input signal line and a 1-bit input signal line is replaced with a special multiplier a,
A case where a multiplier having a 1-bit input signal line and a 1-bit input signal line is replaced with a special multiplier b is searched. Since the two replacements are performed on the same multiplier function macro and cannot be performed simultaneously, a case is selected in which the replacement is performed with the special multiplier b having a higher priority than the replacement priority 12. Then, the multiplier function macro 201 is changed to the special multiplier b.
The connection information 32 including the connection between the special multiplier b macro 321 and the adder function macro 202 is output.

The soft macro synthesizing means 42, based on the connection information 32, outputs the corresponding special multiplier b soft macro core 1
A special multiplier b gate level circuit 521 and an adder gate level circuit 512 are generated by using the adder 32 and the adder soft macro core 61.

Accordingly, even if the designer does not designate a special macro or another function macro, the special macro or another function macro is automatically replaced with a high-quality gate-level circuit netlist in area or speed. Can be obtained.

(Third Embodiment) FIG. 3 shows an overall configuration of a logic design optimizing apparatus according to a third embodiment of the present invention, and FIG. 11 shows a specific example thereof.

As shown in FIG. 3, the logic design optimizing device includes a connection information extracting unit 23 and a soft macro synthesizing unit 4.
3 and a soft macro library 73.

The soft macro library 73 includes a list 14 of combinations of constant input signals of function macros that can be replaced with special macros or other function macros, and a replacement priority 15 thereof.
And a soft macro core 6 in a function macro unit and a soft macro core 16 in a special macro unit.

The special macro has the same function as a function macro having a specific constant input signal. Compared with a case where soft macro synthesis is performed on a function macro basis, a high-quality gate level circuit in area or speed is used. What you can get. If a function macro has a specific constant input signal, it can be replaced with another function macro having the same function.
In this case, it may be possible to obtain a high-quality gate level circuit in terms of area or speed by performing soft macro synthesis with the other function macro.

The connection information extracting means 23 inputs the function level circuit information 1 described by the connection of the parameterized function macros, and includes in the circuit information 1 a constant input signal combination list 14 of the function macro. Search for a constant input signal of a function macro included in the function macro, and if there is a function macro that is the corresponding constant input signal, this is extracted, and the function macro is converted to a special macro or another function macro according to the replacement priority 15. And then connect information 3 between this special macro or another function macro and the function macros before and after this special macro.
3 is generated.

The soft macro synthesizing means 43 stores the connection information 33 and the soft macro core 6 for each function macro.
And a soft macro core 16 in a special macro unit to perform soft macro synthesis in each function macro unit and special macro unit to generate a gate level circuit 53.

Next, a specific example of FIG. 11 will be described. When generating a gate level circuit from the function level circuit information 1 described using the multiplier function macro 201 and the adder function macro 202, the multiplier function macro 201 includes an input signal line 205 that takes a variable value, Signal value is constant value "1"
And has a fixed input signal line 206 and an output signal line 207. Here, if one input of the multiplier is always a constant “1”, the output of the multiplier remains the value of the other input signal line.

The connection information extraction means 23 replaces a multiplier having an input signal line having a variable value and an input signal line having an arbitrary constant signal value with a constant multiplier from the constant macro input signal combination list 14 of the function macro. And a case where a multiplier having an input signal line having a variable value and an input signal line having a constant value of “1” is replaced with a special multiplier a. A search is made for a case where a multiplier having an input signal line whose value takes a constant value “1” is deleted. Since the three replacements are performed on the same multiplier function macro, they cannot be executed at the same time, and a case where a multiplier having a priority higher than the replacement priority 15 is deleted is selected. Then, the multiplier function macro 201 is deleted, the input signal line 205 having a variable value is connected to the input of the adder function macro 202, and the connection information 33 is output.

The soft macro synthesizing means 43 generates an adder gate level circuit 512 from the connection information 33 by using the corresponding adder soft macro core 61.

Therefore, even if the designer does not designate a special macro or another function macro, the special macro or another function macro is automatically replaced with a high-quality gate-level circuit netlist in area or speed. Can be obtained.

(Fourth Embodiment) FIG. 4 shows the overall configuration of a logic design optimization apparatus according to a fourth embodiment of the present invention, and FIG. 12 shows a specific example thereof.

As shown in FIG. 4, the logic design optimizing device includes a connection information extracting unit 24 and a soft macro synthesizing unit 4.
4 and a soft macro library 74.

The soft macro library 74 includes a list 17 of combinations of input signals of function macros that can be replaced with special macros or other function macros, a replacement priority 18 thereof, and a soft macro core 6 for each function macro. ,
And a soft macro core 19 in a special macro unit.

The special macro has the same function as a function macro having a specific input signal, and obtains a high-level gate-level circuit in terms of area or speed as compared with a case where soft macros are synthesized in units of function macros. Is what you can do. In addition, when a function macro has a specific input signal, it can be replaced with another function macro having the same function. In that case, it is better to combine a soft macro with the other function macro in terms of area or speed. In some cases, a high-quality gate level circuit can be obtained.

The connection information extracting means 24 inputs the function level circuit information 1 described by the connection of the parameterized function macro, and the circuit information 1 includes the function macro input signal list 17 in the input signal combination list 17 of the function macro. The input signal of the included function macro is searched, and if there is a function macro which is the corresponding input signal, it is extracted, and the function macro is replaced with a special macro or another function macro according to the replacement priority 18. Then, the connection information 34 between the special macro or another function macro and the function macros before and after the special macro is generated.

The soft macro synthesizing means 44 stores the connection information 34 and the soft macro core 6 for each function macro.
And the soft macro core 19 in the special macro unit, the soft macro synthesis is performed in each function macro unit and the special macro unit, and the gate level circuit 54 is generated.

Next, a specific example of FIG. 12 will be described. When a gate level circuit is generated from the function level circuit information 1 described using the multiplier function macro 201 and the adder function macro 202, the adder function macro 202 has the same input signal. Here, an adder having the same input signal is equivalent to doubling the input signal.

The connection information extracting means 24 searches the input signal combination list 17 of the function macro for a case where the two inputs are replaced with a constant multiplier for the same adder and a case where the adder is replaced with a shift operation unit for performing a bit shift. I do. Since the two replacements are performed on the same adder function macro, they cannot be executed at the same time, and a case is selected in which replacement is performed with a shift operation unit having a higher priority than the replacement priority 18. Then, the adder function macro 202 is replaced with the shift operation function macro 341 and the connection information 34 including the connection between the multiplier function macro 201 and the shift operation function macro 341 is output.

The soft macro synthesizing means 44, based on the connection information 34,
Using the shift operation unit soft macro core 64, a multiplier gate level circuit 541 and a shift operation unit gate level circuit 542 are generated.

Therefore, even if the designer does not specify a special macro or another function macro, the special macro or another function macro is automatically replaced with a high-level gate-level circuit netlist in area or speed. Can be obtained.

(Fifth Embodiment) FIG. 5 shows a flow of a logic design optimizing method according to a fifth embodiment of the present invention.

As shown in FIG. 5, in the logic design optimizing method, function level circuit information described by connection of parameterized function macros is input.

Step 610 searches the input function level circuit information for a connection of a function macro which is a combination that can be replaced with one composite macro which is a composite of at least two mutually connected function macros. . Here, the composite macro has a function in which at least two function macros are composited, and it is possible to obtain a high-quality gate-level circuit in terms of area or speed compared to a case where each function macro is used for soft macro synthesis. You can do it.

In step 600, if there is no connection of the corresponding function macro in step 610, a soft macro is generated for each function macro, and a gate level circuit is generated for each function macro.

In step 611, if there is a connection of the corresponding function macro in step 610, all connections of the function macro are extracted. The steps 610 and 611 constitute the first step of the invention according to claim 7.

In step 612, when there are a plurality of connections of the function macros extracted in step 611, it is searched whether or not there is a mutually overlapping function macro.

In step 613, when there is a function macro that overlaps in step 612, the connection of the function macro to be replaced and the composite macro to be replaced are not overlapped according to the replacement priority to the composite macro. Select.

Step 614 replaces the connection of the function macro to be replaced with the corresponding composite macro, and creates a connection between the replaced composite macro and the function macros before and after the replaced composite macro.
The steps 612, 613, and 614 constitute the second step of the present invention.

In step 615, a soft macro is generated for each functional macro unit and each composite macro unit, and a gate level circuit for each functional macro unit and a gate level circuit for each composite macro unit are generated.

Therefore, even if the designer does not specify the composite macro, the composite macro is automatically replaced with the composite macro, and a high-quality gate-level circuit netlist in area or speed can be obtained.

(Sixth Embodiment) FIG. 6 shows a flow of a logic design optimizing method according to a sixth embodiment of the present invention.

As shown in FIG. 6, in the logic design optimizing method, function level circuit information described by connection of parameterized function macros is input.

Step 620 searches the input function level circuit information for a function macro having a specific input signal line bit width which can be replaced with a special macro or another function macro. Here, a special macro has the same function as a function macro having a specific input signal line bit width, and has a higher area or speed in terms of area or speed compared to a case where a soft macro is synthesized in function macro units. Can be obtained. If the function macro has a specific input signal line bit width, it can be replaced with another function macro having the same function. In this case, it is better to perform soft macro synthesis with the other function macro in terms of area. Alternatively, a high-speed gate-level circuit may be obtained in some cases.

In step 600, when there is no function macro having the corresponding input signal line bit width in step 620, a soft macro is generated for each function macro, and a gate level circuit is generated for each function macro.

In step 621, if there is a function macro having the corresponding input signal line bit width in step 620, all the function macros are extracted.

In step 622, a search is made as to whether the function macro having the specific input signal line bit width extracted in step 621 can be replaced with a plurality of special macros or other function macros.

In step 623, when there is a function macro that can be replaced with a plurality of special macros or other function macros in step 622, the extracted specific macro is determined according to the priority of replacement with the special macro or other function macro. A special macro or another function macro to be replaced is selected so that function macros having an input signal line bit width do not overlap.

In step 624, the function macro having the extracted specific input signal line bit width is replaced with the selected special macro or another function macro, and the replaced special macro or other function macro is replaced with the preceding or following function macro. Create a connection with the function macro of.

In step 625, a soft macro is generated for each functional macro unit and a special macro or another functional macro unit to generate a gate level circuit for each functional macro unit and a special macro or another functional macro unit. .

Therefore, even if the designer does not designate a special macro or another function macro, the special macro or another function macro is automatically replaced with a high-quality gate-level circuit netlist in area or speed. Can be obtained.

(Seventh Embodiment) FIG. 7 shows a flow of a logic design optimizing method according to a seventh embodiment of the present invention.

As shown in FIG. 7, in the logic design optimizing method, function level circuit information described by connection of parameterized function macros is input.

Step 630 searches the function level circuit information for a function macro having a specific constant input signal line that can be replaced with a special macro or another function macro. The special macro has the same function as a function macro having a specific constant input signal line, and obtains a high-quality gate level circuit in terms of area or speed as compared with a case where soft macros are synthesized in function macro units. Can be done. If the function macro has a specific constant input signal line, it can be replaced with another function macro having the same function. In some cases, a high-speed gate-level circuit can be obtained.

In step 600, when there is no function macro having the corresponding constant input signal line in step 630, a soft macro is generated for each function macro, and a gate level circuit is generated for each function macro.

In step 631, if there is a function macro having the corresponding constant input signal line in step 630, all the function macros are extracted.

In step 632, a search is made to determine whether there are a plurality of special macros or other function macros that can be replaced with the function macro having the specific constant input signal line extracted in step 631.

In step 633, when there is a function macro which can be replaced by a plurality of special macros or other function macros in step 632, the function macro to be replaced is replaced according to the priority of replacement to the special macro or other function macro. And the special macro to be replaced or another function macro are selected so as not to overlap.

In step 634, the function macro to be replaced is replaced with the selected special macro or another function macro, and a connection between the replaced special macro or other function macro and the function macros before and after the replaced special macro or other function macro is created. .

In step 635, a soft macro is generated in units of function macros and special macros or other function macros, and a gate level circuit is generated in function macros and special macros or other function macros.

Therefore, even if the designer does not designate a special macro or another function macro, the special macro or another function macro is automatically replaced with a high-quality gate-level circuit netlist in area or speed. Can be obtained.

(Eighth Embodiment) FIG. 8 shows a flow of a logic design optimizing method according to an eighth embodiment of the present invention.

As shown in FIG. 8, in the logic design optimizing method, function level circuit information described by connection of parameterized function macros is input.

Step 640 searches the function level circuit information for a function macro having a specific input signal line combination that can be replaced with a special macro or another function macro. The special macro has the same function as a function macro having a specific combination of input signal lines, and obtains a high-quality gate level circuit in terms of area or speed as compared with a case where soft macros are synthesized in units of function macros. Is what you can do. In addition, when a function macro has a specific combination of input signal lines, it may be possible to replace the function macro with another function macro having the same function. In some cases, a high-quality gate level circuit can be obtained in terms of area or speed.

In step 600, when there is no function macro having the corresponding combination of input signal lines in step 640, a soft macro is generated for each function macro to generate a gate level circuit for each function macro.

In step 641, if there is a function macro having the corresponding combination of input signal lines in step 640, all the function macros are extracted.

In step 642, a search is made as to whether there are a plurality of special macros or other function macros that can be replaced with the function macro having the specific input signal line combination extracted in step 641.

In step 643, when there is a function macro which can be replaced with a plurality of special macros or other function macros in step 642, the function macro to be replaced is replaced according to the priority of replacement with the special macro or other function macro. And the special macro to be replaced or another function macro are selected so as not to overlap.

Step 644 replaces the function macro to be replaced with the selected special macro or another function macro, and creates a connection between the replaced special macro or other function macro and the function macros before and after the replaced special macro or other function macro. .

In step 645, a soft macro is generated in units of function macros and special macros or other function macros, and a gate level circuit is generated for each function macro unit and special macro or other function macros.

Therefore, even if the designer does not designate a special macro or another function macro, the special macro or another function macro is automatically replaced and a high-quality gate-level circuit netlist in area or speed is obtained. Can be obtained.

[0102]

As described above, according to the logic design optimizing apparatus and the logic design optimizing method of the present invention, the connection relationship between the function macros can be obtained without any manual designation at the function level design stage. By simply describing the function level circuit, a gate level circuit optimal in terms of speed or area can be obtained, and work efficiency and circuit quality can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a logic design optimization device according to a first embodiment of this invention.

FIG. 2 is a diagram illustrating a configuration of a logic design optimization device according to a second embodiment of this invention.

FIG. 3 is a diagram showing a configuration of a logic design optimization device according to a third embodiment of the present invention.

FIG. 4 is a diagram illustrating a configuration of a logic design optimization device according to a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a flow of a logic design optimization method according to a fifth embodiment of the present invention.

FIG. 6 is a diagram showing a flow of a logic design optimization method according to a sixth embodiment of the present invention.

FIG. 7 is a diagram showing a flow of a logic design optimization method according to a seventh embodiment of the present invention.

FIG. 8 is a diagram showing a flow of a logic design optimization method according to an eighth embodiment of the present invention.

FIG. 9 is a diagram showing a specific example of the operation of the logic design optimization device according to the first embodiment of the present invention.

FIG. 10 is a diagram illustrating a specific example of the operation of the logic design optimization device according to the second embodiment of this invention.

FIG. 11 is a diagram illustrating a specific example of the operation of the logic design optimization device according to the third embodiment of this invention.

FIG. 12 is a diagram showing a specific example of the operation of the logic design optimization device according to the fourth embodiment of the present invention.

FIG. 13 is a diagram showing a configuration of a conventional logic design apparatus.

FIG. 14 is a diagram showing a flow of a conventional logic design method.

[Explanation of symbols]

1 Function Level Circuit Information 2 Function Macro Connection Information Extraction Means 6 Soft Macro Core in Function Macro Unit 7 Soft Macro Library 8 Function Macro Compound Combination List 9 Function Macro Compound Combination Priority 10 Soft Macro Core in Compound Macro Unit 11 Function Macro input signal bit width combination list 13, 16, 19 Soft macro core in special macro unit 14 Function macro constant input signal combination list 17 Function macro input signal combination list 21-24 Connection information extraction means 41-44 Soft macro synthesis Means 61 Adder soft macro core 62 Multiplier soft macro core 63 Constant multiplier soft macro core 64 Shift calculator soft macro core 101 Three-input adder soft macro core 102 Product-sum calculator soft macro core 131 Special multiplier a soft macro Core 132 Special multiplier b soft macro core 161 Special multiplier a soft macro core

Continuation of front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 17/50

Claims (12)

(57) [Claims] 1. A logic design optimizing device for inputting function level circuit information described by connection of parameterized function macros and optimizing a logic design of a digital LSI based on the function level circuit information, A special macro or another function macro different from the function macro describing the input function level circuit information,
A macro capable of generating a gate level circuit superior in speed or area as compared with a function macro describing the function level circuit information, and a function macro or a combination of function macros replaced with this special macro or another function macro A list in advance, and in the input function level circuit information, a search is made for a connection relationship of a function macro corresponding to a function macro or a combination of function macros included in the list, and extracted, The connection relationship between the extracted function macros is replaced with a special macro or another function macro based on the list, and connection information between the replaced special macro or another function macro and the function macro connected thereto is generated. A logic design optimizing device, comprising: 2. The list includes a replacement priority for replacing a function macro or a combination of function macros with a special macro or another function macro, and the connection information extracting means determines a connection relationship of the extracted function macros. 2. The logic design optimizing apparatus according to claim 1, wherein the macro is replaced with a special macro or another function macro in the order of the replacement priority. 3. The list includes a composite macro in which at least two mutually connected function macros are composited, and a combination of the at least two function macros replaced with the composite macro. The logic design optimization device according to claim 1 or 2. 4. The list includes: a special macro or another function macro; and a function macro which receives a plurality of signals and is distinguished for each combination of bit widths of the plurality of input signals. 3. The logic design optimizing device according to claim 1, further comprising a function macro replaced with the function macro. 5. The list includes a special macro or another function macro, and a function macro which receives a specific constant as an input signal and is replaced with the special macro or another function macro. The logic design optimization device according to claim 1 or 2. 6. The list includes a special macro or another function macro, a function macro which receives a plurality of signals and is distinguished for each combination of the plurality of input signals, and wherein the special macro or another function macro is used. 3. The logic design optimization device according to claim 1, further comprising a function macro replaced with a macro. 7. A logic design optimization method for inputting function level circuit information described by connection of parameterized function macros and optimizing a logic design of a digital LSI based on the function level circuit information, From the input function level circuit information, it can be replaced with a special macro or another function macro capable of generating a gate level circuit superior in speed or area as compared with a function macro describing this function level circuit information. First to search for and extract the connection relationship of a function macro or a combination of function macros
And the connection relation of the function macro or the combination of the function macros extracted in the first step is replaced with the special macro or another function macro, and the replaced special macro or other function macro is replaced with Generating a connection information with a function macro connected to the logic macro. 8. In the second step, the connection relation of the extracted function macros or the combination of the function macros is replaced with a special macro or another function macro in the order of a predetermined replacement priority. 7. The logic design optimization method according to 7. 9. In a first step, a connection relationship of a combination of function macros that can be replaced with a composite macro obtained by combining at least two mutually connected function macros is searched from the input function level circuit information. The logic design optimization method according to claim 7 or 8, wherein the extraction is performed. 10. In a first step, a connection relation of a function macro that receives a plurality of signals and is distinguished for each combination of bit widths of the plurality of input signals is searched from the input function level circuit information. And
9. The logic design optimizing method according to claim 7, wherein extraction is performed. 11. The method according to claim 7, wherein in the first step, a connection relation of a function macro having a specific constant as an input signal is searched and extracted from the input function level circuit information. Claim 8
The described logic design optimization method. 12. In a first step, a connection relation of a function macro that receives a plurality of signals and is distinguished for each combination of the plurality of input signals is searched from the input function level circuit information and extracted. 9. The logic design optimization method according to claim 7, wherein the logic design optimization is performed.