JP3090135B2 - Logic circuit synthesis method and logic synthesis system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for automatically synthesizing a logic circuit, and more particularly to a logic circuit synthesis method and system for optimizing a given logic circuit so as to satisfy given constraints such as a given area and delay. About. More specifically,
The present invention relates to a logic circuit synthesis technique for optimizing a logic circuit so as to satisfy given constraints such as area and delay when a design change is assumed.

[0002]

2. Description of the Related Art Conventional automatic synthesis techniques for logic circuits include, for example, L.A. Boolean Dozer by Stok et al .: Logic Synthesis for ASICs (BoolD
ozer: LogicSynthesis for
ASICs) 1996.7, IBM J.C. RES.
Development, pp. 407-430) and the like are referred to.

In this technique, in the process of optimizing a circuit, management is performed as to which part of the circuit before optimization corresponds to which part of the circuit. Although it is possible to roughly specify a partial circuit as to whether or not has been changed, it is not possible to save the circuit before the change except for the part changed with the change of the circuit.

[0004] In addition, Y. Watanabe et al., Incremental Synthesis For Engineering Changes (IncrementalSy)
nthesis for Engineering Ch
angels, Proceedins of IEEE
E, International Conference
e on Computer Design, 199
1 pp40-43), when a design change occurs,
A method is described in which the circuit after the design change is maintained substantially equivalent to the circuit before the design change only by changing the wiring connection.
However, any change merely changes the wiring connection, and there is no guarantee that the state before the design is maintained. Also,
In this method, since the calculation regarding the addition of wiring is performed using the logic information of the entire circuit, the processing is complicated and it is difficult to apply the method to a large-scale circuit.

[0005]

The conventional logic circuit automatic synthesis technique described above has the following problems.

A first problem is that when a part of a circuit is changed in design, it is impossible to save the circuit before the change except for the part changed in accordance with the change in the circuit.

The second problem is that there is no guarantee that the state before the design is preserved, and since wiring is added based on the logic information of the entire circuit, the processing is complicated, and the processing for a large-scale circuit is difficult. It is difficult to apply.

A first object of the present invention is to generate a new circuit around the redesigned circuit part when a part of the circuit is redesigned, and to design the circuit except for the changed part in the circuit. It is an object of the present invention to provide a method and a system for synthesizing a logic circuit which can keep the circuit state before the change.

A second object of the present invention is to perform a design change based on a synthesis result that satisfies the circuit requirements, such as area delay, as much as possible, even on the premise that the design change is performed. Is to provide a logic circuit synthesizing method and a system which output as much as a logic circuit synthesizing method which is not a premise.

It is a third object of the present invention to provide a method and system for synthesizing a logic circuit which does not depend on the circuit scale and which is based on a design change.

[0011]

According to the present invention, which achieves the above object, there is provided a logic circuit synthesis method for optimizing a given logic circuit so as to satisfy given constraints such as area and delay. The logic circuit is divided into a plurality of partial circuits based on the circuit information of the logic circuit, and logic optimization is performed so as to satisfy a constraint input for each of the partial circuits. Outputs the circuit as a result of synthesis,
At the time of changing the logic circuit, the result circuit is divided in the same manner as the previous time, the logic optimization is performed only on the changed partial circuit, and the remaining result circuit is reused for other partial circuits as it is, and outputting as said logic optimized modified partial circuit and synthesizing results circuit, the logic
When the circuit is divided into partial circuits,
Circuit elements with fanouts of 2 or more.
Fan-out is classified into 1 circuit element and fan-out is 2
Using the above circuit elements as a unit of division, fan-out
Fanout 1 connected to input terminals of two or more circuit elements
Are merged together, and the classification result and the
The logic circuit is divided into partial circuits based on the result of the combination .

According to the logic circuit synthesis method of the present invention , in dividing the logic circuit into partial circuits,
The circuit elements that make up the logic circuit have a fanout of 2 or more
Are classified into circuit elements with a fanout of 1 and circuit elements with a fanout of 1.
The circuit element having a fanout of 2 or more is defined as a unit of division.
Connected to the input terminal of a circuit element with a fanout of 2 or more.
The circuit elements of fan-out 1
By tracing until the above circuit elements are encountered,
Circuit element of fanout 2 or more and circuit element of fanout 1
Children are merged together, and based on the classification result and the merged result,
Then, the logic circuit is divided into partial circuits .

According to the logic circuit synthesizing method of the present invention, in the logic optimization processing of the partial circuit,
Logic optimization for all adjacent combinations of subcircuits
And, as a result of the logic optimization,
Select the combination of subcircuits that is closest to the
And select the combination of the selected partial circuits into a new part.
It is a circuit .

According to a fourth aspect of the present invention, there is provided a logic circuit.
To meet given area, delay, and other constraints.
In the logic circuit synthesis system to be optimized,
Logical dividing means for dividing a logical circuit into a plurality of partial circuits;
Constraints such as area and delay given to the subcircuit
A constraint input means for inputting, and the logic
Logic for each of the sub-circuits of the path to satisfy the constraints
Split optimization means for performing optimization and changes in the circuit
, New discussions are made only for the changed partial circuit.
New optimization means to perform logical optimization and the part where the change occurred
The results after the first logic optimization for the
Reusing means to be retained, and
Merge subcircuits and newly optimized subcircuits
Merging means, and the synthesis result by the division optimizing means or
Outputs the merged result by the merger.
And logic means, wherein the logic dividing means
Regarding the constituent circuit elements, the circuit elements having a fan-out of 1
Circuit elements classified into two or more circuit elements
Dividing child elements and circuit elements with more than 2 fan-outs
The input terminal of a circuit element with a fanout of 2 or more
All the fine-out 1 circuit elements connected to the
And cone generating means for merging and dividing .

A logic circuit synthesis system according to the present invention.
According to the report, for logic circuits that are
First circuit input means for inputting the logic circuit first,
Change section circuit input means for inputting a changed partial circuit
And the previous input of the logic circuit as the result of the previous synthesis
Circuit input means .

According to the logic circuit synthesis system of the present invention, the cone generating means has a fan-out of 2 or more.
Using the above circuit element as a unit of division, fan out 2
The fan out 1 connected to the input terminal of the above circuit element
Circuit elements are encountered in a chain with fan-out 2 or more.
By tracing until the fan out 2 or more
Circuit elements and fan-out 1 circuit elements are merged together
And is divided into partial circuits .

According to the logic circuit synthesis system of the present invention, the divided logic optimizing means includes a divided part
Perform logic optimization on all adjacent combinations of the circuit.
Logic optimization means for merging, and
The subcircuit closest to the constraints of the input circuit during optimization
Merging determination means for selecting a combination of
Conemer that uses a combination of partial circuits as a new partial circuit
It is characterized in that it is constituted by a means .

According to the logic circuit synthesis system of the present invention, the logic dividing means constitutes the logic circuit.
Circuit elements with a fan-out of 1
Circuit element classification to classify circuit elements with fanout of 2 or more
Means and unit of division of circuit elements with fanout of 2 or more
Connected to the input terminal of a circuit element with a fanout of 2 or more.
Fine-out 1 circuit elements that follow are merged together
And a cone generating means for dividing
The logical optimization means is a combination of the neighboring combinations of the divided partial circuits.
Logic Optimizer for Merging that Performs Logic Optimization on Everything
Stage and the result of the logic optimization,
Select the combination of subcircuits closest to the constraints of the circuit
The combination of the merging determination means and the selected partial circuit
It is characterized by being constituted by cone merge means as a new partial circuit .

According to the present invention of claim 9, the given theory
Logic circuit to satisfy given area, delay and other constraints.
Computer Program for Logic Circuit Synthesis Optimized for
A storage medium for storing a program,
The program is based on the input circuit information of the logic circuit.
Dividing the logic circuit into a plurality of partial circuits;
Perform logic optimization to satisfy the constraints entered for each
Outputs the circuit as a result of synthesizing the sub-circuits that have been
When the logic circuit is changed, the result circuit is
And only discuss the changed partial circuits
Optimization, and other partial circuits
The result circuit is reused as it is, and the logic-optimized
The result is synthesized with the further partial circuit and output as a result circuit.
In dividing the logic circuit into partial circuits, the logic circuit
Circuit elements having a fan-out of 2 or more.
And fan-outs are classified into one circuit element.
The circuit element having two or more
A fan connected to the input terminal of the circuit element
A circuit with fanout 2 or more in a chain of circuit elements of out1
By tracing until the device is encountered, the fan-out
Combines two or more circuit elements and fan-out 1 circuit elements
And based on the classification result and the merged result,
Logic characterized by dividing the logic circuit into partial circuits
Perform circuit synthesis.

[0020]

[0021]

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In the logic circuit synthesizing method according to the present invention, an input circuit is divided into a plurality of partial circuits, a logic optimization is performed for each of the partial circuits, and a result circuit obtained by synthesizing the logic-optimized partial circuits is obtained. At that time, division information is held, and when the circuit is changed, the above result circuit is divided in the same manner as the previous time, and only the changed partial circuit is subjected to logic optimization, and the other partial circuits are not changed. It is reused, combined with the logic-optimized changed partial circuit, and output as a result circuit.

More specifically, the method of synthesizing a logic circuit according to the present invention comprises the steps of: (a) dividing a first-time input logic circuit into a plurality of divided partial circuits for a circuit whose design change is expected; (b) While maintaining the divided state, logic optimization was individually performed for each of the divided partial circuits so as to satisfy the constraints such as the area and delay given to each of the divided partial circuits, and the logic optimization was performed. Outputting the synthesis result of the divided partial circuit; (c) Next, when a change occurs in the circuit,
The circuit of the previous synthesis result is input, and the input circuit is
A step of dividing in the same way as the previous division, (d) newly performing logic optimization only on the divided partial circuit corresponding to the changed part, and using the remaining partial circuits as they are, It comprises a step of combining the divided sub-circuit before the change and the divided sub-circuit newly subjected to the logic optimization and outputting a synthesis result.

The processing in each of the above-described steps is controlled by a program executed by a data processing device having an input means, an output means, a storage means such as a file device, a main storage device, and an arithmetic means.

As shown in FIG. 1, a logic circuit synthesis system of the present invention for realizing the above-described logic circuit synthesis method includes a first circuit input unit 101 for inputting a first circuit for a circuit whose design is expected to be changed, A changed circuit input unit 103 for inputting a circuit after a change, a previous circuit input unit 102 for inputting a result of a previous synthesis after a design change, a logical division unit 104 for previously dividing an input circuit, and the division form is held. A constraint input unit 105 for inputting constraints such as an area and a delay given to each circuit, and a division optimization unit 106A for individually executing logic optimization so as to satisfy the input constraints, are changed to circuits. Is generated, a new optimization unit 106B that newly performs logical optimization only on the divided part,
Other parts are a reuse unit 107 that reuses the circuit before the change as it is, a combining unit 108 that combines the reused partial circuit and the newly optimized partial circuit, and a combined result that outputs a combined result. It comprises an output unit 109 and a control unit 110 for controlling the whole.

Regarding the processing procedure of the embodiment of the present invention,
Referring to FIG. 2, the first logic circuit for which a design change is expected is input from the initial circuit input unit 101 (steps 201 and 202). The input logical circuit is divided into a plurality of partial circuits by the logical dividing unit 104 (step 203).

While maintaining the divided form, the divided optimizing unit 106A adjusts the individual partial circuits so as to satisfy the constraints such as the area and delay given to each circuit input by the constraint input unit 105. To perform logic optimization (step 204). The optimized logic circuit is output as a synthesis result by the synthesis result output unit 109 (step 205).

Next, when a change occurs in the circuit, the result of the first synthesis is input by the previous circuit input unit 102 (steps 201 and 206). The division optimizing unit 104 divides the input circuit into partial circuits in the same manner as the first time based on the first time division information (step 207). Then, the circuit of the changed part is input by the changed circuit input unit 103 (step 208), and only the changed part is newly subjected to logical optimization by the new optimizing unit 106B (step 209).

As for the partial circuits other than the changed part, the reuse unit 107 uses the partial circuit before the change as it is, and combines the partial circuit to be reused by the merging unit 108 with the newly optimized circuit. (Step 210), and outputs the synthesis result by the synthesis result output unit 109 (Step 20).
5).

The control of the processing by each processing unit is performed by the control unit 110.

When performing the logic optimization on the divided circuit, the restrictions such as the area and delay targeted by the logic optimization are as follows.
Since the divided partial circuits are not equal and may give an excessive demand, the mitigation determining means may apply a constraint in accordance with the limit of optimization for each partial circuit. And the mitigation target assigning unit gives the new constraint to the partial circuit, and then executes the division optimizing unit 106A.

FIG. 3 is an explanatory diagram schematically showing an example of an initial synthesis method by the logic circuit synthesis system according to the first embodiment of the present invention.

First, AND, OR, NAND, NOR,
A logic circuit including logic elements such as XOR, XNOR, and flip-flops and wiring connecting the logic elements is input to the first logic circuit input unit 101. This logic circuit is to be changed. On the other hand, constraints such as area delay required for this circuit are input from the constraint input unit 105.

In the first synthesis, the input circuit is converted by the logical dividing unit 104 as shown in FIG.
Divided partial circuits "A", "B", "C", "D", "E"
Is divided into The first division method is stored as division information in the logical division unit 104. Therefore, the same division is performed when the changed circuit is input.

The divided first logic circuit (the logic circuit input from the first circuit input unit 101) is a partial circuit for each division unit.
“B”, “C”, “D”, and “E” are input to the constraint input unit 105.
The logic optimization is performed by the division optimization 106A for each of the partial circuits so as to approach the constraint input from the maximum as much as possible. Then, the optimized partial circuits "A-1", "B
By synthesizing "-1", "C-1", "D-1", and "E-1", a logic circuit including a logic element and a wiring is output from the synthesis result output unit 109. The first synthesizing process before the change ends here.

FIG. 4 is an explanatory diagram schematically showing an example of a method of synthesizing a modified circuit in the logic circuit synthesizing system according to the first embodiment of the present invention.

In the second and subsequent synthesizing processes in which a design change has occurred in the circuit, the logic circuit based on the previous optimization result is input from the previous circuit input unit 102 and the previous (in this case,
As in the first case, the logical division unit 104 divides the circuit into a plurality of partial circuits. Here, as shown in FIG.
The partial circuits "A-1", "B-1", "C-1", "D-
1 "and" E-1 ".

In the result of the division, the contents of the divided partial circuits are different from those of the first logic circuit. However, since the first optimization processing is performed for each divided circuit, the location and number of divisions are different from those of the first logic circuit. Are identical.

The changed partial circuit "B-
"2" is input from the change unit circuit input unit 103. In this state, each divided partial circuit can determine which divided partial circuit has changed and which is not. Also, the same constraint as the constraint on the first circuit is input from the constraint input unit 105.

The divided partial circuit "A-
For the "1", "C-1", "D-1", and "E-1", the reuse unit 107 retains the result after the optimization of the first circuit as it is, and the divided partial circuit "B- For “2”, the new optimization unit 106 newly performs optimization to satisfy the constraints such as the area and the delay, and the divided partial circuit “B−
3 ". A divided partial circuit “A-1” in which the result after the first optimization is held by the reuse unit 107,
"C-1", "D-1", "E-1" and the newly optimized divided sub-circuit "B-3" are merged by the merging unit 108 and the result is output by the synthesis result output unit 109. Output. These controls are performed by the control unit 110.

Next, a second embodiment of the present invention will be described. FIG. 4 is a block diagram showing the configuration of the logic circuit synthesis system according to the second embodiment of the present invention.

Referring to FIG. 5, according to the second embodiment of the present invention, the logical divider 104 for dividing the logic circuit of the first embodiment shown in FIG. And a circuit element classifying unit 201 for classifying circuit elements (circuit elements) or more and other circuit elements (circuit elements), and a circuit element with a fan-out of “1” to an input of a circuit element with a fan-out of “2” or more And a cone generating unit 202 that divides as much as possible.

As a division method of the logical division unit 104, "A
ND "," OR "," NOR "," NAND "," XO "
R "," XNOR "," flip-flop ", etc., the fan-out of which is" 2 "
The above circuit elements are classified by the circuit element classification unit 201, and the cone generation unit 202 is configured to connect the circuit element of the fan-out 2 to the input of the circuit element of the fan-out 2 or more and divide the circuit element.

The division processing of the logical division unit 104 will be described with reference to the flowchart of FIG.

The circuit element classifying unit 201 classifies the circuit elements constituting the input logic circuit into circuit elements (circuit elements) having a fan-out of “2” or more and other circuit elements (circuit elements) (step 601). ).

The cone generation unit 202 uses the circuit elements whose fan-out classified by the circuit element classification unit 201 is “2” or more as a unit of division, and performs the fan-in of the circuit elements whose fan-out is “2” or more. The circuit elements having the fan-out "1" are merged as much as possible (step 602). That is, the cone generation unit 202 traces and merges the circuit elements of the fan-out “1” connected to the input terminals of the circuit elements of the fan-out “2” or more until the circuit elements of the fan-out “2” or more are encountered. .

Then, the logic circuit is divided into a plurality of partial circuits based on the result of the classification and the result of the merging (step 603).

FIG. 7 is a diagram schematically showing an example of a circuit dividing method in the logical dividing section 104 by the logic circuit synthesizing system according to the second embodiment of the present invention.

The logic circuit shown in FIG. 7 has circuit elements (circuit elements) (1), (2), (3), (4), (5),
(6), (7) and (8).

In the division, except for the input / output portion of the circuit element which is a natural cut end, the circuit element having a fan-out “2” or more which causes an increase in the circuit area and delay is classified into the circuit element classification. The unit 201 includes a circuit element (1),
(4), (8) and other logic elements (2), (3),
(5), (6), and (7). Cone generator 2
In the example 02, the circuit element groups (2), (3), (5), and (6) of the fan-out “1”, in which the control of the circuit area and the delay is easy, using the logic element of the fan-out “2” as a unit of division. ),
(7) is integrated into the circuit element (8). When the first circuit is input, such a division form is adopted for the purpose of obtaining a single division result. As a result, the above-described logic circuit is subjected to the partial circuit “A” by the cone generation unit 202.
(1) ", partial circuit" B (4) ", partial circuit" C (2,
3, 5, 6, 7, 8) ".

Next, still another embodiment of the present invention will be described. FIG. 8 is a diagram illustrating a configuration example of a logical division unit of a logical circuit synthesis method according to the third embodiment of the present invention.

Referring to FIG. 8, in the third embodiment of the present invention, division optimizing section 106A optimizes a combination of adjacent divided partial circuits at the time of the first synthesis. A merging optimization unit 302, a merging determination unit 301 that determines whether to merge adjacent divided sub-circuits based on the optimization result, and a new combination of the divided sub-circuits determined by the merging determination unit 301 are newly added. And a cone merge unit 303 which is a simple divided partial circuit.

After executing the optimization after the merging, the merging judging section 301 selects a combination approaching due to circuit restrictions. That is, the merging determination unit 301 determines whether merging is advantageous or disadvantageous when merging a plurality of adjacent divided circuits so as to be advantageous for optimization.

In the first embodiment described above, the logical optimization processing by the division optimization unit 106A is performed by the logical division unit 104.
Are applied individually to the divided sub-circuits. Therefore, the logic optimization is applied to the whole, and as a result, the optimization performance may be inferior to the logic synthesis method that is not aware of the design change. Therefore, in the third embodiment of the present invention, in order to approach a logic synthesis method that is not aware of any design change, the merging determination unit 301 mainly focuses on a partial circuit that cannot satisfy the given constraint and its peripherals. Are merged and the logic optimization is executed, and if it seems to approach the overall constraint, the cone merge unit 303 merges the division circuits. This merging of the split circuits is performed during the synthesis of the first design.

The logic optimization process of the division optimization unit 106A will be described with reference to the flowchart of FIG.

When the result of division into the partial circuits from the logical division unit 104 is input (step 901), the merging optimization unit 302 performs logical optimization on all adjacent combinations of the divided partial circuits (step 901). 902).

After the execution of the optimization, the merge determination unit 301 determines the combination whose optimization result is closest to the input constraint (step 903). Then, cone merge part 3
03 sets the determined combination of partial circuits as a new partial circuit (step 904).

FIG. 10 is an explanatory diagram schematically showing an example of the processing of the division optimizing unit 106A of the logic circuit synthesis method according to the third embodiment of the present invention.

It is assumed that the circuit is divided into partial circuits "A", "B", "C", "D", and "E" as shown in FIG. In this case, all combinations (A, C), (C, D), (A, D), (D, E),
Merging optimization unit 302 for (A, B) and (B, E)
Actually perform the optimization.

Based on the result of the optimization, the merging judgment unit 30
1 determines the combination that comes closest to the constraints of the circuit. Here, a case is shown where the merging determination unit 301 determines that the merging of the combination (D, E) is closest to the restriction of the circuit.

The cone merge unit 303 sets the combination (D, E) of the partial circuits as a new divided partial circuit "E-1". As a result, it is possible to obtain a result close to a case where the entire circuit is optimized without performing division.

Of course, it is also possible to combine the logical dividing unit 104 according to the second embodiment with the dividing optimizing unit 106A according to the third embodiment.

It should be noted that the present invention is not limited to the above-described embodiment, and can be implemented with various modifications within the scope of the technical idea.

[0065]

As described above, according to the present invention,
The circuit before the change is divided into a plurality of partial circuits, and by retaining the division information, only the partial circuit that has undergone the design change is newly logically optimized, and the remaining partial circuits are the circuits before the change. By reusing, changes in the circuit can be made as small as possible. As a result, when expressing a circuit using actual physical elements such as transistors, even if the design changes, the parts that have not changed can be used as they are, and the parts that have changed Only a new physical design need be performed, and the design when a change occurs can be simplified.

Further, by dividing the circuit and handling it,
Each time, the circuit scale handled by the optimization unit is very small compared to the whole, enabling high-speed processing and dividing the circuit by counting the number of fan-outs of circuit elements. If the storage capacity of the computer is prepared linearly, it is possible to handle a circuit having a very large circuit scale.

Further, by creating a somewhat large divided circuit by merging the divided partial circuits, it is possible to perform the logical optimization individually on the divided partial circuits as in the present invention without dividing the circuit. It is possible to obtain a result close to the case of optimizing the whole.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a logic circuit synthesis system according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating processing of the logic circuit synthesis system according to the first embodiment.

FIG. 3 is an explanatory diagram schematically illustrating an example of first-time circuit synthesis according to the first embodiment of the present invention.

FIG. 4 is an explanatory diagram schematically illustrating an example of the synthesis of a change circuit according to the first embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration of a logical division unit according to a second embodiment of the present invention.

FIG. 6 is a flowchart illustrating a process performed by a logical division unit according to the second embodiment;

FIG. 7 is a diagram schematically illustrating an example of a logical division method according to the second embodiment of the present invention.

FIG. 8 is a block diagram illustrating a configuration of a division optimization unit according to a third embodiment of the present invention.

FIG. 9 is a flowchart illustrating processing performed by a division optimization unit according to the third embodiment.

FIG. 10 is an explanatory diagram schematically showing an example of merging of divided partial circuits according to the third embodiment of the present invention.

[Explanation of symbols]

 101 First circuit input unit 102 Previous circuit input unit 103 Changed circuit input unit 104 Logical division unit 105 Constraint input unit 106A Division optimization unit 106B New optimization unit 107 Reuse unit 108 Merging unit 109 Synthesis result output unit 110 Control unit 201 Circuit Classification unit 202 Cone generation unit 301 Merging determination unit 302 Merging optimization unit 303 Cone merge unit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-8-212246 (JP, A) JP-A-10-91651 (JP, A) JP-A-10-83416 (JP, A) JP-A-5-216 143675 (JP, A) Yuichi Nakamura, Takeshi Yoshimura, "A Partitioning-based Logic Optimization Met for large Scal Circuits with Biz Matrix," Research Institute of Electronics, Information and Communication Technology, Information Technology Society of Japan, Information and Communication Technology, Vol. 7, 1993, Information and Communication Society, Information Technology Society of Japan, Information Technology Society of Japan, Information Technology Society of Japan, Information Technology Society of Japan, Information Technology and Communications, pp. 1993, Information and Communication Technology, Information Communication Society of Japan, Information and Communication Technology, (1995), Information and Communication Technology, Information Technology Society of Japan, Information and Communication Technology, pp. 1993, Information Technology, Communications Society of Japan, Information and Communication Technology, 1995, Information and Communication Technology, Information Technology Society of Japan, Information and Communication Technology, pp. 95, 1993, Information and Communication Technology, LD. July, Vol. 95, No. 171, p. 15-21 (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 17/50

Claims (10)

(57) [Claims] 1. A method for converting a given logic circuit into a given surface
Logic circuit that optimizes to satisfy constraints such as product and delay
In the synthesis method, the logic circuit is configured based on circuit information of the input logic circuit.
Divided into a plurality of sub-circuits, and a logical
Performs optimization and synthesizes logic-optimized partial circuits.
When the logic circuit is changed, the result circuit is output as before.
And perform logic optimization only on the changed partial circuit.
For other partial circuits, the previous result circuit is left as it is.
Reuse and combine with the logic-optimized modified subcircuit
Output as result circuitAlong with In dividing the logic circuit into partial circuits, The circuit elements constituting the logic circuit are provided with a fan-out of 2
Classification of the above circuit elements and circuit elements with fanout of 1
And The circuit element having a fan-out of 2 or more is defined as a unit of division.
Connected to the input terminal of a circuit element with a fanout of 2 or more.
The circuit elements of fan-out 1 are merged together, The logic circuit based on the classification result and the merging result;
Is divided into partial circuits Logic circuit synthesis method characterized by the following:
Law. (2)In dividing the logic circuit into partial circuits
hand, The circuit elements constituting the logic circuit are provided with a fan-out of 2
Classification of the above circuit elements and circuit elements with fanout of 1
And The circuit element having a fan-out of 2 or more is defined as a unit of division.
Connected to the input terminal of a circuit element with a fanout of 2 or more.
The circuit elements of fan-out 1
By tracing until the above circuit elements are encountered,
Circuit element of fanout 2 or more and circuit element of fanout 1
Merge the children together, The logic circuit based on the classification result and the merging result;
Is divided into partial circuits 2. The method of claim 1, wherein:
Logic circuit synthesis method. (3)In the logic optimization processing of the partial circuit
hand, Discuss all neighboring combinations of divided subcircuits
Optimization. A circuit that is input at the time of optimization as a result of the logic optimization
Select the combination of partial circuits that is closest to the constraint A combination of the selected partial circuit and a new partial circuit
Claim 1 or Claim 2 Discussion of description
The method of logic circuit synthesis. (4)Given logic circuit, given surface
Logic circuit that optimizes to satisfy constraints such as product and delay
In a synthesis system, Logical component that divides the input logic circuit into multiple subcircuits
Splitting means, Constraints such as area and delay given to the partial circuit
Constraint input means for inputting For each of the partial circuits of the logic circuit input for the first time,
Partition optimization that performs logic optimization to satisfy the above constraints
Means, If a change occurs in the circuit, only the partial circuit in which the change occurred
New optimization means to perform new logic optimization on
When, After the first logic optimization for the changed partial circuit
A reuse means for retaining the result of New logic optimization with the partial circuit held in the reuse means
Merging means for merging partial circuits subjected to The result of the synthesis by the division optimization means or the merging means
Output means for outputting a merged result by The logical partitioning means comprises: The circuit elements constituting the logic circuit are fan-out.
Circuit element with 1 and circuit element with 2 or more fan out
Circuit element classifying means for classifying, A circuit element with a fan-out of 2 or more is a unit of division,
A fan connected to the input terminal of a circuit element
Merge and split circuit elements of main out 1
Corn generating means Arguments characterized by
Physical circuit synthesis system. Claim 5.For logic circuits where design changes are expected
First circuit input means for inputting the logic circuit first
When, Change section circuit input means for inputting the partial circuit after design change
Steps and Previous circuit to enter the logic circuit as the result of the previous synthesis
5. The apparatus according to claim 4, further comprising an input unit.
 The described logic circuit synthesis system. 6. The cone generating means has a fan-out.
Two or more of the circuit elements are used as a unit for division, and
Fan out connected to the input terminal of circuit element 2 or more
One circuit element is a fan-out circuit element of 2 or more
Follow up until you encounter
The above circuit element and the circuit element of fan-out 1
The logic circuit synthesis system according to claim 4, wherein the system is divided into partial circuits . 7.The partitioning logic optimization means, Discuss all neighboring combinations of divided subcircuits
Merging logic optimization means for performing logical optimization; A circuit that is input at the time of optimization as a result of the logic optimization
Merger that selects the combination of subcircuits closest to the constraint
Setting means, A combination of the selected partial circuit and a new partial circuit
Corn merge means,
To claim 4 The described logic circuit synthesis system. 8.The logical partitioning means comprises: The circuit elements constituting the logic circuit are fan-out.
Circuit element with 1 and circuit element with 2 or more fan out
Circuit element classifying means for classifying, A circuit element with a fan-out of 2 or more is a unit of division,
A fan connected to the input terminal of a circuit element
Merge and split circuit elements of main out 1
And a cone generating means, The partitioning logic optimization means, Discuss all neighboring combinations of divided subcircuits
Merging logic optimization means for performing logical optimization; A circuit that is input at the time of optimization as a result of the logic optimization
Merger that selects the combination of subcircuits closest to the constraint
Setting means, A combination of the selected partial circuit and a new partial circuit
Corn merge means,
To claim 4 The described logic circuit synthesis system. 9.Given logic circuit, given surface
Logic circuits optimized to satisfy constraints such as product and delay
Storage medium storing computer program for performing
Wherein the computer program performs the following processing:
Execute. Based on the input circuit information of the logic circuit,
Divide the logic circuit into multiple partial circuits, Logic to satisfy constraints input for each of the partial circuits
Performs optimization and synthesizes logic-optimized partial circuits.
Output the result circuit When changing the logic circuit, the result circuit is
Divided into Logic optimization is performed only for the changed partial circuit,
For other partial circuits, the previous result circuit is left as it is.
Reuse and combine with the logic-optimized modified subcircuit
And output it as a result circuit. In dividing the logic circuit into partial circuits, The circuit elements constituting the logic circuit are provided with a fan-out of 2
Classification of the above circuit elements and circuit elements with fanout of 1
And The circuit element having a fan-out of 2 or more is defined as a unit of division.
Connected to the input terminal of a circuit element with a fanout of 2 or more.
The circuit elements of fan-out 1
By tracing until the above circuit elements are encountered,
Circuit element of fanout 2 or more and circuit element of fanout 1
Merge the children together, The logic circuit based on the classification result and the merging result;
Is divided into sub-circuits.
Do. 10.The computer program comprises: In the logic optimization processing of the partial circuit, Discuss all neighboring combinations of divided subcircuits
Optimization. A circuit that is input at the time of optimization as a result of the logic optimization
Select the combination of partial circuits that is closest to the constraint A combination of the selected partial circuit and a new partial circuit
The method according to claim 9, wherein Logic circuit synthesis described
A storage medium for storing a computer program to be executed.