CN115048893A

CN115048893A - FPGA layout method for simplifying layout by modifying netlist

Info

Publication number: CN115048893A
Application number: CN202210736330.1A
Authority: CN
Inventors: 王新晨; 董志丹; 刘佩
Original assignee: Wuxi Zhongwei Yixin Co Ltd
Current assignee: Wuxi Zhongwei Yixin Co Ltd
Priority date: 2022-06-27
Filing date: 2022-06-27
Publication date: 2022-09-13

Abstract

The method firstly carries out initial layout on the basis of neglecting layout position association among logic units, improves the flexibility of layout position selection and reduces the position selection difficulty; and then, by properly adding and/or deleting the logic units and modifying the user input netlist on the premise of not changing the functional logic designed by the user, the layout position association between the logic units is restored and restored, a required layout result can be obtained, only one operation of modifying the original user netlist needs to be executed, the layout constraint does not need to be repeatedly checked in iteration, the layout process can be simplified on the basis of meeting the layout association constraint of the logic units, the layout difficulty is reduced, the layout time is shortened, and the layout efficiency is improved.

Description

FPGA layout method for simplifying layout by modifying netlist

Technical Field

The invention relates to the technical field of FPGA, in particular to an FPGA layout method for simplifying layout by modifying a netlist.

Background

A Field-Programmable Gate Array (FPGA) is a chip widely used in household appliances, large machinery and even aerospace. An Electronic Design Automation (EDA) tool is used for the FPGA chip, and the main flow of the EDA tool includes integration, packaging, layout, wiring, simulation verification, bit stream downloading and the like.

The layout is an important ring in the EDA tool, and the main function of the layout is to map the logic units in the user netlist to layout positions of the FPGA chip with actual physical coordinates one by one under an optimization target. The method comprises the steps that a part of logic units in a user netlist have dependency or constraint relations, and the layout positions of the logic units with the dependency or constraint relations in the FPGA often have constraint relations. For example, several logic cells constituting a carry chain must be placed in order in successive areas of the same column in the FPGA. In order to meet the layout requirements, layout constraints are often added to the logic units with dependency or constraint relationships. However, the added layout constraint increases the layout difficulty, on one hand, because of the existence of the layout constraint, the flexibility of selecting the layout position of the logic unit in the layout process is low, and on the other hand, after the layout position of the logic unit is adjusted each time, whether the layout constraint is met needs to be checked, the checking process needs to consume time, and the whole layout process needs to be adjusted for many times, so that the whole layout process consumes long time.

Disclosure of Invention

In view of the above problems and technical needs, the present applicant proposes an FPGA layout method for simplifying layout by modifying a netlist, and the technical solution of the present application is as follows:

a method of FPGA placement by modifying a netlist to simplify placement, the method comprising:

acquiring an original user netlist and determining associated layout groups in the original user netlist, wherein each associated layout group comprises at least two types of logic units with layout position association;

performing initial layout on the FPGA based on the original user netlist to obtain an initial layout result on the basis of ignoring layout position association of logic units in the association layout group;

modifying the original user netlist according to the initial layout result based on the layout position association among the logic units in the same associated layout group, and adding and/or deleting the logic units and the connected nets in the original user netlist to obtain a modified netlist, wherein the functional logic of the modified netlist is the same as that of the original user netlist, and the modified netlist comprises the layout position association of each associated layout group on the basis of the initial layout result;

and finishing layout based on the initial layout result according to the modified netlist.

According to a further technical scheme, the layout positions of at least two types of logic units contained in one associated layout group are associated to be that the at least two types of logic units are in the same layout area of the FPGA, and the method for adding and/or deleting the logic units in the original user netlist comprises the following steps:

modifying the original user netlist according to the operation of adding logic units in a layout region of the initial layout result so that all the logic units in the associated layout group are contained in the layout region at the same time;

and/or modifying the original user netlist according to an operation of deleting logic cells in a layout region of the initial layout result so that any logic cell in the associated layout group is not contained in the layout region.

The further technical scheme is that one associated layout group comprises a first type logic unit and a second type logic unit, the first type logic unit and the second type logic unit do not have a signal connection relation, and the layout position association of the first type logic unit and the second type logic unit is that the layout area comprising at least one first type logic unit must comprise the second type logic unit;

and when the original user netlist is modified, the modification is carried out according to the operation of deleting redundant second-type logic units and connecting nets thereof in the layout region which does not contain the first-type logic units in the initial layout result.

The further technical scheme is that initial layout is carried out on the FPGA based on the original user netlist to obtain an initial layout result, and the method comprises the following steps:

copying the original second-class logic units in the original user netlist, adding a plurality of second-class logic units and adding a net to obtain a preprocessed netlist, wherein the number of the second-class logic units contained in the preprocessed netlist is equal to the number of layout areas contained in the FPGA, and the functional logic of the preprocessed netlist is the same as that of the original user netlist;

and performing initial layout on each logic unit in the preprocessed netlist on the FPGA, and placing a second type logic unit in each layout region to obtain an initial layout result.

The method has the further technical scheme that the first type of logic units are idelay units, the second type of logic units are idelay yctrl units, and the method for adding the nets to the plurality of the second type of logic units added in a copying mode comprises the following steps:

adding the same wire mesh as the input end of the original idecayctrl unit to the input end of each idecayctrl unit with the added duplication;

and adding an AND gate and a line network between the AND gate and the output ends of all the idecayctrl units, so that the output ends of all the idecayctrl units after being copied and added are connected to the subsequent logic unit connected with the output end of the original idecayctrl unit through the AND gate.

The method for deleting the idecayctrl cells and the connected nets thereof from the layout area which does not contain the idecay cells when the original user netlist is modified comprises the following steps:

and deleting redundant idecayctrl units and the nets at the input ends thereof in the layout area which does not contain any idecay unit from the preprocessed net list, reserving the nets at the output ends of the redundant idecayctrl units, and modifying the signals of the nets provided by the redundant idecayctrl units for the output ends into VCC signals to obtain the modified net list.

The method comprises the following steps that a related layout group comprises a third type logic unit and a fourth type logic unit, a signal connection relation exists between the third type logic unit and the fourth type logic unit, and the layout positions of the third type logic unit and the fourth type logic unit are related to the fourth type logic unit and all the third type logic units connected with the fourth type logic unit are necessarily in the same layout area;

and after initial layout is carried out on the FPGA based on the original user netlist, the third type logic units connected with each fourth type logic unit are distributed in a plurality of layout areas, and when the original user netlist is modified, the fourth type logic units and the nets thereof are added in the layout areas which contain the third type logic units but not the fourth type logic units connected with the third type logic units.

The further technical scheme is that the third type logic unit is a register connected with a local clock, the fourth type logic unit is a local clock used for forming a global clock, and the method for increasing the local clock and the net thereof in the layout area which contains the register connected with the local clock but does not contain the local clock comprises the following steps:

the region clock is copied and added to the layout region containing the register but not the region clock connected to it, the added net to the output of the added region clock is connected to the register in the same layout region, and the added region clock is added to the input of the same net as the original region clock.

The beneficial technical effect of this application is:

the application discloses an FPGA layout method for simplifying layout by modifying a netlist, which comprises the steps of firstly carrying out initial layout on the basis of neglecting layout position association among logic units, improving the flexibility of layout position selection and reducing the difficulty of position selection; and then, by properly adding and/or deleting the logic units and modifying the user input netlist on the premise of not changing the functional logic designed by the user, the layout position association between the logic units is restored and restored, a required layout result can be obtained, only one operation of modifying the original user netlist needs to be executed, the layout constraint does not need to be repeatedly checked in iteration, the layout process can be simplified on the basis of meeting the layout association constraint of the logic units, the layout difficulty is reduced, the layout time is shortened, and the layout efficiency is improved.

The method is suitable for various layout position associations which may occur among the logic units, and has strong universality. And two different implementation modes are further provided according to whether the logic units have the direct connection relation or not, and the actual application requirements of association of different layout positions are met.

Drawings

Fig. 1 is a flowchart of a method of an FPGA layout method according to an embodiment of the present application.

Fig. 2 is a flowchart of a method of an FPGA layout method according to another embodiment of the present application.

FIG. 3 is a diagram illustrating the duplication and addition of nets for the second type of logic cells in the original user netlist, according to an example of the embodiment shown in FIG. 2.

FIG. 4 is a diagram illustrating the deletion of redundant second type logic cells and their nets in the example of FIG. 3.

Fig. 5 is a flowchart of a method of an FPGA layout method according to yet another embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application refers to the accompanying drawings.

The application discloses an FPGA layout method for simplifying layout by modifying netlist, which includes the following steps, please refer to the flowchart shown in fig. 1:

step 110, obtaining an original user netlist and determining associated layout groups in the original user netlist, where each associated layout group includes at least two types of logic units having layout position association, the layout position association indicates a layout position relative relationship between the logic units, and the logic units having the layout position association often have an association relationship in functional logic.

The different associated layout groups may contain different categories, number of categories, and layout position associations of logical units. Common associative layout groups are, for example, the logic cells forming the carry chain mentioned in the background section, such as the idelay cell and the idecayctrl cell, and so on.

And step 120, performing initial layout on the FPGA based on the original user netlist to obtain an initial layout result on the basis of ignoring the layout position association of the logic units in the associated layout group.

According to a conventional method, layout constraints are added to the logic units in the associated layout group according to the layout position association, and then initial layout and subsequent layout are performed based on the layout constraints, so that the logic units are uniformly moved and uniformly placed to meet the layout position association. At this stage, the layout position association between the logic units is not considered temporarily, that is, the layout constraint is not generated, and each logic unit can be flexibly initially laid out, so that the position selection of each logic unit is more flexible.

And step 130, modifying the original user netlist according to the initial layout result based on the layout position association among the logic units in the same association layout group, and adding and/or deleting the logic units and the nets connected with the logic units in the original user netlist to obtain a modified netlist.

The modified netlist has the same functional logic as the original user netlist, and includes layout position associations of each associated layout group on the basis of the initial layout result. Since the layout position association between the logic cells in the same associated layout group is not considered in step 120, the initial layout result obtained in step 120 is often not ideal enough, and may not satisfy the layout position association between the logic cells. The satisfied layout position associations are thus repaired at this step by modifying the original user netlist.

And step 140, finishing layout, subsequent wiring and other design processes based on the initial layout result according to the modified netlist. Since the modified netlist contains layout position associations of the associated layout groups on the basis of the initial layout result, the layout position associations can be satisfied after layout.

According to the method, the layout position association among the logic units is ignored firstly, and then the layout position association is repaired by modifying the original user netlist, so that on one hand, layout constraints do not need to be considered when the layout positions of the logic units are selected in the step 120, the position selection is more flexible, the layout difficulty is reduced, the layout time is reduced, on the other hand, only one operation of modifying the original user netlist is needed, the layout constraints do not need to be checked repeatedly in iteration, the layout difficulty is reduced, the layout time is reduced, and therefore the method can simplify the layout process on the basis of meeting the layout association constraints of the logic units and improve the layout efficiency.

In one embodiment, the layout positions of at least two types of logic units included in one associated layout group are associated such that the at least two types of logic units are in the same layout area of the FPGA, which is usually a clock domain. After the initial layout is performed in step 120 with the layout position association omitted, the following situations may occur: (1) all logic cells in the associated layout group are contained simultaneously in one layout area. (2) One layout area does not contain any logic cells in the associated layout group. (3) A layout area contains a portion of the logical units in the associated layout group.

Cases (1) and (2) already satisfy the layout position association of the logic cells in the associated layout group, and the original user netlist corresponding to the layout region does not need to be modified. And if the situation (3) does not satisfy the layout position association of the logic cells in the associated layout group, the original user netlist corresponding to the layout region needs to be modified.

There are two main modifications:

in the first method, the logic units in the associated layout group already included in the layout area are reserved, and the missing logic units in the associated layout group are added in the layout area, for example, the associated layout group includes a logic unit a and a logic unit B, and if only the logic unit a is in the layout area, the logic unit B is added in the layout area, so that the above-mentioned condition (1) is achieved. One way is therefore to modify the original user netlist based on the addition of logic cells in the associated layout group within one layout region of the initial layout result so that all logic cells in the associated layout group are contained simultaneously within the layout region. After the logic units in the associated layout groups are added, the corresponding net needs to be added to ensure that the functional logic remains unchanged.

And in a second mode, deleting the logic unit in the associated layout group already contained in the layout area, for example, if the associated layout group includes the logic unit a and the logic unit B, and if only the logic unit a is contained in the layout area, deleting the logic unit a in the layout area, so as to achieve the above-mentioned condition (2). Therefore, the second method for adding and/or deleting logic units in the original user netlist is as follows: and modifying the original user netlist according to the operation of deleting the logic cells in one layout region of the initial layout result, so that any logic cell in the associated layout group is not contained in the layout region. However, in this manner, after deleting the logic cells in the associated layout group from the layout area, it is still necessary to ensure that the associated layout group exists and the functional logic remains unchanged, so the deleted logic cells are often some redundant logic cells, and after deleting the logic cells, the nets related to the logic cells also need to be deleted.

Based on the two methods for modifying the original user netlist, in one embodiment, one association layout group includes a first type logic unit and a second type logic unit, the first type logic unit and the second type logic unit do not have a signal connection relationship, and the association of the layout positions of the first type logic unit and the second type logic unit is that the layout area including at least one first type logic unit must include the second type logic unit. When the original user netlist is modified according to the initial layout result, the embodiment is generally modified in the above manner two, namely, by deleting redundant logic cells.

A typical case of conforming to this scenario is: when the two types of logic units are arranged, the idecayctrl unit is required to be arranged in a clock domain where the idecayctrl unit exists, the idecayctrl unit is used for ensuring that the idecayctrl unit in the same clock domain normally works, a plurality of idecay units in the clock domain can be arranged, and no direct connection relation exists between the idecay units and the idecayctrl unit. Conventional practice would utilize layout constraints to ensure that the idelay cell and the idelaytrl cell are both present in a certain clock domain, i.e., the logic cells can be freely placed within a certain range, but cannot be beyond that range.

The method does not consider the layout position association between the idelay unit and the idelaytrl unit and does not add layout constraint. For an original user netlist, the number of included idelay cells is often large, and the number of idelay cells is small, so that if initial layout is performed on an FPGA directly based on the original user netlist, the situation that no idelay cell exists in a clock domain of the idelay cell is easy to occur. However, because the idecayctrl cell is not in a direct signal connection relationship with the idecay cell, if the idecayctrl cell is added in the clock domain after the initial layout, it is difficult to determine how to add a net to the added idecayctrl cell to ensure that the functional logic remains unchanged before and after the addition.

In this embodiment, please refer to the flowchart shown in fig. 2, first copy the original second-type logic units in the original user netlist, add a plurality of second-type logic units, and add a net to obtain a preprocessed netlist, where the number of the second-type logic units included in the preprocessed netlist is equal to the number of layout areas included in the FPGA, and the functional logic of the preprocessed netlist is the same as that of the original user netlist. And then, performing initial layout on each logic unit in the preprocessed netlist on the FPGA, and placing a second type logic unit in each layout region to obtain an initial layout result.

That is, the initial layout is not directly performed according to the original user netlist, but the operation of preprocessing the original user netlist exists, the second type of logic units are copied and added according to the number of layout areas, and because the number of the second type of logic units in the preprocessed netlist is equal to that of the layout areas, when the initial layout is performed on the FPGA according to the original user netlist and the preprocessed netlist, one second type of logic unit can be guaranteed to exist in each layout area. For the second type of logic units added by copying, corresponding nets need to be added according to actual functional logic, so that the whole functional logic remains unchanged.

Therefore, after initial layout, each layout area is provided with one second type logic unit, and if each layout area is provided with the first type logic unit, the layout position association of the first type logic unit and the second type logic unit is met. If only part of the layout area has the first type of logic units, the second type of logic units in the layout area without the first type of logic units are redundant, and then the original user netlist is modified according to the second mode according to the operation of deleting the redundant second type of logic units and the connecting nets thereof in the layout area which does not contain the first type of logic units in the initial layout result.

Therefore, in this embodiment, the method actually includes two modifications to the original user netlist, the first modification to the original user netlist adds logic cells and their nets to obtain a preprocessed netlist, and after the initial layout, the redundant logic cells and their nets are deleted from the preprocessed netlist to implement the second modification to the original user netlist.

In the example of the idelay cell and the idelaytrl cell, when the original user netlist is modified for the first time to add logic cells and their nets to obtain a preprocessed netlist, a method for adding nets to a plurality of second-class logic cells added by copying is as follows: the same net as the input of the original idecayctrl cell is added to the input of each idecayctrl cell with the copy added. And adding an AND gate and a line network between the AND gate and the output ends of all the idecayctrl units, so that the output ends of all the idecayctrl units after being copied and added are connected to the subsequent logic unit connected with the output end of the original idecayctrl unit through the AND gate. The and gate may be implemented in the FPGA in the form of a slice.

For example, referring to fig. 3, the FPGA includes 20 clock domains, and only one idecaycrl unit is named IDELAYCTRL _1 in the original user netlist, and the input terminals of the original idecaycrl unit include REFCLK and RST, where REFCLK is used to connect the O port of the BUFG _ inst unit, and RST is used to connect the a port of the SLICE _ inst. The output RDY1 of the original idelaytrl unit is connected to the O port of the IOB _ inst unit.

Then the original idecaycrl unit is first copied and an additional 19 idecaycrl units are added, named IDELAYCTRL _ 2-IDELAYCTRL _20, according to the method provided in this example. After the copy addition, 20 idecaycrl units are arranged, so that one idecaycrl unit can be arranged in each clock domain.

The same net as the input of the original idecaycrl unit is added to the input of each idecaycrl unit added by replication, that is, 19 newly added idecaycrl units IDELAYCTRL _ 2-IDELAYCTRL _20 are the same as IDELAYCTRL _ 1: REFCLK is connected to the O port of BUFG _ inst unit and RST is connected to the A port of SLICE _ inst.

And adding and gates and the nets between the and gates to the outputs of all the idelaytrl units, wherein the signals at the outputs of all the idelaytrl units are processed by and gates to be connected with the output of the original idelaytrl unit after operation, namely the O port of the IOB _ inst unit in the embodiment. When the AND gates are added, corresponding digits and the AND gates with corresponding numbers can be added according to the numbers, and a multi-level relation can be formed between the AND gates. For example, in the example shown in fig. 3, 7 4-input AND gates are added, which are AND1 to AND7, 16 input terminals of AND gates AND1 to AND4 are connected to the output terminals of 16 idecaycrl units, which are written as RDY1 to RDY16, the output terminals of AND1 to AND4 are connected to 4 input terminals of AND gate AND5, the output terminal of AND5 AND the output terminals of 3 idecaycrl units are written as RDY17 to RDY19, which are connected to 4 input terminals of AND gate AND6, the output terminal of AND6 AND the output terminals RDY20 AND VCC signals of the remaining 1 idecaycrl units are connected to 4 input terminals of AND gate AND7, AND the output terminal of AND7 is connected to the O port of IOB _ inst unit. Therefore, any idelaycltrl unit which is finally used can legally control the idelayy unit of the clock domain where the idelaycltrl unit is located.

Therefore, the second type of logic unit and the net are added in the original user netlist on the basis of ensuring that the functional logic is unchanged, and the preprocessed netlist is obtained. And then, carrying out initial layout on the FPGA according to the preprocessed netlist, so that an idelaytrl unit is placed in each layout area. And then deleting the idecayctrl cells and the connected nets thereof from the layout area which does not contain any idecay cell when the original user netlist is modified.

For example, in the example shown in fig. 3, assuming that IDELAYCTRL _1 to IDELAYCTRL _20 are respectively placed in the layout areas 1 to 20, after the initial layout, the

layout areas

3, 8 and 19 contain idelay cells, all the remaining 17 idelay cells in the layout area that does not contain idelay cells should be deleted, so that only IDELAYCTRL _3, IDELAYCTRL _8 and IDELAYCTRL _19 are reserved. After 17 idecayctrl units needing to be deleted are deleted, all nets at the input ends of the 17 idecayctrl units are deleted, but the AND gates and the nets at the output ends of the 17 idecayctrl units are reserved, but signals provided by the 17 idecayctrl units to the nets at the output ends need to be modified into VCC signals, as shown in FIG. 4, except for RDY3, RDY8 and RDY19 output by IDELAYCTRL _3, IDELAYCTRL _8 and IDELAYCTRL _19, signals acquired by other input ends of the AND gates are VCC signals. The

layout areas

3, 8, 19 thus all satisfy the layout position association between the idelay cell and the idelaytrl cell.

Based on the above two methods for modifying the original user netlist, in another embodiment, one associated layout group includes a third type logic unit and a fourth type logic unit, a signal connection relationship exists between the third type logic unit and the fourth type logic unit, and the layout positions of the third type logic unit and the fourth type logic unit are associated such that the fourth type logic unit and all the third type logic units connected thereto must be in the same layout area. This embodiment is generally modified in the manner described above, i.e., by adding missing logic cells, when modifying the original user netlist based on the initial placement results.

A typical case of conforming to this scenario is: the third type of logic unit is a register connected by a local clock, and the fourth type of logic unit is a local clock (RCLK) used for forming a global clock. When the requirement of the global clock GCL on the chip exceeds the number of resources, the global clock GCL can be realized by combining a plurality of local clocks RCLK and the registers REG connected with the local clocks RCLK, and the realization method requires that the local clocks RCLK and the registers REG connected with the local clocks RCLK are necessarily located in the same layout area, namely, the layout position association between the local clocks and the registers connected with the local clocks GCL is realized.

The registers REG connected by the region clock RCLK are often in a large number and may exceed the number of resources of one layout region, and the number of resources of the layout region needs to be satisfied during initial layout, so the common practice is to split the RCLK and complete the layout by using a plurality of layout regions. For example, the RCLK connections REG1, REG2, REG3, REG4 exceed the number of resources in a single layout region, the conventional method would first split the RCLK into RCLK1 and RCLK2 according to the number of resources in the layout region, the input end nets of RCLK1 and RCLK2 are the same as RCLK, RCLK1 connects REG1 and REG2, and RCLK2 connects REG3 and REG4, so that the number of resources in each layout region can meet the resource requirement. There is also a layout position association between the split region clock and its connected registers, i.e. RCLK1 and its connected REGs 1 and REG2 must be in one layout region, and RCLK2 and its connected REGs 3 and REG4 must be in one layout region, and two sets of layout constraints are added separately in the conventional practice. However, this not only increases the difficulty, but also may lead to an undesirable layout result, and even a layout result cannot be obtained, for example, in the case that there are no two sets of layout constraints, it may be that RCLK1 and REG1 and REG4 are in a layout region, and the layout result is better when RCLK2 and REG2 and REG4 are in a layout region, and then the two sets of layout constraints are added, so that it is finally impossible to achieve the better layout result, and if these layout constraints are mutually tied to other constraints, it may lead to a legal layout not being obtained.

In the method of the present application, first, the area clock is not split, and the layout position association between the area clock and the register connected to the area clock is not considered, but the initial layout is performed on the FPGA according to the original user netlist, please refer to the flowchart shown in fig. 5, because the initial layout is performed respectively under the condition that the layout position association is not considered, and the initial layout is limited by the number of resources in the layout area, the third type of logic units connected to each fourth type of logic unit may be distributed in one or more layout areas, and this embodiment takes as an example that the layout area where the fourth type of logic unit is located at least includes one third type of logic unit connected to the fourth type of logic unit. And when the third type logic units connected with the fourth type logic units are all in the same layout area with the fourth type logic units, the layout position association is satisfied. More particularly, the third type of logic units connected to the fourth type of logic units are distributed in a plurality of layout areas, and when the original user netlist is modified, the original user netlist is modified according to the operation of adding the fourth type of logic units and the net thereof in the layout area containing the third type of logic units but not the fourth type of logic units connected to the third type of logic units, so that the modified netlist is obtained. The difference between this embodiment and the embodiment shown in fig. 2 is that in this embodiment, there is a direct connection relationship between the third type logic cells and the fourth type logic cells, so generally, by adding the fourth type logic cells, it can be determined how to add nets according to the connection relationship, so that it is not necessary to add logic cells first and then delete redundant logic cells as in the embodiment of fig. 2, and it is possible to directly add required logic cells after the initial layout.

In the example of a local clock and its connected registers, a method of adding a local clock and its nets in a layout area that contains local clock connected registers but not local clocks includes: the region clock is copied and added to the layout region containing the register but not the region clock connected to it, the added net to the output of the added region clock is connected to the register in the same layout region, and the added region clock is added to the input of the same net as the original region clock.

For example, a region clock RCLK1 connects registers REG1, REG2, REG3, REG4, and after the initial layout, region clocks RCLK1 and REG1 and REG4 are in one layout region 1 and REG2 and REG3 are in another layout region 2. Then the region clock RCLK2, which is a replica of region clock RCLK1, is added to layout region 2 and the input of region clock RCLK2 is added to the net connected to the input of the original region clock RCLK1 and the output of region clock RCLK2 is added to the net connected to REG2 and REG3 within the same layout region. Therefore, layout position association is satisfied in each layout region, so that the processing is equivalent to splitting an original region clock, but the implementation mode is simpler, and the obtained layout result can be better.

Claims

1. A method for FPGA placement by modifying a netlist to simplify placement, the method comprising:

performing initial layout on the FPGA based on the original user netlist to obtain an initial layout result on the basis of ignoring layout position association of logic units in an associated layout group;

modifying the original user netlist based on the layout position association among the logic units in the same associated layout group according to the initial layout result, and adding and/or deleting the logic units and the nets connected with the logic units in the original user netlist to obtain a modified netlist, wherein the functional logic of the modified netlist is the same as that of the original user netlist, and the modified netlist comprises the layout position association of each associated layout group on the basis of the initial layout result;

and finishing the layout based on the initial layout result according to the modified netlist.

2. The method of claim 1, wherein layout positions of at least two types of logic cells included in one associated layout group are associated such that the at least two types of logic cells are in the same layout area of the FPGA, and the method for adding and/or deleting logic cells in the original user netlist comprises:

modifying the original user netlist according to an operation of adding logic cells in a layout region of the initial layout result so that all logic cells in the associated layout group are contained in the layout region at the same time;

and/or modifying the original user netlist according to the operation of deleting logic units in a layout region of the initial layout result, so that any logic unit in the associated layout group is not contained in the layout region.

3. The method of claim 2, wherein an association layout group comprises a first type logic unit and a second type logic unit, wherein the first type logic unit and the second type logic unit do not have a signal connection relationship, and the layout positions of the first type logic unit and the second type logic unit are associated such that the second type logic unit must be included in a layout area including at least one first type logic unit;

and each layout area contains a second logic unit after initial layout is carried out on the FPGA based on the original user netlist, and when the original user netlist is modified, the modification is carried out according to the operation of deleting redundant second logic units and connecting nets thereof in the layout area which does not contain the first logic units in the initial layout result.

4. The method of claim 3, wherein the performing an initial placement on the FPGA based on the original user netlist to obtain an initial placement result comprises:

copying the original second type logic units in the original user netlist, adding a plurality of second type logic units and adding a net to obtain a preprocessed netlist, wherein the number of the second type logic units contained in the preprocessed netlist is equal to the number of layout areas contained in the FPGA, and the functional logic of the preprocessed netlist is the same as that of the original user netlist;

5. The method of claim 4, wherein the first type of cell is an idelay cell, wherein the second type of cell is an idelay yctrl cell, and wherein adding nets to the number of second type of cells added for replication comprises:

6. The method of claim 5, wherein the method of deleting an idecayctrl cell and its connected nets from a layout area that does not contain an idecay cell when modifying the original user netlist comprises:

and deleting redundant idecayctrl units and the nets at the input ends thereof in the layout area which does not contain any idecay unit from the preprocessed netlist, reserving the nets at the output ends of the redundant idecayctrl units, and modifying the signals of the nets which are provided for the output ends by the redundant idecayctrl units into VCC signals to obtain the modified netlist.

7. The method of claim 2, wherein an associated layout group comprises a third type logic unit and a fourth type logic unit, wherein the third type logic unit and the fourth type logic unit have a signal connection relationship, and the layout positions of the third type logic unit and the fourth type logic unit are associated such that the fourth type logic unit and all the third type logic units connected thereto must be in the same layout area;

and after initial layout is carried out on the FPGA based on the original user netlist, distributing the third type logic units connected with each fourth type logic unit in a plurality of layout areas, and when the original user netlist is modified, adding the fourth type logic units and the net thereof in the layout area containing the third type logic units but not the fourth type logic units connected with the third type logic units.

8. The method of claim 7, wherein the third type of logic cells are local clock-connected registers, the fourth type of logic cells are local clocks used to form global clocks, and the method of adding local clocks and their nets in layout areas that contain local clock-connected registers but not local clocks comprises:

the region clock is copied and added to the layout region containing the register but not the region clock to which it is connected, the added net to the output of the added region clock is connected to the register in the same layout region, and the added region clock is added to the input of the same net as the original region clock.