KR20020036471A - Method for making VHDL codes with flow chart conversion from IP interface waveform - Google Patents

Abstract

PURPOSE: A method for generating a VHDL(Very High-speed integrated circuit Description Language) code by using the waveform transformation of an IP(Internet Protocol) interface is provided to be usefully applied to the designing of an asynchronous circuit excluding a main clock. CONSTITUTION: The method comprises steps of tabulating a truth table by enlarging a rising edge section in an optional sequential circuit waveform and dividing the waveform of input and output signals into many motion sections in a specific sequence(S1), classifying the input signals into a level signal and a pulse signal based on the output signals on the truth table(S2), simplifying the truth table and settling the remaining motion sequence(S3), drawing a flow chart of the remaining motion sequence depending on respective output signals(S4), writing a VHDL source code by referring to the flow chart(S5), and synthesizing an asynchronous electronic circuit with the VHDL source code by using a CAD(Computer-Aided Design) tool(S6).

Description

Method for making VHDL codes with flow chart conversion from IP interface waveform

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for designing electronic circuits that can generate logic circuits from any timing diagram presented, in particular using a main clock such as a processor and an IP (Intellectual Property) or handshaking signals between IP and IP. The present invention relates to a method for generating a sequential circuit that can be usefully used in designing an asynchronous circuit that does not.

Conventionally, in order to design a logic circuit from an arbitrary timing waveform, a transition diagram is created by representing the current state and the next state as a state diagram, the logic equation is extracted, and a master flip-flop circuit is applied. After that, the sequential circuit is designed to generate the circuit in the second order by applying the slave flip-flop circuit. Such a conventional method is a method of previously setting a master flip-flop and a slave flip-flop to be applied in advance to generate a circuit corresponding thereto, and a main clock must be applied and generated through two procedures. The problem is that the method is very complex and difficult to implement.

In addition, Janus algorithm is a method that can synthesize pulsed sequential circuit using only the presented timing waveform. The Janus algorithm takes as input the event-driven timing waveforms for both IPs, converts them into Even graphs, and then uses three types of templates, SR-latch and D-FF, for synchronous and asynchronous characteristics. It is a method to generate a logic circuit through the synthesis process after applying accordingly. This method also has difficulty in implementing an asynchronous pulse type sequential circuit because the main clock must be applied while using the SR-latch and D-FF.

Therefore, these conventional sequential circuit generation methods are not applicable to the design of an IP interface logic circuit having a data-flow circuit structure that executes an instruction based on arrival of a command or data instead of using a main clock. There is this. In other words, when the main clock is applied to the flip-flop type used in the IP interface logic circuit, the sequential circuit generation method becomes synchronous, and after that, the circuit must be converted asynchronously according to the characteristics of each interface target IP. The application is very demanding. In addition, when designing as an asynchronous circuit without using the main clock at all, there is a problem in that the sequential circuit generation method cannot be applied.

The present invention has been made to solve the above problems. When only timing waveforms in which a level input and a pulse input are mixed are presented, a truth table of the waveform is generated, the components are classified, and the process is simplified. Asynchronous circuit design that converts individual output signals into a flow chart according to the waveform operation sequence, inserts a VHDL (very high speed integrated circuit description language) code and extracts the VHDL source code without using the main clock. It is an object of the present invention to provide a method of generating VHDL code by waveform conversion, which can be usefully applied to a system.

1 is a flowchart illustrating a waveform conversion algorithm according to the present invention;

Figure 2 is a block diagram according to one embodiment of the interface logic application signals according to the present invention;

3 is a waveform diagram according to an embodiment of an interface logic circuit according to the present invention;

4 is a modified waveform diagram in which the rising edge section of the waveform shown in FIG. 3 is enlarged and divided;

4A is a truth table according to the operation sequence of FIG. 4;

FIG. 5 is a truth table classifying and displaying signal components of the truth table of FIG. 4B;

6 is a truth table grouping the same output signal groups in the truth table of FIG. 5;

6A is a truth table in which input signal components are determined based on IBF output in the truth table of FIG. 6;

6B is a truth table in which input signal components are determined based on INTR output in the truth table of FIG. 6;

7 is a flowchart of converting the truth table of FIG. 6A according to one embodiment;

8 is a flowchart of a conversion of the truth table of FIG. 6B according to one embodiment;

9 is a VHDL code prepared according to an embodiment by combining the flowcharts of FIGS. 7 and 8;

10 is an interface logic circuit synthesized according to an embodiment using an existing CAD tool with the VHDL code of FIG. 9;

FIG. 11 is a simulation diagram illustrating the interface logic circuit of FIG. 10 according to an embodiment using an existing CAD tool.

VHDL code generation method by converting the flow chart of the IP interface waveform in accordance with the present invention for achieving the above object, an electronic circuit design capable of generating a logic circuit with a timing diagram mixed with any level input and pulse input A method, comprising: a first step of enlarging a rising edge section of an arbitrary sequential circuit waveform, dividing a waveform of an input and an output signal into a plurality of operation sections, and determining an operation sequence to prepare a corresponding truth table; Classifying the input signals into level signals and pulse signals based on output signals in the truth table; A third step of simplifying the truth table of the second step and then determining the remaining operation sequence remaining; A fourth step of preparing a flowchart of a residual operation sequence corresponding to each output signal from the truth table of the third step; A fifth step of creating VHDL source code from the flowchart of the fourth step; And a sixth step of synthesizing an asynchronous electronic circuit using a conventional CAD tool from the VHDL source code created in the fifth step.

The method may further include: a first step of expanding a rising edge section of an arbitrary sequential circuit waveform in a computer, dividing a waveform of an input and an output signal into a plurality of operation sections, and determining an operation order to create a corresponding truth table; Classifying the input signals into level signals and pulse signals based on output signals in the truth table;

A third step of simplifying the truth table of the second step and then determining the remaining operation sequence remaining; A fourth step of preparing a flowchart of a residual operation sequence corresponding to each output signal from the truth table of the third step; A fifth step of creating VHDL source code from the flowchart of the fourth step; And a sixth step of synthesizing an asynchronous electronic circuit using a conventional CAD tool from the VHDL source code created in the fifth step, and providing a computer-readable recording medium having recorded thereon a program capable of executing.

Hereinafter, a VHDL code generation method by converting a flowchart of an IP interface waveform according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a flowchart illustrating a waveform conversion algorithm of the present invention, FIG. 2 is a block diagram according to an embodiment of signals applied to an interface logic circuit of the present invention, and FIG. 3 is a waveform according to an embodiment of an interface logic circuit. As a figure, these are demonstrated in more detail as follows.

The present invention proposes an algorithm that can generate a VHDL code from an arbitrary presented pulsed sequential waveform called a waveform conversion algorithm.

IP interface waveform to VHDL code creation algorithm using a flow chart conversion (Wave2VHDL algorithm) is an asynchronous sequential waveform for handshaking.When a waveform is presented, the waveform is converted into a flowchart and converted into a VHDL code by the converted flowchart. As an alternative algorithm, "In asynchronous waveforms with mixed level and pulsed inputs, create a truth table of the waveform, classify the components, and convert the individual output signals into flowcharts according to the waveform's sequence of operations. An algorithm for circuit design that allows you to create asynchronous electronics using CAD tools by inserting code and then completing the VHDL source. 1 is a flowchart illustrating a method of implementing such an algorithm.

FIG. 1 is a waveform of the handshaking and request and response portions shown in FIG. 2, and when the asynchronous sequence circuit waveform shown in FIG. A method of generating an IP interface logic circuit as a circuit is shown. That is, when the strobe signal (/ STB, 11) and the read signal (/ RD, 12) of the waveform as shown in FIG. 3 are inputted, the output signals of IBF ((Interrupt BufferFull, 13) and INTR 14 are outputted. This is how to create a sequential circuit.

First, referring to FIG. 3, characteristics of the interface circuit are as follows. The interface circuit receives the strobe input (/ STB, 11) from the peripheral IP, outputs an interrupt buffer full (IBF) 13, and pulls the IBF 13 at the rising edge of the read signal (/ RD, 12). Should quit. In FIG. 3, the / STB signal 11 and the RD 12 are handshaked, and the IBF 13 becomes a request signal. The STB signal 11 is a level input and the RD 12 is an edge input. Therefore, this part should be designed as a sequential circuit mixed with a level signal and a pulse signal. In addition, in FIG. 3, an INTR (interrupt) output 14 is also output in response to the STB 11 and the RD input 12.

FIG. 4 is a modified waveform diagram in which the rising edge section of the waveform shown in FIG. 3 is enlarged and partitioned, FIG. 4A is a truth table according to the operation sequence of FIG. 4, and FIG. 5 is a classified and displayed signal component of the truth table of FIG. 4B. 6 is a truth table grouping the same output signal groups in the truth table of FIG. 5, FIG. 6A is a truth table in which input signal components are determined based on an IBF output in the truth table of FIG. 6, and FIG. A truth table in which an input signal component is determined based on an INTR output in a truth table, FIG. 7 is a flowchart of converting the truth table of FIG. 6A according to an embodiment, and FIG. 8 is a flowchart of converting the truth table of FIG. 6B according to an embodiment. 9 is a VHDL code created according to an embodiment by combining the flowcharts of FIGS. 7 and 8, and FIG. 10 is an interface logic circuit synthesized according to an embodiment using an existing CAD tool with the VHDL code of FIG. 9. FIG. 11 is a simulation diagram of an interface logic circuit of FIG. 10 using an existing CAD tool, according to an embodiment, and a method of generating an interface circuit having such characteristics will be described in detail with reference to the flowchart of FIG. 1. Explained as follows.

First, by dividing the section in which the change of the output occurs in the implementation target waveform and the rising edge section by enlarging and defining the waveform operation sequence (S1).

In this case, the method of enlarging enlarges the input signal based on an input signal applied when the output is changed by the rising edge of the input signal. That is, since the INTR signal 14 is changed at the rising edge after the / STB signal 11 is input in FIG. 3, this section is enlarged as shown in FIG. 4, and the IBF signal 13 is at the rising edge of the / RD signal 12. Since this section should be enlarged as shown in FIG. 4, the truth table indicated by the upward arrow is prepared as shown in FIG. 4A.

Next, in the truth table of the waveform to be implemented, the signal components are classified into pulses when the output signal changes with respect to the rising edge, and levels when the previous state is maintained (S2). Specifically, FIG. 5 shows an example in which the truth table of FIG. 4A is classified. Referring to the waveform operation sequences 2 and 3 of FIG. 5, the output IBF is "level" because it maintains the previous state of the waveform operation sequence 2 in the waveform operation sequence 3, and "1" to "0" in the waveform operation sequences 5 and 6. As signal change occurred, it is classified as "pulse".

Also, the output INTR of waveform operation sequences 2 and 3 is "pulse" because the signal change occurred from "0" to "1", and since the previous state as waveform operation sequence 5 is maintained in waveform operation sequence 6, "level" Classified as " Therefore, signal components are classified by the coexistence of levels and pulses in waveform operation sequences 2 and 3 and waveform operation sequences 5 and 6.

Next, successive comparisons are made between the right directions of the waveform operation sequences in which " level and pulse coexist " classified in step S2, and the waveform operation sequence of the same output value is found and omitted (S3). A concrete example of this is shown in FIG. Referring to FIG. 6, waveform operations 3 and 4 are compared. Since the outputs are the same, the waveform 4 may be omitted. In this case, a comparison method is performed by logically exclusive OR between outputs of waveform operation sequence 3 and identical output rows of waveform operation sequence 4, and if the result value is "0", it is the same and if it is "1", it is different. Can be.

In addition, by comparing the outputs of the waveform operation sequence 4 and 5, 5 and 6, 6 and 7, 7 and 1, 1 and 2 in the above manner, the waveform operation sequence 7 and 1 can be omitted.

Accordingly, waveform operation sequences 2, 3, 5, and 6 remain, and FIG. 6A summarizes the components of the remaining waveform operation sequences with respect to the output signal IBF (STB is level, RD is pulse), and FIG. 6B is output signal INTR. This is a summary of the components of the remaining waveform operation sequences with respect to RD (level and STB pulse). This achieves the simplification of the truth table and the determination of the remaining operation sequence on the basis of the same output value to be achieved in the third step S3.

Next, one flowchart per output signal is created for the remaining waveform operation sequence. In this case, the level signal is used as a start point of the flowchart and is written to proceed in a right direction (S4).

Fig. 7 shows an example in which a truth table of the operation sequence of the residual waveform in Fig. 6A is shown in a flowchart, and Fig. 8 shows an example in which a truth table of the operation sequence of the residual waveform in Fig. 6B is created in a flowchart.

In Fig. 6A, the level signal is waveform operation procedure 2, from which the flowchart starts. Therefore, when STB is "0", IBF becomes "1" as the (1) comparative statement of the flowchart of FIG. When the STB is "1", the IBF becomes "0" only when RD is raised in the waveform operation sequence 6, and this is written as the (2) th comparison statement. In other cases, the waveform operation sequence is 3 and 5, in which case the previous state remains.

Also, in Fig. 6B, the level signal is waveform operation procedure 5, from which the flowchart starts. Therefore, when RD is "0", INTR becomes "0" as the (1) comparative statement of the flowchart of FIG. In the case where RD is "1", IBF becomes "1" only when STB is raised in waveform operation sequence 3, and this is made as the (2) th comparison statement. In other cases, it will be waveform operation sequence 6 and 2. At this time, the previous state will be maintained.

Next, a VHDL file is created from the flowchart of the fourth step S4. At this time, one Process statement is created for each flowchart, but starting from the flowchart with the level signal in which the waveform operation sequence takes precedence (S5).

In FIG. 9, a part indicated by flow chart # 1 (# 1 flow) corresponds to an IBF, and a part indicated by flow chart # 2 (# 2 flow) corresponds to an INTR.

As described above, the waveform conversion (Wave2VHDL) algorithm of the present invention has been described above, and the validity thereof is as follows.

In the waveform conversion algorithm of the present invention, a flow diagram designed as shown in FIGS. 7 and 8 was inputted from Mentor's Renoir99, synthesized into VHDL, and then simulated using a model simim (Synopsys). Circuit synthesis was performed in VSS.

In addition, by inputting the VHDL code prepared as shown in FIG. 9 in the VHDL synthesizer of the load cap (LODECAP) applying the 0.8㎛ SOG process rule of ETRI, it was possible to synthesize the interface circuit diagram as shown in FIG. In addition, a simulation result of FIG. 11 was obtained for the IBF and the INTR using the waveform editor of the load cap, which was the same as the timing diagram shown in FIG. 3. In FIG. 11, an unknown state is initially shown because a flip-flop is synthesized, which can be solved by a power on reset, and it can be confirmed that the same waveform is continuously applied.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

In the present invention as described above, when only asynchronous timing waveforms in which a level input and a pulse type input are mixed for IP and IP handshaking are presented, a truth table of the waveforms is prepared, the components are classified, and a simplified process is performed. After that, the individual output signals are converted into flow charts according to the waveform operation sequence, and the VHDL source code can be easily written after inserting the VHDL code step by step in the flow chart to easily generate asynchronous sequential circuit using existing CAD tools. This is useful for designing asynchronous circuits that do not use the main clock.

Claims (6)

A sequential circuit generation method capable of generating a logic circuit using a timing diagram in which an arbitrary level type input and a pulse type input are mixed, A first step of enlarging a rising edge section of an arbitrary sequential circuit waveform and dividing a waveform of an input and output signal into a plurality of operation sections to determine an operation order and to prepare a truth table corresponding thereto; Classifying the input signals into level signals and pulse signals based on output signals in the truth table; A third step of simplifying the truth table of the second step and then determining the remaining operation sequence remaining; A fourth step of preparing a flowchart of a residual operation sequence corresponding to each output signal from the truth table of the third step; A fifth step of creating VHDL source code from the flowchart of the fourth step; And And a sixth step of synthesizing an asynchronous electronic circuit using a conventional CAD tool from the VHDL source code created in the fifth step. The method of claim 1, The first step, And a magnified section on the basis of the input signal applied when the output is changed by the action of the rising edge among the input signals, and enlarges this to create a truth table represented by an arrow. The method of claim 1, The second step, And a signal component is classified into pulses when a change in an output signal occurs based on the rising edge of the input signal, and into levels when the previous state is maintained. The method of claim 1, The third step, And sequentially comparing the right directions of the waveform operation sequences in which the "level and pulse coexist" classified in the second step, find and omit the waveform operation sequences of the same output value. The method of claim 1, The fourth step, A flowchart of one waveform per output signal is prepared for the remaining waveform operation sequence after the simplification in the third step, and the level signal is created as a start point of the flowchart and proceeds to the right. How to create a sequential circuit. On your computer, A first step of enlarging a rising edge section of an arbitrary sequential circuit waveform and dividing a waveform of an input and output signal into a plurality of operation sections to determine an operation order and to prepare a truth table corresponding thereto; Classifying the input signals into level signals and pulse signals based on output signals in the truth table; A third step of simplifying the truth table of the second step and then determining the remaining operation sequence remaining; A fourth step of preparing a flowchart of a residual operation sequence corresponding to each output signal from the truth table of the third step; A fifth step of creating VHDL source code from the flowchart of the fourth step; And And a sixth step of synthesizing an asynchronous electronic circuit using a conventional CAD tool from the VHDL source code created in the fifth step.