JPH10173515A - Fpga device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an FPGA device capable of high-speed operation. SOLUTION: In this FPGA(field programmable ctate array) device, a logic block is composed of a signal-change detecting part 3 for detecting the change of a wiring signal between logic blocks for connecting logic blocks, a logic circuit part 4 for performing processing based on logic defining information, and an output signal storing part 5 for storing the output signal of the logic circuit part. Thus, the change of the wiring signal between the logic blocks for connecting logic blocks is detected, and the logic defining information of the logic circuit part 4 is automatically and orderly switched at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FPGA (Fiel
d Programmable Gate Array (hereinafter referred to as an FPGA) device, and in particular, automatically changes the logic definition information of the logic circuit section in a logic block due to a change in the wiring signal between the logic blocks connecting the logic blocks. , And switches sequentially.

[0002]

2. Description of the Related Art An FPGA device is characterized in that various circuits can be realized by rewriting logic definition information of a logic circuit. At present, there is a trend toward incorporating a memory in order to enable rewriting of logic definition information during operation and to speed up rewriting of logic definition information.

FIG. 5 shows an example of a configuration block diagram of a conventional FPGA device. In the figure, reference numeral 51 denotes an FPGA device,
The GA device 51 includes a plurality of logical blocks 52a, 52b, 52c, and 52d obtained by dividing a large-scale logical circuit into blocks.
And the logic circuit units 54a, 54b, 54 in the logic block
a logic switching control unit 56 that controls the switching of the logic of c and d, a logic definition information memory unit 57 that stores logic definition information of the logic circuit unit, and a wiring unit that is wired between logic blocks and is not described. It consists of.

FIG. 4 shows an example of a switching operation of a logic block of a conventional FPGA device. The switching operation will be briefly described with reference to FIG. FIG. 4A shows a logical definition information memory unit 47, which stores two pieces of switching logical definition information in this example. The logical definition information 49a stores the logical definition information A, B, C and D are stored, and logical definition information E, F, G, and H of four logical blocks are stored in the logical definition information 49b.

FIG. 4B is a diagram of logic definition information set in the FPGA device 41 in response to a logic switching request instruction performed in the initial setting at the time of power-on. In this example, A of the logical definition information 49a is stored in the logical block 42a, B of the logical definition information 49a is stored in the logical block 42b, C of the logical definition information 49a is stored in the logical block 42c, and the logical block 42d is stored in the logical block 42d. D of the logic definition information 49a is stored.

Then, the system operates, the CPU is requested to perform some processing, and the FPG is executed to execute the processing.
The CPU calculates the necessity of switching the logic definition information of the logic circuit unit of the A device 41, and the CPU transmits a logic switching request instruction to the FPGA device 41. Upon receiving the logical switching request instruction, the logical switching control unit 46 of the FPGA device 41 stores E of the logical definition information 49b in the logical block 42a, and stores F of the logical definition information 49b in the logical block 42b. G of the logic definition information 49b is stored in 42c,
H of the logic definition information 49b is stored in the logic block 42d. Thereby, the logic block 4 of the FPGA device 41
2a operates as logical definition information E, logical block 42b operates as logical definition information F, logical block 42c operates as logical definition information G, and logical block 42d operates as logical definition information H.

[0007]

However, in the prior art shown in FIG. 5, when the scale of a logic circuit to be realized in an FPGA device is large, the functions of a plurality of logic blocks are switched and used at the same time. Therefore, there is a problem that switching of the logic circuit in the logic block takes a very long time and cannot be used for a circuit that requires a high-speed operation.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and detects a change in a wiring signal between logic blocks connecting logic blocks in an FPGA device. A logic block includes a signal change detection unit, a logic circuit unit that performs processing based on the logic definition information, and an output signal storage unit that stores an output signal of the logic circuit unit. Thus, it is possible to detect a change in the wiring signal between the logical blocks connecting the logical blocks and to switch the logical definition information of the logical circuit portion automatically and step by step at high speed.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION A logic circuit section which performs processing based on logic definition information, and a change in a wiring signal between logic blocks connecting logic blocks, and a change in logic of the logic circuit section are logically switched. A logic block is composed of a signal change detection unit that instructs the control unit and an output signal storage unit that stores the output signal of the logic circuit unit, and the logic definition information of the logic circuit unit is automatically and sequentially switched. Thereby, high-speed operation becomes possible.

[0010]

FIG. 1 is a block diagram showing an example of the configuration of an FPGA device according to the present invention. In the figure, reference numeral 1 denotes an FPGA device,
The A device 1 includes a plurality of logic blocks 2a, 2b, 2c, and 2d obtained by dividing a large-scale logic circuit into blocks, a logic switching control unit 6 that controls switching of logic of the logic circuit unit 4 in the logic block, It is composed of a logic definition information memory section 7 for storing logic definition information of a logic circuit section, and a non-described wiring section for wiring between a plurality of logic blocks.

The logic block 2a detects a change in a wiring signal between the logic circuit unit 4 where the processing is performed based on the logic definition information and a wiring signal between the logic blocks connecting the logic blocks and detects the logic of the logic circuit unit 4. A signal change detection unit 3 for instructing a logic switching control unit to switch the logic, and a logic circuit unit 4
And an output signal storage unit 5 for storing the output signal. The logical blocks 2b, 2c, and 2d have the same configuration as the logical block 2a.

FIG. 2 shows a detailed block diagram of a logical block. With reference to this figure, switching of the logic definition information of the logic circuit unit 24 in the logic block 22 will be briefly described.

The logic block 22 shown in FIG. 2A includes signal change detection units 23a and 23b, a logic circuit unit 24, and an output signal holding unit 25. The wiring signal a is connected to the logic circuit unit 24 via the signal change detection unit 23a, and the wiring signal b is connected to the logic circuit unit 24 via the signal change detection unit 23b. Also, the signal change detection unit 23
a and the signal change detection unit 23b and the logic switching control unit are connected by a logic switching request signal a and a logic switching request signal b. The output of the logic circuit unit 24 is output to the next logic block by the output signal a or the output signal b via the output signal holding unit 25.

The logic circuit section 24 shown in FIG. 2A is composed of an AND gate and a flip-flop by an initial setting at the time of power-on, and receives an input signal from a wiring signal a to output an output signal a. Output.

When the signal change detector 23b detects a change in the signal of the wiring signal b, the signal change detector 23b outputs a logic switching request signal b to the logic switching controller. The logic switching control unit transfers the logic definition information stored in the logic switching information memory unit to the logic circuit unit 24. This allows
The logic circuit unit 24 includes the OR gate shown in FIG.
The logic circuit is switched to a logic circuit including an ND gate, receives an input signal from the wiring signal b, and outputs the received signal to the output signal b.

FIG. 3 shows an example of the switching operation of the logic blocks of the FPGA device of the present invention. The switching operation will be briefly described with reference to FIG. FIG. 3A is a configuration diagram of the logic definition information of the logic definition information memory unit 37. In this example, one piece of logic definition information 39 is stored. The logical definition information 39 stores the logical definition information of the logical blocks A, B, C, D, E, and F.

FIG. 3 (b) shows the initial setting when the power is turned on.
The logic blocks 32a, 32b, 32c of the GA device 31,
The logical definition information set in 32d is shown. A of the logical definition information 39 is stored in the logical block 32a.
Of the logical definition information 39, C of the logical definition information 39 in the logical block 32c, and D of the logical definition information 39 in the logical block 32d.

During the operation of the FPGA device 31, when the wiring signal wired from the logic block 32d to the logic block 32b changes, the logic block 32b
The signal change detection unit detects a change in the wiring signal and outputs a logic switching request signal to the logic switching control unit. The logic switching control unit 36 receives the logic switching request signal from the logic block 32b and sets the logic definition information E in the logic definition information memory unit 37 in the logic block 32b. FIG. 3C is a diagram in which E of the logic definition information 39 is set in the logic circuit portion of the logic block 32b.

Subsequently, when a wiring signal wired from the logic block 32b to the logic block 32d changes, the signal change detection unit of the logic block 32d detects a change in the wiring signal and sends a logic change to the logic switching control unit 36. It outputs a switching request signal. The logical switching control unit 36 is a logical block 32d
Receiving a logic switching request signal from the logic definition information memory unit 3
7 is set in the logical block 32d.
FIG. 3D is a diagram in which F of the logic definition information 39 is set in the logic circuit unit of the logic block 32d.

Subsequently, when a wiring signal wired from the logical block 32d to the logical block 32c changes, the signal changes from the logical block 32c to the logical block 3c.
2d and from the logical block 32c to the logical block 32b via the logical block 32a. The change in the wiring signal is detected by the signal change detection unit of the logic block 32b and the signal change detection unit of the logic block 32d, and a logic switching request signal is output to the logic switching control unit 36. The logic switching control unit 36 receives logic switching request signals from the logic blocks 32b and 32d, sets B of the logic definition information of the logic definition information memory unit 37 to the logic block 32b, and sets the logic of the logic definition information memory unit 37. The definition information D is set in the logical block 32d.

As a result, the FPGA device 31 is
Returning to the logical definition information of (a), A of the logical definition information 39 is stored in the logical block 32a, B of the logical definition information 39 is stored in the logical block 32b, and the logical definition information 3 is stored in the logical block 32c.
9 in the logical block 32d.
Is set.

[0022]

The present invention is embodied in the form described above, and has the following effects.

The logic switching unit performs processing based on the logic definition information, and detects a change in a wiring signal between the logic blocks connecting the logic blocks, and switches the logic of the logic circuit to the logic switching control unit. A logic block is composed of a signal change detection unit for instructing and an output signal storage unit for storing an output signal of the logic circuit unit, and the logic definition information of the logic circuit unit is automatically and sequentially switched to achieve high speed. An FPGA device capable of performing various operations can be provided.

[Brief description of the drawings]

FIG. 1 is a structural block diagram of an FPGA device according to the present invention.

FIG. 2 is a detailed structural block diagram of a logical block.

FIG. 3 is a diagram illustrating an example of a switching operation of a logic block of the FPGA device according to the present invention.

FIG. 4 is a diagram illustrating an example of a switching operation of a logic block of a conventional FPGA device.

FIG. 5 is a structural block diagram of a conventional FPGA device.

[Explanation of symbols]

 2a, 2b, 2c, 2d Logic block 3 Signal change detection unit 4 Logic circuit unit 5 Output signal storage unit

Claims (1)

[Claims] 1. A logic circuit unit (4) that performs processing based on logic definition information, and detects a change in a wiring signal between logic blocks connecting logic blocks and switches the logic circuit unit (4). And a signal change detection unit (3) for instructing the logic circuit unit (4) and an output signal storage unit (5) for storing the output signal of the logic circuit unit (4).
c, 2d), and automatically and sequentially switches the logic definition information of the logic circuit unit.
GA device.