JPH10173063A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To mount lateral bipolar transistors (L-PNP Tr), MIS capacitors and thin film resistor elements on a common substrate, with keeping the characteristic of each component good. SOLUTION: Using a first polysilicon film layer, take-up electrodes 9VB, 9LC, 9LE, capacitance-on-electrodes 9M of MIS capacitors and polysilicon resistance layer 9R are formed, the entire substrate surface is covered with a second SiN film layer 10, and a second SiOx layer insulation film 11 is deposited to form upper layer wiring contacts contg. a Ti type barrier metal 16. This SiN film 10 forms a diffusion barrier against H atoms remaining in the first layer insulation film 7 and resistance layer 9R, thus blocking the Ti barrier metal 16 from sucking up the H atoms. The second SiN film thickness is set independently of a capacitance insulation film 8M, thereby not hindering the increase of MIS capacitance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device in which a lateral bipolar transistor, a MIS capacitor using a SiN film as a capacitor insulating film, and a thin film resistor are mounted on a common semiconductor substrate. The present invention relates to an improvement in an element structure capable of preventing deterioration of characteristics of a lateral bipolar transistor and a thin film resistance element while increasing the capacity, and a manufacturing method for obtaining the element structure.

[0002]

2. Description of the Related Art In the field of ASICs (application-specific ICs) and logic LSIs, it is common practice to mount various elements such as bipolar transistors, MIS capacitors, and thin-film resistors on a common semiconductor substrate. FIGS. 9 to 12 show a conventional typical manufacturing process of such a semiconductor device.
This will be described with reference to FIG. In these drawings, a single semiconductor substrate is described in two upper and lower stages for the sake of space.
In the upper stage, a vertical NPN bipolar transistor (hereinafter, referred to as
Notated as V-NPNTr. ) And a lateral PNP bipolar transistor (hereinafter referred to as L-PNPTr).
And the lower part shows the MIS capacitance and polysilicon resistance formation areas, respectively. In addition, in the reference numerals used in the drawings, the suffix V of the alphabet is V-NPNTr, the suffix L is L-PNPTr, the suffix M is the MIS capacitance, and the suffix R is the structure or member related to each element of the polysilicon resistor. , Subscript B is base, subscript E is emitter,
The suffix C indicates a structure or member associated with each region of the collector. Note that these notations are the same in FIGS. 1 to 8 for describing embodiments to be described later.

FIG. 9 shows V-NPNTr and L-PNPT.
In a manufacturing process of a semiconductor device in which r, MIS capacitance, and polysilicon resistance are mixedly mounted on the same substrate, a region for forming a MIS capacitance is defined in a first interlayer insulating film 27 (SiOx) formed on the substrate. Open the capacity window 27M,
The figure shows a state in which the capacitance insulating film 28M is formed by patterning the SiN film so as to cover the capacitance window 27M.

The steps so far are roughly as follows. First, n-type impurities and p-type impurities are selectively introduced into the surface layer of the p-type Si substrate 21 (p-Sub) to form the buried layers 22V and 22L (n ⁺ -BL) and the channel stop 23, respectively. After that, an n-type epitaxial layer 24 (n-Epi) is formed on the entire surface of the substrate. Known LOCO
After the field oxide film 25 is formed by the S method, an n-type impurity is selectively introduced into a part of the element formation region, and V-NP
NTr collector extraction area 26VC, L-PNPTr
Of the MIS capacitor and a capacitor lower region 26M of the MIS capacitor are formed. After performing the impurity activation annealing, an interlayer insulating film 2 made of a SiOx film is formed on the entire surface of the substrate.
7 is deposited, and this film is patterned to form a capacity window 27M.
To form Further, a SiN film is deposited on the entire surface of the substrate, and this film is patterned to form a capacitance insulating film 28M covering the capacitance window 27M.

Next, as shown in FIG. 10, the first interlayer insulating film is patterned to open an extraction electrode window of the bipolar transistor. The extraction electrode window includes a base window 27VB of V-NPNTr, L-PNP
A collector window 27LC of Tr and an emitter window 27LE of L-PNP Tr. Next, the entire surface of the substrate is covered with a first-layer polysilicon film (1-polySi), and p-type impurities are introduced into the film. This first-layer polysilicon film is patterned so as to remain in the above-described extraction electrode window, and the base extraction electrodes 29VB, L-
PNP Tr collector extraction electrode 29LC and emitter extraction electrode 29LE, MIS capacitance upper electrode 29M,
And a resistance layer 29R of polysilicon resistance are formed.

Next, as shown in FIG. 11, a second interlayer insulating film 31 (SiOx) is deposited on the entire surface of the substrate,
An emitter window 31VE is opened in the formation region of -NPNTr, and p-type impurities are ion-implanted to form an intrinsic base region. Next, the SiO for forming the sidewall is formed.
x-film is deposited over the entire surface and an impurity diffusion annealing is performed to
A graft base region 33VB and an intrinsic base region 32 of NPNTr, and a collector region 33LC and an emitter region 33LE of L-PNPTr are formed, respectively. Next, the SiOx film for forming the sidewall is anisotropically etched back to form the sidewall 34 on the inner wall surface of the emitter window 31VE. Subsequently, a second polysilicon film (2-polySi) is deposited on the entire surface of the substrate, and n
Introduce type impurities. After the n-type impurity is diffused into the active region by performing annealing, the emitter region 36 of the V-NPNTr is formed. Then, the second polysilicon film is patterned to form the emitter extraction electrode 35VE.

Next, as shown in FIG. 12, the second interlayer insulating film 31 or, in addition to this, the first interlayer insulating film 27 is dry-etched to obtain each of the extraction electrodes or the substrate. A contact hole facing the extraction region is opened. Next, a laminated film of a Ti-based barrier metal 36 and an Al-based conductive film is formed on the entire surface of the base, and the laminated film is patterned to form a base electrode 37VB, an emitter electrode 37VE, and a collector electrode 37VC of the V-NPNTr. Forming an emitter electrode 37LE, a collector electrode 37LC, and a base electrode 37LB of the PNP Tr, a capacitance connection electrode 37M of a MIS capacitance, and a resistance connection electrode 37R of a polysilicon resistor; Finally, the entire surface of the base is covered with a passivation film (not shown) to complete the semiconductor device.

[0008]

However, in the semiconductor device manufactured as described above, the L-PN
Deterioration of PTr characteristics often becomes a problem. L-PNPT
In r, the surface portion of the n-type epitaxial layer 24 between the emitter region 33LE and the collector region 33LC surrounding the emitter region 33LE is used as a base active region.
The crystallinity of this region has a great effect on the device characteristics. In general, the higher the proportion of dangling bonds in the Si crystal lattice in this region that are terminated with terminating atoms, the lower the interface state density, the smaller the leakage current and noise, and the L-PNP Tr capable of high-speed operation. Become.

The terminating atom is usually a hydrogen (H) atom supplied from an SiOx-based interlayer insulating film. SiOx
In many cases, the system-based interlayer insulating film is formed by CVD using SiH ₄ or TEOS (tetraethoxysilane), so that H atoms, which are constituent atoms of these source gases, are considerably taken into the interlayer insulating film. Are diffused and auto-doped into the n-type epitaxial layer. Therefore, if a sufficient amount of H atoms is supplied from within the interlayer insulating film, the characteristics of the L-PNPTr will naturally be adjusted well.

Meanwhile, in a semiconductor device manufactured based on recent fine design rules, in order to prevent a pn junction breakdown due to an alloying reaction between an Al-based wiring and a base extraction electrode and a penetration of a diffusion layer. , Ti
System barrier metal is used. A general configuration of a Ti-based barrier metal is a laminated system of a Ti film for achieving an ohmic contact with a Si-based base material and a TiN film or a TiW film having a better barrier property than the Ti film. Is done. However, since Ti is a metal having a very high H storage capacity, the presence of the Ti-based barrier metal causes a shortage of H atoms to be supplied from the interlayer insulating film to the n-type epitaxial layer, deteriorating the characteristics of L-PNPTr. The problem has arisen. The problem is that in the future, from the viewpoint of improving the moisture resistance and the dielectric constant of the interlayer insulating film, residual H atoms in the film will be reduced, and the thickness of the interlayer insulating film itself will be reduced in thickness using a low dielectric constant material. Given that, it becomes more and more serious.

Therefore, in order to solve this problem, Si
By patterning the N film, the capacitance insulating film 28M of the MIS capacitance is formed.
It has been proposed to form a protective film in the region where L-PNPTr is formed at the same time. An example of a manufacturing process of the semiconductor device in this case will be described with reference to FIGS. Note that the reference numerals used in these drawings are the same as those in FIGS. 9 to 12 described above.

FIG. 13 shows the substrate shown in FIG.
This shows a state in which a protective film 28L in the L-PNP Tr region has been added. This protective film 28L is formed by patterning a SiN film common to the capacitance insulating film 28M. The protective film 28L is patterned together with the first interlayer insulating film 27 at the opening of the extraction electrode window in the next step. FIG. 14 shows a state in which a collector extraction electrode 29LC and an emitter extraction electrode 29LE are attached to the collector window 27LC and the emitter window 27L formed by this patterning, respectively. Thereafter, the processes up to the formation of the upper layer wiring as shown in FIG. 15 are performed by the same process as described above.

In the semiconductor device completed in this manner, the SiN film is also formed on the surface of the first interlayer insulating film 27 in the region where the L-PNPTr is formed, as is apparent from FIG.
In this state, the protective film 28L made of a film is left.
Therefore, if the thickness of the protective film 28L is sufficiently large, the Ti-based barrier metal 36 is removed from the first interlayer insulating film 27.
Is diffused by the protective film 28L, and dangling bonds near the surface of the n-type epitaxial layer 24 are efficiently terminated by H atoms supplied from the first interlayer insulating film 27. Will be done.

However, since the protective film 28L is formed using a common SiN film with the capacitance insulating film 28M of the MIS capacitance, there is a problem that it is difficult to secure a sufficiently large film thickness. That is, in recent semiconductor devices, the occupied area of each element is reduced with an increase in integration degree.
As for the capacity, it is required to secure a high capacity with a small area. To meet this demand, it is effective to reduce the thickness of the capacitive insulating film 28M.
Naturally, the protective film 28L also becomes thin. However, when the thickness is too small, the protective film 28L cannot block the diffusion of H atoms at a certain critical thickness, and the characteristics of the L-PNPTr rapidly decrease. Therefore, if priority is given to ensuring the characteristics of the L-PNP Tr, there is a problem that the MIS capacitance cannot be increased.

[0015] Further, H based on Ti-based barrier metal 36 is used.
The absorption of atoms is not limited to the above-mentioned interlayer insulating film,
It also arises from semiconductor films. In the semiconductor device shown in FIGS. 12 and 15, the resistance layer 29R of the polysilicon resistor is in direct contact with the second interlayer insulating film 31, but the second interlayer insulating film 31 is made of a Ti-based barrier metal. 36 serves as a passage for absorbing H atoms in the film from the resistance layer 29R, and as a result, the resistance value of the polysilicon resistor increases or fluctuates.

As described above, in the conventional semiconductor device structure and manufacturing method, the reliability of the wiring is increased and the MIS capacitance per unit area is increased while preventing the characteristic fluctuation of the L-PNP Tr and the thin film resistance element. It was difficult. Therefore, the present invention solves these problems and provides L-PN
It is an object of the present invention to provide a semiconductor device in which a PTr, a MIS capacitor, and a thin-film resistance element are mixedly mounted on a common substrate while maintaining good characteristics, and a method of manufacturing the same.

[0017]

According to the present invention, there is provided a semiconductor device comprising:
At least the contact formation surface side of the common semiconductor film forming the emitter extraction electrode and the collector extraction electrode of the L-PNPTr and the resistance layer of the thin-film resistance element is MIS.
The above object is achieved by adopting a configuration in which a SiOx-based interlayer insulating film is covered via a second-layer SiN film provided separately from the first-layer SiN film serving as a capacitance insulating film of a capacitor. Such a configuration is extremely effective when the upper-layer wiring contacted via the connection hole opened in the SiOx-based interlayer insulating film and the second-layer SiN film contains a Ti-based barrier metal. Further, in addition to the above-described configuration, a protective film made of the first-layer SiN film may be left on the surface of the lower SiOx-based interlayer insulating film. In addition, in addition to the above three elements, a V-NPN is further formed on the semiconductor substrate.
Tr may be mixed. V-NPNT in this case
The base extraction electrode for r can be formed using the semiconductor film.

In order to manufacture the semiconductor device of the present invention as described above, first, a SiOx-based 1
A capacitor window is opened in the first interlayer insulating film, the first SiN film is patterned, and a capacitor insulating film is deposited on the capacitor window, and then the first interlayer insulating film and a film formed thereon are formed. After patterning the semiconductor film, an emitter extraction electrode and a collector extraction electrode of L-PNPTr, a capacitor upper electrode of a MIS capacitor, and a resistance layer of a thin-film resistance element are simultaneously formed. The entire surface of the semiconductor film pattern is once covered with a second SiN film different from the first SiN film, and then the entire surface of the substrate is covered with a second SiOx-based interlayer insulating film. The first interlayer insulating film and the second SiN film are patterned to open at least a connection hole facing the semiconductor film pattern, and the connection hole is filled with an upper wiring.

Here, when forming the capacitive insulating film by patterning the first SiN film, this film is formed by L-PNPT.
The protective film may be left in the region where r is formed. In this case, when patterning the first interlayer insulating film,
The layered SiN film will be patterned together. Note that V-NPNTr may be further mounted on the semiconductor substrate. In this case, the base window of the V-NPNTr can be opened at the same time as the patterning of the first interlayer insulating film, and the base extraction electrode of the V-NPNTr can be formed using the semiconductor film.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a semiconductor film forming an extraction electrode of an L-PNP Tr and a resistance layer of a thin-film resistance element;
The function of the conventional protective film provided using the first-layer SiN film between the lower-layer first interlayer insulating film and the lower-layer first interlayer insulating film is basically changed to that of the semiconductor film and the second-layer interlayer insulating film thereover. Is replaced with a second-layer SiN film provided therebetween. The second SiN film is a first SiN film which is also used as a capacitance insulating film.
Unlike the N film, its thickness can be set independently of the device performance of the MIS capacitor. Therefore, the second layer S
As long as the iN film is formed to a sufficient thickness, it is possible to prevent the absorption of H atoms from the first interlayer insulating film or the n-type epitaxial layer by the Ti-based barrier metal, and thereby the base region of the L-PNPTr can be prevented. , The interface state density can be reduced, and the deterioration of the device performance can be prevented.

In the conventional semiconductor device, the contact forming surface side of the thin-film resistance element is in direct contact with the second-layer interlayer insulating film. In the present invention, this side is also covered with the second-layer SiN film. Therefore, the rate at which H atoms contained in the semiconductor layer pass through the second interlayer insulating film and are absorbed by the Ti-based barrier metal is reduced, and deterioration and fluctuation of the characteristics of the thin-film resistance element are prevented.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention is applied to V-NPNTr, L
-Regarding a semiconductor device in which four elements of PNP Tr, MIS capacitance, and polysilicon resistor are mixed and a manufacturing process thereof,
This will be described with reference to FIGS.

First, an example of the configuration of a semiconductor device according to the present invention is shown in FIG. This semiconductor device has V on a common Si substrate 1.
-NPNTr, L-PNPTr, MIS capacitance, and polysilicon resistor are mounted together. The capacitance insulating film 8M of the MIS capacitance and the protective film 8L left on the first interlayer insulating film 7 of the L-PNP Tr are derived from the common first SiN film, and the thickness thereof is MIS capacitance. Is selected in a sufficiently thin range of approximately 10 to 50 nm in order to sufficiently increase the capacity of the device. Also, the base extraction electrode 9VB of the V-NPNTr and the collector extraction electrode 9LC of the L-PNPTr
The emitter take-out electrode 9LE, the capacitor upper electrode 9M of the MIS capacitor, and the resistance layer 9R of the polysilicon resistor are formed using a common first-layer polysilicon film (1-polySi). This first polysilicon film has a thickness of about 100 to 300 nm and contains, for example, B (boron) as a p-type impurity in a dose of 5 × 10 ¹² to 2 × 10 ¹³ / cm ² .

The biggest feature of this semiconductor device is that
Each pattern derived from the second-layer polysilicon film is the second layer S
SiOx-based second interlayer insulating film 11 via iN film 10
In other words, the second-layer SiN film 10 always exists as a base of the second-layer interlayer insulating film 11. When an upper wiring is to be contacted with each pattern derived from the first polysilicon film, the second interlayer insulating film 11 and the second SiN film 10 are simultaneously patterned to open a contact hole. An electrode layer made of Al is applied to the inside through a Ti-based barrier metal.

Such a configuration improves the characteristics of the L-PNP Tr and the polysilicon resistance. First, L-PNPTr
Base region, that is, p ⁺ -type collector region 13C
A surface layer of the sandwiched n-type epitaxial layer 4 between the p ⁺ -type emitter region 13LE has been coated on the first layer interlayer insulating film 7 and the second layer interlayer insulating film 11, both these A protective film 8L made of a first-layer SiN film (1-SiN) and a second-layer SiN film 10 are interposed in an intermediate portion of the insulating film. These two SiN films are located between the base region of the L-PNP Tr and the Ti-based barrier metal 16 and function as barriers for diffusion of H atoms in the film. In addition, the film that substantially fulfills a more important function as a barrier is the second layer S
The protective film 8L, which is the iN film 10 and is the thinner film
Is not essential in the present invention. However, this protective film 8L
Irrespective of the presence or absence of the above, in the present invention, at least the excellent barrier effect shown by the second-layer SiN film 10 prevents H atoms in the film of the first-layer interlayer insulating film 7 from being absorbed by the Ti-based barrier metal 16, H atoms are efficiently used as terminal atoms of dangling bonds of Si atoms in the n-type epitaxial layer 4.

When the characteristics of the semiconductor device manufactured as described above were confirmed, the current amplification factor h _FE of the L-PNP Tr was changed to the L-PNP Tr formed without forming the second-layer SiN film 10. It has been improved about three times compared to the previous model.

On the other hand, in the case of the polysilicon resistor, the second layer S is formed on the resistance layer 9R made of the first layer polysilicon film.
The second interlayer insulating film 11 is stacked via the iN film 10, and the resistance layer 9R is not directly in contact with the second interlayer insulating film 11 as in the related art. Therefore, the resistance layer 9R
The portion where the H atoms in the film are absorbed into the Ti-based barrier metal 16 is limited to the vicinity of the contact portion, and the absorption amount is much smaller than in the conventional case. When the characteristics of the semiconductor device manufactured as described above were confirmed, the resistance value of the polysilicon resistor was extremely stable.
On the other hand, for comparison, a polysilicon resistor formed without forming the second-layer SiN film 10 has a resistance value of 1 due to absorption of H atoms by the Ti-based barrier metal 16.
It increased by about 0%, and the rate of increase was not constant.

Next, a method for manufacturing the above-described semiconductor device will be described. FIG. 1 shows a p-type Si in which various impurity diffusion layers and a field oxide film 5 (SiOx) are formed in advance.
The figure shows a state in which a first-layer SiOx-based interlayer insulating film 7 of SiOx is formed on the entire surface of the substrate 1, and this film is patterned in a region where a MIS capacitor is formed to form a capacitor window 7M.

The steps up to this point will be briefly described. First, an SiO ₂ film (not shown) having a thickness of about 300 nm is formed on the surface of a p-type <111> Si substrate 1 (p-Sub) by thermal oxidation. Then, this SiO ₂ film is formed by V-NPNTr and L-
An opening was formed in the PNP Tr formation region to form a gas phase diffusion mask. In this state, about 120 using Sb ₂ O ₃
By performing gas phase diffusion at 0 ° C. for 0.5 to 1 hour, antimony (Sb) is vapor-phase diffused into the substrate through the opening, and n ⁺ -type buried layers 2V, 2L (n ⁺ -BL)
Was formed. At this time, the sheet resistance ρs of the buried layers 2V and 2L is, for example, 20 to 50Ω / □, and the junction depth x _j is 1 to
It was 2 μm.

Next, the gas phase diffusion mask is removed to form a new resist mask (not shown), and a p ⁺ -type channel is formed in a region where a field oxide film 5 for element isolation is to be formed later. In order to form the stop 3, ion implantation of boron (B ⁺ ) was performed. At this time, the ion acceleration energy is 50 keV, and the dose is 4 × 10 ¹⁴ / cm.
^{And 2} .

Next, the resist mask was removed, and an n-type epitaxial layer 4 (n-Epi) was grown on the entire surface of the substrate. The resistivity of this n-type epitaxial layer 4 is 1.07
Ωcm, and the thickness was 1.08 μm.

Next, the field oxide film 5 was formed by selectively oxidizing the substrate by the LOCOS method. This LOCO
In the S method, first, a thickness of 30
A pad oxide film having a thickness of 65 nm and a SiN film having a thickness of 65 nm were laminated, and the laminated film was patterned to form a selective oxidation mask. Subsequently, in order to make the surface of the substrate after the selective oxidation substantially flat, n exposed in the opening of the selective oxidation mask is used.
The concave portion was formed by etching the type epitaxial layer 4. The depth of the recess was set to about half of the designed thickness of the field oxide film 5. In this state, pyrogenic oxidation is performed at 1000 to 1050 ° C. for 2 to 6 hours, and the thickness is 1 μm.
m of the field oxide film 5 was formed.

Next, S constituting the selective oxidation mask is described.
The iN film was removed using a hot phosphoric acid solution. Further, a resist (not shown) is provided on a part of the n-type epitaxial layer 4.
An n ⁺ -type diffusion layer was formed by ion-implanting phosphorus (P ⁺ ) through a mask. These diffusion layers are
V-NPNTr collector extraction area 6VC, L-PN
These are a base extraction region 6LB of the PTr and a lower capacitance region 6M of the MIS capacitance. The ion implantation conditions at this time were, for example, an ion acceleration energy of 50 keV and a dose of 6.15 × 10 ¹⁵ / cm ² . Further, the surface of the substrate was covered with a flattening SiOx film by CVD, and impurity activation annealing was performed in this state. Furthermore, this S
The iOx film was covered with a planarizing resist film, and the resist film and the oxide film were etched back at a constant speed to remove the bird's head and pad oxide film of the field oxide film 5.
At this stage, the surface of the base is flattened.

Next, a first interlayer insulating film 7 was formed on the entire surface of the substrate. The first interlayer insulating film 7 is a SiOx film having a thickness of about 85 nm deposited by CVD. In the first interlayer insulating film 7, a resist pattern is formed by ordinary photolithography and, for example, CHF ₃ / O ₂
RIE (Reactive Ion Etching) using mixed gas
After that, the capacity window 7M was formed. FIG. 1 shows a state in which the process up to this point has been completed.

Next, a first-layer SiN film (1-SiN) having a thickness of about 30 nm was formed on the entire surface of the substrate by, for example, thermal CVD. Next, the first SiN film is patterned through normal photolithography and dry etching,
As shown in FIG. 2, a capacitor insulating film 8M covering the capacitor window 7M, an L-PNP Tr
The protective film 8L was left in each of the formation regions. Note that the protective film 8L does not necessarily have to be formed.

Next, as shown in FIG. 3, the first interlayer insulating film 7 is patterned through ordinary photolithography and dry etching to form a base window 7 of the V-NPNTr.
The collector window 7LC and the emitter window 7LE of VB and L-PNPTr were opened. In the region where the L-PNP Tr is formed, the protective film 8L and the first interlayer insulating film 7 are etched at the same time, but these films can be etched using a common etching gas.

Next, a first-layer polysilicon film (1-pol) having a thickness of about 300 nm is formed on the entire surface of the substrate by, for example, CVD.
ySi) was deposited. Next, ion implantation for containing a p-type impurity in the first polysilicon film was performed.
This p-type impurity is used to form a graft base region of V-NPNTr (reference numeral 13VB in FIG. 6), and a collector region (reference numeral 13LC in FIG. 6) and an emitter region (reference numeral 13LE in FIG. 6) of L-PNPTr. Things. The above ion implantation is performed using, for example, BF ₂ ⁺ , an ion acceleration energy of 60 keV, and a dose of 3.5 × 10 ¹⁵ / cm ^2.
Was performed under the following conditions.

Thereafter, the first-layer polysilicon film is patterned, and as shown in FIG. 4, the base extraction electrodes 9VB, L covering the base window 7VB of the V-NPNTr.
A collector extraction electrode 9LE covering the collector window 7LC of the PNP Tr;
An emitter extraction electrode 9LE covering the LE, a capacitor upper electrode 9 laminated on the capacitor insulating film 8M of the MIS capacitor.
M, and a resistance layer 9R of polysilicon resistance disposed on the field oxide film 5 were formed, respectively.

Next, as shown in FIG.
An N film 10 (2-SiN) was formed on the entire surface of the substrate. This film forming step is a step which is a feature of the present invention. Here, the second-layer SiN film 10 having a thickness of about 30 nm is deposited by, for example, thermal CVD.

Next, as shown in FIG. 6, a SiOx film having a thickness of about 400 nm was formed on the entire surface of the substrate by CVD, and a second interlayer insulating film 11 was formed. Then, VN
In the region where the PNTr is formed, the second interlayer insulating film 1 is formed.
The first and second SiN films 10 and the base extraction electrode 9VB were collectively patterned to open an emitter window 11VE. Next, ions were implanted into the surface layer of the n-type epitaxial layer 4 to form the p ⁻ -type intrinsic base region 12 through the emitter window 11VE. B ⁺ was used for the ion implantation at this time, for example, under the conditions of an ion acceleration energy of 70 keV and a dose of 7.2 × 10 ¹³ / cm ² .

Next, an SiOx film (not shown) for forming a sidewall is formed on the entire surface of the base by 300 to 6 by CVD.
Deposited to a thickness of 00 nm. In this state, 900 ° C,
Annealing is performed for 30 minutes to activate the intrinsic base region 12, and also diffuse impurities into the substrate from the base extraction electrode 9VB, the collector extraction electrode 9LC, and the emitter extraction electrode 9LE, thereby forming a p ⁺ -type graft base region. 13VB, the collector region 13LC, and the emitter region 13LE were formed in a self-aligned manner. Next, the SiOx film was anisotropically etched back to form a sidewall 14 on the sidewall of the emitter window 11VE.

Next, as shown in FIG. 7, a second-layer polysilicon film 15 (2-polySi) having a thickness of about 150 nm is deposited on the entire surface of the substrate by CVD to introduce n-type emitter impurities. Was implanted. This ion implantation is performed using, for example, As ⁺ , under the conditions of an ion acceleration energy of 40 keV and a dose of 1 × 10 ¹⁶ / c.
It was m ^2. Next, the entire surface of the substrate was covered with a SiOx film (not shown) having a thickness of about 300 nm, and annealed at 950 ° C. for 10 minutes or at 950 to 1100 ° C. for several seconds to several tens of seconds. As a result, the intrinsic base region 1 is diffused by the diffusion of the n-type impurity from the second polysilicon film 15.
In FIG. 4, an n ⁺ -type emitter region 16 was formed in a self-aligned manner.

Thereafter, the SiOx film is removed by wet etching, the second polysilicon film 15 is patterned, and the emitter extraction electrode 15V as shown in FIG.
E was formed. Next, a second-layer interlayer insulating film 11 and a second-layer SiN film 10 on each of the extraction electrodes, and a second-layer interlayer insulating film 11 on an n ⁺ -type diffusion layer formed in the Si substrate 1. And the second-layer SiN film 10 and the first-layer interlayer insulating film 7 were simultaneously etched to form contact holes.

Further, an upper layer wiring was applied on the entire surface of the substrate by a sputtering method. This upper layer wiring
For example, a T film formed by laminating a Ti film and a TiN film in this order.
This is a multilayer film in which the i-based barrier metal 16 and the Al-1% Si film are stacked in this order. This multilayer film is patterned to form a base electrode 17VB of V-NPNTr, an emitter electrode 17VE, and a collector electrode 17VC, a collector electrode 17LC of L-PNPTr, an emitter electrode 17LE, and a base electrode 17LB, a capacitance connection electrode 17M of MIS capacitance, and polysilicon. The resistance connection electrodes 17R of the resistance were respectively formed. After that, the semiconductor device was completed through steps such as ordinary multilayer wiring and passivation.

Although the specific embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. For example, in the above embodiment, L-PNP Tr
Although the process for leaving the protective film 8L derived from the first-layer SiN film has been described above, the semiconductor device can be manufactured in exactly the same process even when the protective film 8L is not left. In addition, the conductivity types of the V-NPNPr and L-PNPTr are reversed, and V-PNPTr and LN
It may be a PNTr. In addition, the details of the design rules, the structure of the bipolar transistor, and the details of the process conditions such as film formation, etching, ion implantation, and annealing can be appropriately changed and selected.

[0046]

As is clear from the above description, according to the present invention, the lateral bipolar transistor and the thin-film resistance element can be highly reliable while increasing the MIS capacitance and the reliability of the upper wiring. Can be provided at the same time. Further, the method of the present invention for manufacturing such a semiconductor device comprises a patterning step of a semiconductor film for forming an extraction electrode of a lateral bipolar transistor and a resistance layer of a thin-film resistance element, and a step of coating the semiconductor film.
A second-layer SiN film formation step is added between the second-layer interlayer insulation film formation step and no new capital investment is required. That is, it is possible to manufacture a highly reliable semiconductor device with high compatibility with existing processes and without causing a significant increase in TAT (turn around time).

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a state in which a capacitor window is opened by patterning a first interlayer insulating film in a semiconductor device manufacturing process example to which the present invention is applied.

2 is a diagram showing a pattern of a first-layer SiN film that covers the entire surface of the substrate shown in FIG. 1;
FIG. 4 is a schematic cross-sectional view showing a state where a protective film in a PTr region is formed.

3 is a schematic cross-sectional view showing a state in which an electrode extraction window of a bipolar transistor is formed by patterning a first-layer interlayer insulating film of FIG. 2;

4 is a schematic cross-sectional view showing a state in which an extraction electrode, a capacitor upper electrode, and a resistive layer are formed by patterning a first-layer polysilicon film covering the entire surface of the substrate of FIG. 3;

FIG. 5 is a schematic cross-sectional view showing a state where the entire surface of the substrate of FIG. 4 is covered with a second-layer SiN film.

FIG. 6 is a schematic cross-sectional view showing a state in which a second interlayer insulating film covering the entire surface of the substrate of FIG. 5 is formed, an emitter window is opened, base ions are implanted, and impurities are diffused.

FIG. 7 shows the formation of a sidewall on the emitter window of FIG. 6;
FIG. 9 is a schematic cross-sectional view showing a state in which a layer polysilicon film has been formed, emitter / ion implantation and emitter diffusion have been performed.

FIG. 8 illustrates patterning of a second-layer polysilicon film of FIG. 7;
FIG. 4 is a schematic cross-sectional view showing a state in which a contact hole opening and an upper wiring are formed.

FIG. 9 shows an example of a conventional semiconductor device manufacturing process.
FIG. 4 is a schematic cross-sectional view showing a state in which a capacity window is opened by patterning a first interlayer insulating film and a capacity insulating film is formed by patterning a SiN film.

FIG. 10 shows a state in which an extraction electrode window of a bipolar transistor is opened in the first interlayer insulating film of FIG. 9 and an extraction electrode, a capacitor upper electrode, and a resistance layer are formed by patterning the first polysilicon film. It is a typical sectional view shown.

11 is a schematic cross-sectional view showing a state in which the entire surface of the substrate of FIG. 9 is covered with a second-layer interlayer insulating film, and a structure around the emitter of the V-NPNTr is formed.

FIG. 12 is a schematic cross-sectional view showing a state in which a contact hole opening and an upper wiring are formed.

FIG. 13 is a schematic cross-sectional view showing a state in which a SiN film forming a capacitance insulating film is left as a protective film also in an L-PNP Tr region in another process example of a conventional semiconductor device.

FIG. 14 shows a state in which an extraction electrode window of a bipolar transistor is opened in the first interlayer insulating film of FIG. 13 and an extraction electrode, a capacitor upper electrode, and a resistance layer are formed by patterning the first polysilicon film. It is a typical sectional view shown.

FIG. 15 is a schematic cross-sectional view showing a state in which the entire surface of the substrate shown in FIG. 14 is covered with a second-layer interlayer insulating film, and a structure around the emitter of the V-NPNTr, a contact hole opening, and an upper wiring are formed. FIG.

[Explanation of symbols]

Reference Signs List 1 ... Si substrate (p-Sub) 4 ... n-type epitaxial layer (n-Epi) 5 ... field oxide film 7 ... first interlayer insulating film 7M ... capacitance window 8M ... capacitive insulating film (1-S)
iL) 8L: Protective film (1-SiN) 9VB: Base extraction electrode 9LC: Collector extraction electrode 9LE: Emitter extraction electrode 9M: Capacitor upper electrode 9R: Resistive layer 10: Second layer SiN film 11: Second layer interlayer insulating film 16: Ti-based barrier metal 17LC: Collector electrode 17LE: Emitter electrode 17R: Resistance connection electrode

Claims (8)

[ Document name] Description [Claims] An MIS capacitor having a lateral bipolar transistor and a capacitor insulating film made of a first-layer SiN film;
A thin-film resistance element and a semiconductor device in which the thin-film resistance element is mounted on a common semiconductor substrate, wherein the lateral bipolar transistor has an emitter extraction electrode and a collector extraction electrode, and a common semiconductor film forming a resistance layer of the thin-film resistance element. A semiconductor device, wherein at least a contact forming surface side is covered with a SiOx-based interlayer insulating film via a second-layer SiN film. 2. The method according to claim 1, further comprising:
2. The method according to claim 1, wherein an upper layer wiring made of a laminated film of a Ti-based barrier metal and a conductive material film is contacted via a connection hole opened in the Ox-based interlayer insulating film and the second-layer SiN film. Semiconductor device. 3. The protective film according to claim 1, wherein the first-layer SiN film is also left as a protective film on the surface of the SiOx-based interlayer insulating film below the emitter extraction electrode and the collector extraction electrode. Semiconductor device. 4. The semiconductor device according to claim 3, wherein a vertical bipolar transistor is mounted on the semiconductor substrate, and a base extraction electrode is formed using the semiconductor film. 5. A lateral bipolar transistor, comprising:
A method of manufacturing a semiconductor device in which an S capacitor and a thin-film resistance element are mixedly mounted on a common semiconductor substrate, comprising: forming a first interlayer insulating film made of a SiOx-based material on the semiconductor substrate; A first step of patterning an interlayer insulating film to open a capacity window of the MIS capacitor; and forming a first-layer SiN film on the entire surface of the substrate,
A second step of patterning an N film to form a capacitive insulating film covering the capacitive window; and a third step of patterning the first interlayer insulating film to open an extraction electrode window of the lateral bipolar transistor. Forming a semiconductor film on the entire surface of the base, patterning the semiconductor film to cover the extraction electrode window, an emitter extraction electrode and a collector extraction electrode, a capacitor upper electrode of the MIS capacitor, and a resistance layer of the thin film resistance element. The fourth to form
And a step of sequentially covering the entire surface of the base with a second-layer SiN film and a second-layer interlayer insulating film made of a SiOx-based material, and patterning these films to form at least the emitter extraction electrode, the collector extraction electrode, and the capacitor upper part. A method for manufacturing a semiconductor device, comprising: a fifth step of opening a connection hole facing each of an electrode and a resistance layer of the thin-film resistance element; and a sixth step of forming an upper wiring to fill the connection hole. 6. The method for manufacturing a semiconductor device according to claim 5, wherein said upper wiring is formed using a laminated film formed by laminating a Ti-based barrier metal and a conductive material film in this order. 7. In the second step, the first-layer SiN film is left as a protective film in the formation region of the lateral bipolar transistor at the same time as the capacitive insulating film. In the third step, the first-layer SiN film is formed. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the extraction electrode window is opened by simultaneously patterning the first electrode and the first interlayer insulating film. 8. In the third step, a base window of the vertical bipolar transistor is simultaneously opened by patterning the first interlayer insulating film, and in the fourth step, the vertical bipolar transistor is patterned by patterning the semiconductor film. 6. The method according to claim 5, wherein a vertical bipolar transistor is mixedly mounted on the semiconductor substrate by simultaneously forming the base extraction electrodes.