JP3700298B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present inventionSemiconductor device and itsIt relates to a manufacturing method.
[0002]
[Prior art]
In the field of ASIC (application specific IC) and logic LSI, various elements such as bipolar transistors, MIS capacitors, and thin film resistors are generally mounted on a common semiconductor substrate.
A conventional typical manufacturing process of such a semiconductor device will be described with reference to FIGS. In these drawings, a single semiconductor substrate is described in two upper and lower stages for the sake of space, and a vertical NPN bipolar transistor (hereinafter referred to as V-NPNTr) and a horizontal PNP bipolar transistor are shown in the upper stage. A formation region of a transistor (hereinafter referred to as L-PNPTr) and a formation region of a MIS capacitor and a polysilicon resistor are shown in the lower stage, respectively. In the reference numerals used in the drawings, the alphabetic suffix V is V-NPNTr, the suffix L is L-PNPTr, the suffix M is a MIS capacitor, and the suffix R is a structure or member related to each element of the polysilicon resistor. Subscript B represents a base, subscript E represents an emitter, and subscript C represents a structure or member related to each region of the collector. These notations are the same in FIGS. 1 to 8 for explaining the embodiments described later.
[0003]
FIG. 9 shows a first interlayer insulating film 27 (SiOx) formed on a substrate in a manufacturing process of a semiconductor device in which V-NPNTr, L-PNPTr, MIS capacitance, and polysilicon resistance are mixedly mounted on the same substrate. A state is shown in which a capacitance window 27M for defining the formation site of the MIS capacitance is opened, and the capacitance insulating film 28M is formed by patterning the SiN film so as to cover the capacitance window 27M.
[0004]
The steps so far are outlined as follows. First, n-type impurities and p-type impurities are selectively introduced into the surface layer portion of the p-type Si substrate 21 (p-Sub) to embed the buried layers 22V and 22L (n⁺-BL) and the channel stop 23 are formed, and then an n-type epitaxial layer 24 (n-Epi) is formed on the entire surface of the substrate. After the field oxide film 25 is formed by a known LOCOS method, an n-type impurity is selectively introduced into a part of the element formation region, and a collector extraction region 26VC of V-NPNTr, a base extraction region 26LB of L-PNPTr, and A capacitor lower region 26M of the MIS capacitor is formed.
After performing the impurity activation annealing, an interlayer insulating film 27 made of an SiOx film is deposited on the entire surface of the substrate, and this film is patterned to form a capacitance window 27M. Further, a SiN film is deposited on the entire surface of the substrate, and this film is patterned to form a capacitive insulating film 28M that covers the capacitive window 27M.
[0005]
Next, as shown in FIG. 10, the first interlayer insulating film is patterned to open the extraction electrode window of the bipolar transistor. The extraction electrode windows are a base window 27VB of V-NPNTr, a collector window 27LC of L-PNPTr, and an emitter window 27LE of L-PNPTr.
Next, the entire surface of the substrate is covered with a first-layer polysilicon film (1-polySi), and p-type impurities are introduced into the film. This first polysilicon film is patterned so as to remain in the extraction electrode window, and the V-NPNTr base extraction electrode 29VB, the L-PNPTr collector extraction electrode 29LC, the emitter extraction electrode 29LE, and the upper portion of the MIS capacitance Electrode 29M and polysilicon resistance layer 29R are formed respectively.
[0006]
  Next, as shown in FIG. 11, a second interlayer insulating film 31 (SiOx) is deposited on the entire surface of the substrate, and an emitter window 31VE is opened in the V-NPNTr formation region to form an intrinsic base region. The p-type impurity ions are implanted. NextIn addition,A sidewall forming SiOx film is deposited on the entire surface, and impurity diffusion annealing is performed to form a V-NPNTr graft base region 33VB and intrinsic base region 32, and an L-PNPTr collector region 33LC and emitter region 33LE, respectively. Next, the sidewall forming SiOx film is anisotropically etched back to form a sidewall 34 on the inner wall surface of the emitter window 31VE. Subsequently, a second-layer polysilicon film (2-polySi) is deposited on the entire surface of the substrate, and n-type impurities are introduced into this film. An n-type impurity is diffused into the active region by annealing to form the emitter region 36 of V-NPNTr, and then the second-layer polysilicon film is patterned to form an emitter extraction electrode 35VE.
[0007]
Next, as shown in FIG. 12, the second-layer interlayer insulating film 31 or the first-layer interlayer insulating film 27 in addition to this is subjected to dry etching so that each extraction electrode or the extraction region in the substrate is exposed. Open a contact hole. Next, a laminated film of a Ti-based barrier metal 36 and an Al-based conductive film is formed on the entire surface of the substrate, and this laminated film is patterned to thereby obtain a base electrode 37VB, an emitter electrode 37VE, a collector electrode 37VC, L of V-NPNTr. -An emitter electrode 37LE, a collector electrode 37LC, a base electrode 37LB, a capacitor connection electrode 37M of a MIS capacitor, and a resistance connection electrode 37R of a polysilicon resistor are respectively formed. Finally, the entire surface of the substrate is covered with a passivation film (not shown) to complete the semiconductor device.
[0008]
[Problems to be solved by the invention]
However, in the semiconductor device manufactured as described above, the characteristic deterioration of L-PNPTr often becomes a problem.
In the L-PNPTr, since the surface layer portion of the n-type epitaxial layer 24 between the emitter region 33LE and the collector region 33LC surrounding the emitter region 33LE is used as a base active region, the crystallinity of this region greatly affects the device characteristics. Effect. In general, the higher the proportion of dangling bonds terminated in the Si crystal lattice in this region, the lower the interface state density, the lower the leakage current and noise, and the L-PNPTr capable of high-speed operation. Become.
[0009]
This terminal atom is normally a hydrogen (H) atom supplied from a SiOx-based interlayer insulating film. SiOx-based interlayer insulating films are often SiH_FourSince the film is formed by CVD using TEOS (tetraethoxysilane), H atoms, which are constituent atoms of these source gases, are considerably taken into the interlayer insulating film and diffused to auto-dope the n-type epitaxial layer. It is done. Therefore, if a sufficient amount of H atoms is supplied from the interlayer insulating film, the characteristics of the L-PNPTr are naturally well adjusted.
[0010]
By the way, in a semiconductor device manufactured based on a recent fine design rule, in order to prevent pn junction breakdown due to alloying reaction between Al-based wiring and a base extraction electrode or penetration of a diffusion layer, Ti-based barrier metal is used. The general structure of the Ti-based barrier metal is that a Ti film for achieving ohmic contact with a Si-based base material, and a laminated system of a TiN film and a TiW film that are superior in barrier properties as compared to the Ti film. Is done.
However, since Ti is a metal having an extremely high H storage capacity, the presence of the Ti-based barrier metal causes a shortage of H atoms to be supplied from the interlayer insulating film to the n-type epitaxial layer, thereby degrading the characteristics of L-PNPTr. The problem has arisen. In the future, from the viewpoint of improving the moisture resistance and dielectric constant of the interlayer insulating film, the residual H atoms in the film will be reduced, and the thickness of the interlayer insulating film itself tends to be thinned using a low dielectric constant material. Considering something, it gets more and more serious.
[0011]
In order to solve this problem, it has been proposed to form a protective film at the same time in the L-PNPTr formation region when the SiN film is patterned to form the capacitive insulating film 28M having the MIS capacitance. A manufacturing process example of the semiconductor device in this case will be described with reference to FIGS. The reference numerals used in these drawings are the same as those shown in FIGS.
[0012]
FIG. 13 shows a state in which a protective film 28L in the L-PNPTr region is added to the base shown in FIG. This protective film 28L is formed by patterning a SiN film common to the capacitive insulating film 28M.
The protective film 28L is patterned together with the first interlayer insulating film 27 in the opening of the extraction electrode window in the next step. FIG. 14 shows a state in which the collector extraction electrode 29LC and the emitter extraction electrode 29LE are attached to the collector window 27LC and the emitter window 27L formed by this patterning, respectively.
Thereafter, up to the formation of the upper layer wiring as shown in FIG. 15 is performed by the same process as described above.
[0013]
In the semiconductor device thus completed, as is apparent from FIG. 15, the protective film 28L made of the SiN film is also left on the surface of the first interlayer insulating film 27 in the formation region of the L-PNPTr. It has become. Therefore, if the protective film 28L is sufficiently thick, the diffusion path of H atoms from the first interlayer insulating film 27 to the Ti-based barrier metal 36 is blocked by the protective film 28L. The dangling bonds near the surface of the layer 24 are efficiently terminated by H atoms supplied from the first interlayer insulating film 27.
[0014]
However, since the protective film 28L is formed using a SiN film common to the capacitive insulating film 28M of the MIS capacitor, there is a problem that it is difficult to ensure a sufficiently large film thickness. That is, in recent semiconductor devices, as the degree of integration increases, the area occupied by each element is reduced, and it is required to secure a high capacity with a small area for the MIS capacity. In order to meet this requirement, it is effective to reduce the thickness of the capacitive insulating film 28M, but at this time, the protective film 28L is also naturally thinned. However, if the thickness is too thin, the protective film 28L cannot block the diffusion of H atoms at a certain critical thickness, and the characteristics of the L-PNPTr deteriorate rapidly. Therefore, if priority is given to securing the characteristics of the L-PNPTr, there arises a problem that the MIS capacity cannot be increased.
[0015]
Further, the absorption of H atoms by the Ti-based barrier metal 36 is not limited to the above-described interlayer insulating film, but also occurs from the semiconductor film. In the semiconductor device shown in FIGS. 12 and 15, the polysilicon resistance layer 29R and the second interlayer insulating film 31 are in direct contact with each other. The second interlayer insulating film 31 is made of a Ti-based barrier metal. 36 becomes a passage for sucking H atoms in the film from the resistance layer 29R, and as a result, the resistance value of the polysilicon resistance rises or fluctuates.
[0016]
As described above, in the structure and manufacturing method of the conventional semiconductor device, it is difficult to increase the reliability of the wiring or increase the capacity per unit area of the MIS capacity while preventing the characteristic variation of the L-PNPTr and the thin film resistance element. Met. Accordingly, the present invention solves these problems and provides a semiconductor device in which an L-PNPTr, a MIS capacitor, and a thin film resistance element are mixedly mounted on a common substrate while maintaining all characteristics, and a method for manufacturing the same. The purpose is to do.
[0017]
[Means for Solving the Problems]
  The semiconductor device of the present invention isA lateral bipolar transistor, a MIS capacitor having a capacitive insulating film made of a first-layer SiN film, and a thin film resistance element are mixedly mounted on a common semiconductor substrate, and an emitter extraction electrode and a collector extraction electrode of the lateral bipolar transistor; And an emitter extraction electrode and a collector of the lateral bipolar transistor in a semiconductor device in which a common semiconductor film constituting a resistance layer of the thin film resistance element is contacted with an upper layer wiring composed of a laminated film of a Ti-based barrier metal and a conductive material film At least the contact formation surface side of the common semiconductor film constituting the extraction electrode and the resistance layer of the thin film resistance element is covered with the SiOx-based interlayer insulating film via the second SiN filmBy taking the configuration, the above-mentioned purpose is achieved.That is,Such a configuration is extremely effective when a Ti-based barrier metal is included in the upper wiring contacted through the connection hole opened in the SiOx-based interlayer insulating film and the second-layer SiN film. In addition to the above-described configuration, a protective film made of the first SiN film may be left on the surface of the lower SiOx-based interlayer insulating film. In addition to the above three elements, a V-NPNTr may be further mixed on the semiconductor substrate. The base extraction electrode of V-NPNTr in this case can be formed using the semiconductor film.
[0018]
In order to manufacture the semiconductor device of the present invention as described above, first, a capacitor window is opened in the SiOx-based first interlayer insulating film formed on the semiconductor substrate, and the first SiN film is patterned. A capacitor insulating film is deposited on the capacitor window, and then the first and second interlayer insulating films and the semiconductor film formed thereon are patterned, respectively, so that the emitter and collector extracting electrodes of the L-PNPTr and the MIS capacitor The capacitor upper electrode and the resistance layer of the thin film resistance element are formed simultaneously. The entire surface of these semiconductor film patterns is once covered with a second SiN film different from the first SiN film, and then the entire surface of the substrate is covered with a SiOx-based second interlayer insulating film. The interlayer insulating film and the second SiN film are patterned to open at least a connection hole facing the semiconductor film pattern., Ti-based barrier metal and conductive material film are formed using a laminated film in this order.Embed with upper layer wiring.
[0019]
Here, when the capacitive insulating film is formed by patterning the first SiN film, this film may be left as a protective film also in the formation region of the L-PNPTr. In this case, when the first interlayer insulating film is patterned, the first SiN film is patterned together.
Note that V-NPNTr may be further mounted on the semiconductor substrate. In this case, the base window of the V-NPNTr can be opened simultaneously with the patterning of the first interlayer insulating film, and the base extraction electrode of the V-NPNTr can be formed using the semiconductor film.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
  The present inventionAn L-PNPTr (horizontal bipolar transistor), a MIS capacitor having a capacitive insulating film made of a first SiN film, and a thin film resistance element are mixedly mounted on a common semiconductor substrate, and an emitter extraction electrode of the L-PNPTr In a semiconductor device in which an upper wiring made of a laminated film of a Ti-based barrier metal and a conductive material film is contacted to a common semiconductor film constituting a collector extraction electrode and a resistance layer of the thin film resistor element, an emitter extraction of the L-PNPTr A structure in which at least the contact formation surface side of the common semiconductor film constituting the electrode, the collector extraction electrode, and the resistance layer of the thin film resistance element is covered with the SiOx interlayer insulating film through the second SiN film It is. That is,The conventional protective film provided using the first SiN film between the semiconductor film constituting the take-out electrode of the L-PNPTr and the resistance layer of the thin film resistor and the first interlayer insulating film therebelow. The function is basically replaced with a second-layer SiN film provided between the semiconductor film and the second-layer interlayer insulating film thereon. Unlike the first-layer SiN film that is also used as a capacitor insulating film, the thickness of the second-layer SiN film can be set regardless of the element performance of the MIS capacitor. Therefore, if even the second SiN film is formed to a sufficient thickness, it is possible to prevent H atoms from being sucked up from the first interlayer insulating film and the n-type epitaxial layer by the Ti-based barrier metal. -It is possible to reduce the interface state density in the base region of the PNPTr and prevent deterioration of device performance.
[0021]
In the conventional semiconductor device, the contact forming surface side of the thin film resistor element is in direct contact with the second interlayer insulating film. In the present invention, this side is also covered with the second SiN film. Therefore, the rate at which H atoms contained in the semiconductor layer are absorbed by the Ti-based barrier metal through the second interlayer insulating film is reduced, and deterioration and fluctuation of the characteristics of the thin film resistance element are also prevented.
[0022]
【Example】
Hereinafter, a semiconductor device in which four elements of V-NPNTr, L-PNPTr, MIS capacitor, and polysilicon resistor are applied by applying the present invention and a manufacturing process thereof will be described with reference to FIGS.
[0023]
First, FIG. 8 shows a structural example of a semiconductor device of the present invention.
In this semiconductor device, a V-NPNTr, an L-PNPTr, a MIS capacitor, and a polysilicon resistor are mixedly mounted on a common Si substrate 1. The capacitive insulating film 8M having the MIS capacity and the protective film 8L remaining on the first interlayer insulating film 7 of the L-PNPTr are derived from the common first-layer SiN film, and the thickness thereof is the MIS capacity. Is selected in a sufficiently thin range of approximately 10 to 50 nm in order to sufficiently increase the capacity. Also, the V-NPNTr base take-out electrode 9VB, the L-PNPTr collector take-out electrode 9LC and the emitter take-out electrode 9LE, the MIS capacitor upper electrode 9M, and the polysilicon resistance layer 9R are made of a common first layer polysilicon. It is formed using a film (1-polySi). The thickness of the first polysilicon film is about 100 to 300 nm, and B (boron), for example, 5 × 10 5 is used as a p-type impurity.¹²~ 2x10¹³/ Cm²Including the amount of dose.
[0024]
The greatest feature of this semiconductor device is that each pattern derived from the first-layer polysilicon film is covered with the SiOx-based second-layer interlayer insulating film 11 via the second-layer SiN film 10, in other words. For example, the second-layer SiN film 10 is always present as the base of the second-layer interlayer insulating film 11. When the upper-layer wiring is brought into contact with each pattern derived from the first-layer polysilicon film, the second-layer interlayer insulating film 11 and the second-layer SiN film 10 are simultaneously patterned to open contact holes. An electrode layer made of Al is deposited on the inside of the substrate through a Ti-based barrier metal.
[0025]
Such a configuration provides improved characteristics of the L-PNPTr and the polysilicon resistance.
First, the base region of L-PNPTr, that is, p⁺Type collector region 13C and p⁺The surface layer portion of the n-type epitaxial layer 4 sandwiched between the emitter region 13LE of the type is covered with the first interlayer insulating film 7 and the second interlayer insulating film 11. A protective film 8L made of a first SiN film (1-SiN) and a second SiN film 10 are interposed in the intermediate portion. These two SiN films are located between the base region of the L-PNPTr and the Ti-based barrier metal 16 and function as barriers for diffusion of H atoms in the film. Note that the film that substantially performs a more important function as a barrier is the second-layer SiN film 10, and the protective film 8L, which is the thinner film, is not essential in the present invention. However, regardless of the presence or absence of this protective film 8L, in the present invention, H atoms in the film of the first interlayer insulating film 7 are absorbed by the Ti-based barrier metal 16 by at least the excellent barrier effect exhibited by the second SiN film 10. Thus, the H atoms are efficiently used as the terminal atoms of the dangling bonds of the Si atoms of the n-type epitaxial layer 4.
[0026]
When the characteristics of the semiconductor device manufactured in this way were confirmed, the current amplification factor h of the L-PNPTr_FEHowever, it improved about 3 times compared with L-PNPTr formed without forming the second-layer SiN film 10.
[0027]
On the other hand, in the polysilicon resistance, a second-layer interlayer insulating film 11 is laminated on the resistance layer 9R made of the first-layer polysilicon film via the second-layer SiN film 10. The layer 9R is not in direct contact with the second interlayer insulating film 11. Therefore, the portion where H atoms in the film are sucked up from the resistance layer 9R to the Ti-based barrier metal 16 is limited to the very vicinity of the contact portion, and the amount of suction is much smaller than in the conventional case.
When the characteristics of the semiconductor device manufactured in this way were confirmed, the resistance value of the polysilicon resistor was extremely stable. On the other hand, for comparison, in the polysilicon resistor formed without forming the second-layer SiN film 10, the resistance value increases by about 10% due to the suction of H atoms by the Ti-based barrier metal 16. Moreover, the rate of increase was not constant.
[0028]
Next, a method for manufacturing the above-described semiconductor device will be described.
FIG. 1 shows the formation of a MIS capacitor by forming a SiOx-based first interlayer insulating film 7 on the entire surface of a p-type Si substrate 1 on which various impurity diffusion layers and field oxide films 5 (SiOx) are previously formed. This shows a state in which the film is patterned in a region to form a capacitance window 7M.
[0029]
The process up to here will be briefly described. First, a SiO-type film having a thickness of about 300 nm is formed on the surface of a p-type <111> Si substrate 1 (p-Sub).₂A film (not shown) is formed by thermal oxidation, and this SiO₂The film was opened in the formation region of V-NPNTr and L-PNPTr to form a gas phase diffusion mask. In this state, Sb₂O_ThreeIs used to diffuse the antimony (Sb) into the substrate through the opening by vapor phase diffusion at about 1200 ° C. for 0.5 to 1 hour, and n⁺Type buried layers 2V, 2L (n⁺-BL). At this time, the sheet resistance ρs of the buried layers 2V and 2L is, for example, 20 to 50Ω / □, and the junction depth x_jWas 1 to 2 μm.
[0030]
Next, the vapor phase diffusion mask is removed and a new resist mask (not shown) is formed, and p is formed in a region where a field oxide film 5 for element isolation is formed later.⁺In order to form the channel stop 3 of the mold, boron (B⁺) Ion implantation. At this time, the ion acceleration energy is 50 keV, and the dose amount is 4 × 10.¹⁴/ Cm²It was.
[0031]
Next, the resist mask was removed, and an n-type epitaxial layer 4 (n-Epi) was grown on the entire surface of the substrate. This n-type epitaxial layer 4 has a resistivity of 1.07 Ωcm and a thickness of 1.08 μm.
[0032]
Next, the substrate was selectively oxidized by the LOCOS method to form a field oxide film 5. In this LOCOS method, first, a pad oxide film having a thickness of 30 nm and a SiN film having a thickness of 65 nm were laminated on the entire surface of the substrate in accordance with a conventional method, and this laminated film was patterned to form a selective oxidation mask. Subsequently, in order to make the surface of the substrate after selective oxidation substantially flat, the n-type epitaxial layer 4 exposed in the opening of the selective oxidation mask was etched to form a recess. The depth of the recess is about half of the designed film thickness of the field oxide film 5. In this state, pyrogenic oxidation was performed at 1000 to 1050 ° C. for 2 to 6 hours to form a field oxide film 5 having a thickness of 1 μm.
[0033]
Next, the SiN film constituting the selective oxidation mask was removed using a hot phosphoric acid solution.
Further, phosphorus (P) is formed on a part of the n-type epitaxial layer 4 through a resist mask (not shown).⁺) To be ion-implanted.⁺A mold diffusion layer was formed. These diffusion layers are the V-NPNTr collector extraction region 6VC, the L-PNPTr base extraction region 6LB, and the MIS capacitance lower region 6M. The ion implantation conditions at this time are, for example, ion acceleration energy of 50 keV and a dose amount of 6.15 × 10.¹⁵/ Cm²It was.
Further, the surface of the substrate was covered with a flattening SiOx film by CVD, and impurity activation annealing was performed in this state. Further, the SiOx film was covered with a flattening resist film, and the resist film and the oxide film were etched at a constant speed to remove the bird's head and the pad oxide film of the field oxide film 5. At this stage, the surface of the substrate is flattened.
[0034]
Next, a first interlayer insulating film 7 was formed on the entire surface of the substrate. The first interlayer insulating film 7 is a SiOx film having a thickness of about 85 nm deposited by CVD. The first interlayer insulating film 7 is formed with a resist pattern formed by ordinary photolithography, for example, CHF._Three/ O₂A capacitance window 7M was formed through RIE (reactive ion etching) using a mixed gas. FIG. 1 shows a state in which the processes so far are finished.
[0035]
Next, a first SiN film (1-SiN) having a thickness of about 30 nm was formed on the entire surface of the substrate by, for example, thermal CVD. Next, this first layer SiN film is patterned through normal photolithography and dry etching, and as shown in FIG. 2, the capacitor insulating film 8M, L covering the capacitor window 7M is formed in the MIS capacitor formation region. -The protective film 8L was left in the formation region of PNPTr. Note that the protective film 8L is not necessarily formed.
[0036]
Next, as shown in FIG. 3, the first interlayer insulating film 7 is patterned through normal photolithography and dry etching, and a base window 7VB of V-NPNTr and a collector window 7LC and an emitter window of L-PNPTr 7LE was opened. In the formation region of the L-PNPTr, the protective film 8L and the first interlayer insulating film 7 are etched at the same time, but both films can be etched using a common etching gas.
[0037]
Next, a first layer polysilicon film (1-polySi) having a thickness of about 300 nm was formed on the entire surface of the substrate by, for example, CVD. Next, ion implantation was performed so that the first-layer polysilicon film contained p-type impurities. This p-type impurity forms a V-NPNTr graft base region (reference numeral 13VB in FIG. 6) and an L-PNPTr collector region (reference numeral 13LC in FIG. 6) and an emitter region (reference numeral 13LE in FIG. 6). Is. The ion implantation is performed by, for example, BF₂ ⁺Ion acceleration energy 60 keV, dose amount 3.5 × 10¹⁵/ Cm²It went on condition of.
[0038]
Thereafter, this first layer polysilicon film is patterned, and as shown in FIG. 4, a base extraction electrode 9VB covering the base window 7VB of the V-NPNTr and a collector extraction electrode covering the collector window 7LC of the L-PNPTr 9LE, an emitter take-out electrode 9LE covering the emitter window 7LE of the L-PNPTr, a capacitor upper electrode 9M stacked on the capacitor insulating film 8M of the MIS capacitor, and a polysilicon resistor disposed on the field oxide film 5 Each of the resistance layers 9R was formed.
[0039]
Next, as shown in FIG. 5, a second-layer SiN film 10 (2-SiN) was formed on the entire surface of the substrate. This film forming step is a step that characterizes the present invention. Here, a second SiN film 10 having a thickness of about 30 nm is deposited by, for example, thermal CVD.
[0040]
Next, as shown in FIG. 6, a SiOx film having a thickness of about 400 nm was formed on the entire surface of the substrate by CVD to form a second interlayer insulating film 11. Subsequently, in the V-NPNTr formation region, the second-layer interlayer insulating film 11, the second-layer SiN film 10, and the base extraction electrode 9VB were patterned at once, and the emitter window 11VE was opened. Next, p is applied to the surface layer portion of the n-type epitaxial layer 4 through the emitter window 11VE.^-Ion implantation was performed to form the intrinsic base region 12 of the mold. B for ion implantation at this time⁺For example, ion acceleration energy 70 keV, dose amount 7.2 × 10¹³/ Cm²It went on condition of.
[0041]
Next, a SiOx film (not shown) for forming a sidewall was deposited on the entire surface of the substrate to a thickness of 300 to 600 nm by CVD. In this state, annealing is performed at 900 ° C. for 30 minutes to activate the intrinsic base region 12, and impurities are diffused into the substrate also from the base extraction electrode 9VB, the collector extraction electrode 9LC, and the emitter extraction electrode 9LE.⁺A mold graft base region 13VB, a collector region 13LC, and an emitter region 13LE were formed in a self-aligned manner.
Next, the SiOx film was anisotropically etched back to form a side wall 14 on the side wall surface of the emitter window 11VE.
[0042]
Next, as shown in FIG. 7, a second-layer polysilicon film 15 (2-polySi) having a thickness of about 150 nm is deposited on the entire surface of the substrate by CVD, and ion implantation for introducing n-type emitter impurities is performed. Went. This ion implantation is performed, for example, by As⁺The conditions are ion acceleration energy 40 keV, dose amount 1 × 10¹⁶/ Cm²It was.
Next, the entire surface of the substrate was covered with a SiOx film (not shown) having a thickness of about 300 nm, and annealed at 950 ° C. for 10 minutes, or at 950 to 1100 ° C. for several seconds to several tens of seconds. As a result, n-type impurities are diffused from the second-layer polysilicon film 15 to form n in the intrinsic base region 14.⁺A mold emitter region 16 was formed in a self-aligned manner.
[0043]
Thereafter, the SiOx film was removed by wet etching, and the second-layer polysilicon film 15 was patterned to form an emitter extraction electrode 15VE as shown in FIG. Next, on each extraction electrode, the second interlayer insulating film 11, the second SiN film 10, and the n formed in the Si substrate 1 are formed.⁺On the mold diffusion layer, the second interlayer insulating film 11, the second SiN film 10 and the first interlayer insulating film 7 were etched together to open contact holes.
[0044]
Further, an upper layer wiring was deposited on the entire surface of the substrate by a sputtering method. The upper wiring is a multilayer film in which, for example, a Ti-based barrier metal 16 in which a Ti film and a TiN film are laminated in this order, and an Al-1% Si film are laminated in this order. The multilayer film is patterned to obtain a base electrode 17VB, an emitter electrode 17VE and a collector electrode 17VC for V-NPNTr, a collector electrode 17LC, an emitter electrode 17LE and a base electrode 17LB for L-PNPTr, a capacitor connection electrode 17M for MIS capacitance, and polysilicon. Resistor connection electrodes 17R for resistance were formed.
Thereafter, the semiconductor device was completed through processes such as normal multilayer wiring and passivation.
[0045]
As mentioned above, although the specific Example of this invention was described, this invention is not limited to the above-mentioned Example at all.
For example, in the above-described embodiment, the process of leaving the protective film 8L derived from the first-layer SiN film on the L-PNPTr has been described. However, even when this protective film 8L is not left, the semiconductor device is manufactured by exactly the same process. be able to. The conductivity types of the V-NPNTr and L-PNPTr may be reversed to V-PNPTr and L-NPNTr, respectively. In addition, details such as design rules, details of the bipolar transistor structure, and process conditions such as film formation, etching, ion implantation, and annealing can be changed or selected as appropriate.
[0046]
【The invention's effect】
As is clear from the above description, according to the present invention, the high reliability of the lateral bipolar transistor and the thin film resistance element was simultaneously achieved while increasing the capacity of the MIS capacitor and the high reliability of the upper layer wiring. A semiconductor device can be provided. In addition, the method of the present invention for manufacturing such a semiconductor device includes a patterning step of a semiconductor film for forming a take-out electrode of a lateral bipolar transistor and a resistance layer of a thin film resistance element, and a second layer covering the same. A second layer SiN film forming step is added between the insulating film forming step and no new equipment investment is required. In other words, it is possible to manufacture a highly reliable semiconductor device that has high consistency with existing processes and does not cause a significant increase in TAT (turn around time).
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing a state in which a capacitor window is opened by patterning a first interlayer insulating film in an example of a semiconductor device manufacturing process to which the present invention is applied.
2 is a schematic cross-sectional view showing a state in which a capacitive insulating film of MIS capacitance and a protective film in an L-PNPTr region are formed by patterning a first SiN film covering the entire surface of the substrate of FIG.
3 is a schematic cross-sectional view showing a state in which an electrode extraction window of a bipolar transistor is formed by patterning a first interlayer insulating film in FIG.
4 is a schematic cross-sectional view showing a state in which an extraction electrode, a capacitor upper electrode, and a resistance layer are formed by patterning a first-layer polysilicon film covering the entire surface of the substrate of FIG.
5 is a schematic cross-sectional view showing a state in which the entire surface of the substrate of FIG. 4 is covered with a second-layer SiN film.
6 is a schematic cross-sectional view showing a state in which a second-layer interlayer insulating film covering the entire surface of the substrate of FIG. 5 is formed, emitter window opening, base ion implantation, and impurity diffusion are performed. FIG.
7 is a schematic cross-sectional view showing a state in which sidewall formation on the emitter window of FIG. 6 is performed, formation of a second-layer polysilicon film, emitter-ion implantation, and emitter diffusion are performed. FIG.
8 is a schematic cross-sectional view showing a state in which the second-layer polysilicon film in FIG. 7 is patterned, contact hole openings, and upper-layer wiring are formed.
FIG. 9 is a schematic cross-sectional view showing a state where a capacitor window is opened by patterning a first interlayer insulating film and a capacitor insulating film is formed by patterning a SiN film in a conventional semiconductor device manufacturing process example;
10 shows a state in which an extraction electrode window of a bipolar transistor is opened in the first interlayer insulating film of FIG. 9, and an extraction electrode, a capacitor upper electrode, and a resistance layer are formed by patterning the first polysilicon film. It is a typical sectional view shown.
11 is a schematic cross-sectional view showing a state in which the entire structure of the base body of FIG. 9 is covered with a second interlayer insulating film, and the structure around the emitter portion of V-NPNTr is formed.
FIG. 12 is a schematic cross-sectional view showing a state in which contact hole openings and upper layer wiring are formed.
FIG. 13 is a schematic cross-sectional view showing a state in which the SiN film constituting the capacitive insulating film is left as a protective film also in the L-PNPTr region in another process example of the conventional semiconductor device.
14 shows a state in which an extraction electrode window of a bipolar transistor is opened in the first interlayer insulating film of FIG. 13, and an extraction electrode, a capacitor upper electrode, and a resistance layer are formed by patterning the first polysilicon film. It is a typical sectional view shown.
15 is a schematic cross-sectional view showing a state in which the entire surface of the substrate in FIG. 14 is covered with a second interlayer insulating film, the structure around the emitter of V-NPNTr, the contact hole opening, and the upper layer wiring are formed. FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Si substrate (p-Sub) 4 ... N-type epitaxial layer (n-Epi) 5 ... Field oxide film 7 ... First layer interlayer insulating film 7M ... Capacitance window 8M ... Capacitor insulating film (1-SiN) 8L ... Protection Membrane (1-SiN) 9VB ... Base extraction electrode 9LC ... Collector extraction electrode 9LE ... Emitter extraction electrode 9M ... Capacitor upper electrode
9R ... resistance layer 10 ... second layer SiN film 11 ... second layer interlayer insulation film 16 ... Ti-based barrier metal 17LC ... collector electrode 17LE ... emitter electrode 17R ... resistance connection electrode

Claims (6)

A lateral bipolar transistor, a MIS capacitor having a capacitive insulating film made of a first-layer SiN film, and a thin film resistance element are mixedly mounted on a common semiconductor substrate, and an emitter extraction electrode and a collector extraction electrode of the lateral bipolar transistor; and a common semiconductor film constituting the resistive layer of the thin film resistance elements, Te semiconductor device odor upper wiring of the layer film of Ti-based barrier metal and the conductive material film is contact,
At least the contact formation surface side of the common semiconductor film constituting the emitter extraction electrode and the collector extraction electrode of the lateral bipolar transistor and the resistance layer of the thin film resistor element is a SiOx-based interlayer insulating film through a second SiN film A semiconductor device, characterized in that it is coated with. The semiconductor device according to claim 1, wherein the lower layer the first layer SiN film on the surface of the SiOx-based interlayer insulating film of the emitter extraction electrode and the collector take-out electrode is formed by the residual as a protective film. 3. The semiconductor device according to claim 1, wherein a vertical bipolar transistor is mixedly mounted on the semiconductor substrate, and a base extraction electrode is formed using the semiconductor film . A method of manufacturing a semiconductor device in which a lateral bipolar transistor, an MIS capacitor, and a thin film resistor element are mixedly mounted on a common semiconductor substrate,
  Forming a first interlayer insulating film made of a SiOx-based material on the semiconductor substrate, patterning the first interlayer insulating film to open a capacity window of the MIS capacitor, and an entire surface of the substrate; A second step of forming a first SiN film and patterning the first SiN film to form a capacitive insulating film covering the capacitive window; and patterning the first interlayer insulating film to form the lateral type A third step of opening the extraction electrode window of the bipolar transistor; forming a semiconductor film on the entire surface of the substrate; and patterning the semiconductor film to cover the extraction electrode window, the collector extraction electrode, the collector extraction electrode, and the MIS capacitor A fourth step of forming a capacitor upper electrode and a resistance layer of the thin film resistance element, and covering the entire surface of the substrate with a second-layer SiN film and a second-layer interlayer insulating film made of a SiOx-based material sequentially, A fifth step of patterning these films to open connection holes respectively facing at least the emitter extraction electrode, the collector extraction electrode, the capacitor upper electrode, and the resistance layer of the thin film resistance element, and an upper layer for embedding the connection hole A sixth method of manufacturing a semiconductor device, comprising: forming a wiring using a laminated film in which a Ti-based barrier metal and a conductive material film are laminated in this order. In the second step, the first SiN film is left as a protective film in the formation region of the lateral bipolar transistor simultaneously with the capacitive insulating film, and in the third step, the first SiN film and the first layer interlayer are left. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the extraction electrode window is opened by simultaneously patterning the insulating film . In the third step, the base window of the vertical bipolar transistor is simultaneously opened by patterning the first interlayer insulating film, and in the fourth step, the base extraction electrode of the vertical bipolar transistor is formed by patterning the semiconductor film. 6. The method of manufacturing a semiconductor device according to claim 4 , wherein a vertical bipolar transistor is mixedly mounted on the semiconductor substrate by forming the semiconductor substrate simultaneously .

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