JP2000252365A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a change in the characteristic of a polysilicon resistance and to increase the capacitance value of a MIS capacitance when the MIS capacitance and the polysilicon resistance are provided. SOLUTION: A dielectric film as a first-layer Si3N4 film 18, a polysilicon film 19 as a first-layer conductive film, a dielectric film as a second Si3N4 film 21 and a second-layer conductive film are formed to be of a laminated structure. A MIS capacitor 1 is formed on a P-type semiconductor substrate 11. An interlayer film on the upper layer of a polysilicon resistance (poly-R) 2 is constituted of the second-layer Si3N4 film 21. The dielectric films are formed as many layers, and a part of the dielectric films is used for an interlayer insulating film. As a result, a capacitance value is increased, and it is possible to prevent the resistance or the like of the polysilicon resistance from being changed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device of a bipolar transistor and a method of manufacturing the same, and more particularly to a semiconductor device of a
The present invention relates to an element structure of an S capacitor and a method of manufacturing a semiconductor device in which this capacitor and a Poly-Si resistor are mixed.

[0002]

2. Description of the Related Art A bipolar transistor and other elements such as a resistor and a capacitor are simultaneously formed in an integrated circuit, and these passive elements are combined with the transistor to realize various functions. Next, NPN (bipolar)
Transistor (also referred to as NPNTr), Poly-
Si resistance (Poly-R or polysilicon resistance) and M
A method for manufacturing a semiconductor device including an element such as an IS capacitor (MIS-C) will be described.

FIGS. 6 to 10 show a conventional NPN Tr (N
PN transistor) 101, L-PNPTr (L-PN
P transistor) 102, MIS-C (Metal Insulat)
ingSemiconductor-Capacitor) 103 or Poly-R
(Also referred to as a polysilicon resistor or a Poly-Si resistor) 104 illustrates a method of manufacturing a semiconductor device in which the semiconductor devices are simultaneously configured.

As shown in FIGS. 6A and 6B, P
For example, an N-type collector buried region (N-BL) is formed in a region composed of an NPN transistor or an L-PNP transistor on a type semiconductor substrate (also referred to as P-sub) 111.
Form 112. Thereafter, the N-epi layer 113 is formed on the entire surface.
Is grown, and a field oxide film (Field Ox film, LOC) is formed between each element and in a region where the Poly-R 104 is formed.
OS) 114, and P reaching P-sub 111
⁺ N ⁺ reaching element isolation layer 115 and N-BL 112
The sinkers 116 are respectively formed. Here, when the P ⁺ element isolation layer 115 is formed, a diffusion resistance region of the Poly-R 104 is also formed at the same time. Thus, the N-epi layer 113 is surrounded by the P ⁺ element isolation layer 115 and the P-sub 111
And insulate the lower part of the Poly-R 104,
The respective regions of the NPN Tr 101, the L-PNP Tr 102, the MIS capacitor (MIS-C) 103, and the Poly-R 104 are formed.

An insulating film 117 of SiO ₂ or the like is formed on the surface of the N-epi layer 113 by a CVD method or the like, and is patterned for forming an MIS capacitor (103) region. The insulating film 117 is formed by RIE (Reactive Ion Etching). ), The insulating film (Si ₃ ) of the MIS capacitor 103 is removed.
The N _4, etc.) 118 is formed by CVD. Next, FIG.
As shown in FIG. 7C and FIG. 7D, the insulating film 118 for the MIS capacitor is processed using RIE or WET etching, and is removed while leaving only the region of the MIS capacitor 103. Subsequently, an insulating film 117 such as SiO ₂ is processed by patterning to form an active region of the NPN Tr and an emitter and a collector region of the L-PNP Tr.

[0008] Next, as shown in FIGS. 8E and 8F, a Poly-Si film 119 is deposited on the entire surface.
The ly-Si film 119 is ion-implanted to form an external base region (graft base region) 123 for reducing the base resistance, and then processed using a base extraction electrode pattern. At the time of this ion implantation, Poly-R1
04 resistance value can also be set. Where LP
The emitter, collector, and MIS capacitance (1
An upper electrode for Poly-R104 is formed in the same step.

Then, an insulating film 120 is formed on the Poly-Si film (119) by a CVD method or the like, and the NPN Tr1 is formed.
01 for the formation of the emitter region,
Insulating film 120 and Poly-Si film 119 below insulating film
Are processed by RIE. Thereafter, ion implantation for forming a base region is performed, and a Poly-Si film 119 for extracting a base electrode and an emitter Poly-Si film 1 are drawn.
An insulating film 120 for separating and forming the side wall (125) is deposited by using the CVD method.

[0008] Density of CVD film, diffusion layer of graft base region 123 and base region (intrinsic base region)
Heat treatment is performed to form 124, and then the insulating film 120 is etched back to form a sidewall 125. The graft base region 123 is formed simultaneously with the emitter 123b of the L-PNP Tr 102 and the impurity regions of the collectors 123a and 123c, and the same process is used.

Next, as shown in FIGS. 9 (g) and 9 (h), Poly-S for forming an emitter of the NPN Tr 101 is formed.
An i film 126 is deposited by the CVD method, and then ions are implanted into the Poly-Si film 126 to form a diffusion layer (emitter diffusion layer) 127 in the emitter region. Furthermore, P
A cap layer formed of SiO ₂ or the like is deposited on the poly-Si film 126 (not shown), and heat treatment is performed to activate impurity ions, and impurities contained in the poly-Si film 126 are removed from the base of the semiconductor surface. Diffused into the area 124,
An emitter diffusion layer 127 is formed. After that, the cap layer is removed by wet etching or the like.

[0010] As shown in FIGS. 10I and 10J, the NPN Tr 101 is formed on the Poly-Si film (126).
A pattern for forming the emitter electrode (126a) is formed by a lithography process, and the poly-Si film 12 is formed.
6 is processed by RIE. Next, the base electrode 130, the collector electrode 132, and the L-PNPT of the NPN Tr 101
r102 emitter electrode 133, base electrode 135, collector electrode 134, MIS capacitor 103, Poly-R1
A pattern for taking out each electrode of 04 is formed by a lithography process, and after processing, a metal wiring such as Al or titanium Ti or a metal wiring obtained by laminating them is formed.
Thereafter, a passivation film is deposited on the upper portion.

However, in the above-described semiconductor device, a barrier metal is used due to the problem of the reliability of the Al wiring. However, when a Ti-based barrier metal is used, the reaction between Ti and hydrogen causes the Al to fall on the Poly-Si resistor. When there is a wiring, there is a problem that Ti is absorbed from the Poly-Si film and the characteristics vary depending on the presence or absence of the Al wiring. Also, MI
The capacitance value of the S capacitor is determined by the area of the opening of the MIS capacitor and Si ₃ N ₄
It is determined by the film thickness, and to increase the capacitance value, it is necessary to increase the area or reduce the thickness of the Si ₃ N ₄ film.
Caused a problem that when increasing the area of the MIS capacitor IC chip area becomes large as a result the manufacturing cost becomes high, the Si ₃ N ₄ film and deterioration of the reliability of the Si ₃ N ₄ film when thinned, for example, a high electric field to This causes problems such as easy dielectric breakdown or increased leak current, making it difficult to increase the capacity.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has been made in consideration of the above problems.
The present invention relates to a semiconductor device having an IS capacity and a Poly-Si resistance and a method of manufacturing the same, and particularly to a Poly-Si resistance (Po
It is an object of the present invention to provide a high-performance, highly-integrated, highly-reliable semiconductor device and a method of manufacturing the same, which realize a high MIS capacitance while preventing fluctuations in the characteristics of (ly-R).

[0013]

According to a first aspect of the present invention, there is provided a first conductive type first impurity region formed in a semiconductor substrate;
A first insulating film formed on the first impurity region of the first conductivity type, a first conductive film formed on the first insulating film, and a first conductive film formed on the first conductive film; A second insulating film;
A first electrode formed on the first insulating film, a second electrode opened in the second insulating film and connected to the first conductive film, and connected to the first impurity region of the first conductivity type. And a third electrode provided.

According to a second aspect of the present invention, there is provided a first insulating film for element isolation formed in a semiconductor substrate, a second insulating film formed on the first insulating film for element isolation, and a second insulating film. A first conductive film formed on the film and a second conductive film formed on the first conductive film;
And a plurality of electrodes connected to the first conductive film by opening the second insulating film.

According to a third aspect of the present invention, in a method of manufacturing a semiconductor device, a step of forming a first conductive type semiconductor layer on a semiconductor substrate, and a step of selectively separating elements in the first conductive type semiconductor layer. A step of forming an insulating film, a step of introducing a first impurity into a semiconductor layer of the first conductivity type to form a first impurity region, and a step of depositing a first insulating film over the entire surface; Forming a second insulating film after opening the first insulating film on the impurity region, depositing polysilicon over the entire surface, processing the polysilicon into a predetermined shape, and then depositing a third insulating film; A step of depositing a fourth insulating film after the opening of the third insulating film, further forming a conductive film, a step of processing the conductive film to form a first electrode; Open the insulating film of
And forming a third electrode by opening the first, third and fourth insulating films.

According to a fourth aspect of the present invention, in a method of manufacturing a semiconductor device, a step of forming a semiconductor layer of a first conductivity type on a semiconductor substrate and a step of selectively separating an element in the semiconductor layer of the first conductivity type are performed. A step of forming an insulating film, a step of introducing a first impurity into a semiconductor layer of the first conductivity type to form a first impurity region, and a step of depositing a first insulating film over the entire surface; After opening the first insulating film on the impurity region, a second insulating film is formed in the opened region.
A step of depositing polysilicon over the entire surface, processing the polysilicon film into a predetermined shape of a capacitance region and a resistance region, and depositing a third insulating film; A step of depositing a fourth insulating film after opening the insulating film and processing it into a predetermined pattern to form a conductive film, a step of processing the conductive film to form a first electrode, a step of forming a third electrode, Forming a second electrode of a capacitor and a third electrode of a resistor by opening the fourth insulating film; and forming a fourth electrode of the capacitor by opening the first, third, and fourth insulating films. Forming a semiconductor device.

According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a bipolar transistor, a polysilicon resistor and a MIS capacitance, wherein an SiOx-based material insulating film is formed on a semiconductor substrate, and the insulating film is patterned to form a MIS capacitor. A first step of opening a first connection hole for forming
A second step of forming an Si ₃ N ₄ film of a first dielectric film for filling the first connection hole and patterning the Si ₃ N ₄ film, and a third step of opening a base extraction electrode window of the bipolar transistor And a fourth step of forming a first conductive film on the entire surface and patterning the first conductive film to form a base extraction electrode for covering the base extraction electrode window, and an electrode region for polysilicon resistance and MIS capacitance. And SiOx
A fifth step of depositing a first interlayer insulating film of a base material and patterning the first interlayer insulating film to open a second connection hole for forming a MIS capacitor; The second dielectric film for filling the holes and the SiOx-based material 2
A sixth step in which a second interlayer insulating film is covered and a second interlayer insulating film is patterned to form a region for extracting an upper electrode of the MIS capacitor; and a second conductive film is deposited and patterned to form a bipolar transistor. A seventh step of forming an emitter extraction electrode of the transistor and an upper electrode region of the MIS capacitor;
An eighth step of patterning the first interlayer insulating film, the second dielectric film, and the second interlayer insulating film to open connection holes respectively connected to the base extraction electrode, the polysilicon resistor, and the MIS capacitor; A ninth step of forming an upper layer wiring for filling the hole.

Therefore, in the semiconductor device and the method of manufacturing the same according to the present invention, the first-layer SiOx-based insulating film / Si ₃ N ₄ film / the second-layer SiOx-based insulating film is used as an interlayer film between the Poly-Si resistor and the Al wiring. By stacking with Po
Variations in the characteristics of the ly-Si resistance can be prevented. That is, MIS
By providing the Si ₃ N ₄ film used as the dielectric film of the capacitor on the upper portion of the Poly-Si resistor, absorption of hydrogen by the Ti-based barrier metal is prevented, thereby contributing to stabilization of characteristics. Further, the semiconductor substrate including the Si ₃ N ₄ film / first layer Si ₃ N ₄
By forming a MIS capacitor having a laminated structure of film / first conductive film / second Si ₃ N ₄ film / second conductive film, a MIS capacitor having a high capacitance value can be realized.

[0019]

Embodiments of the present invention will be described below with reference to the drawings.

Embodiment 1 FIG. 1 shows an NPN Tr (NPN transistor or NPN transistor).
(Bipolar) transistor) 3, MIS-C (MIS
A semiconductor device including a capacitor 1 and a Poly-R (Poly-Si resistor, polysilicon resistor) (2) and the like will be described. MIS-C1, Poly-R in order from the left side of FIG.
2 and NPNTr3 are arranged.

In the NPN Tr 3, an N-type high-concentration collector buried region (N-BL; N-Buried Layer) 12 is formed in a P-type semiconductor substrate (P-sub) 11, and an ISO called a channel stopper is formed around its periphery.
Reference numeral 15 denotes a structure in which P-type impurities are diffused in a high concentration in the vertical direction. Isolation region (field oxide film of the insulating film formed of SiO ₂ film or the like on the upper portion of the iso15, LO
COS (Local Oxidation of Silicon) 14 is configured. Regarding the other elements MIS-C1 and Poly-R2, a LOCOS 14 is also formed above the ISO 15, and both elements are physically or electrically separated from each other similarly to the NPN Tr 3 using both the LOCOS 14 and the ISO 15. Here, the P-type semiconductor substrate (or also referred to as a P-type semiconductor substrate) 11 is not necessarily required to be planar, and may be, for example, spherical.

The above LOCOS 14 is a Poly-R2
In this case, the poly-R2 is formed over the entire lower surface of the polysilicon film. In addition, an N-type epitaxial layer (or N-epi layer) 13 formed by epitaxial growth on the N-type high-concentration collector buried region 12 is formed in the region where the NPN Tr 3 is formed.

In the N-type epitaxial layer 13, M
In the IS-C1, N-type impurities are diffused and PLG
An (N ⁺ sinker) 16 is formed, embedded in the LOCOS 14 in the Poly-R2, an intrinsic base region 24 in the NPNTr3, and a graft base 23 at both ends thereof. An N ⁺ sinker (PLG) 16 in the extraction region is configured to be connected to the collector buried region 12.

Next, an insulating film 17 is deposited to separate the electrodes between the devices, and the insulating film 17 is opened to form an electrode window for each device. Specifically, MIS-C
A lower electrode window immediately below the capacitor 1, a lower electrode extraction electrode window formed beside this, and a base electrode and collector electrode window of the NPN Tr3 are formed.

The patterned for MIS-C1 first Si ₃ N4 film 18 was deposited under the MIS-C as a first insulation film lower electrode window in the opening region of (1), the S
Poly-R (2) polysilicon film 19 on the i ₃ N4 film 18 and Si processed for the second MIS-C (1)
A _second Si ₃ N 4 film 21 is sequentially deposited and processed on the O ₂ film,
A polysilicon film 26 as a first upper electrode film is deposited, and a metal electrode such as Al is formed on the polysilicon film 26. Similarly, a lower electrode 33 made of Al or the like is formed in a window for taking out from the base electrode formed of the N ⁺ sinker 16. Furthermore, the first and second Si ₃ as the second upper electrode
A window of the upper electrode 31 is opened between the N4 films 18 and 21 so as to be connected to the polysilicon film 19 for Poly-R (2), and Al or the like is deposited and processed to form the upper electrode 31.

On the other hand, in the Poly-R2, the polysilicon film 19 is processed into a predetermined shape and size in accordance with the resistance value, an interlayer insulating film of SiO ₂ is deposited on the polysilicon film 19, and the second Si ₃ An N4 film 21 is formed. Also, SiO ₂ is formed on the second Si ₃ N 4 film 21 and an electrode window is opened, and electrodes 34 and 3 of Al or the like are formed there.
5 have been deposited. Here, the second Si ₃ N 4 film 21 on the Poly-R2 polysilicon film 19 prevents the Ti-based barrier metal from absorbing hydrogen.

Next, in the NPN Tr 3, a polysilicon film 19 is formed on the graft base region 23, and a base electrode 36 whose end is connected is formed. Further, a polysilicon film 26 is connected to the emitter region 27 at the center of the intrinsic base region 24 with the side wall 25 interposed therebetween, and a metal film such as Al is deposited thereon to form an emitter electrode 37. The graft base region 23, which is a high-concentration P-type impurity region formed around the intrinsic base region 24, is configured to overlap with the intrinsic base region 24, thereby reducing the base resistance. .

Further, at the end of the collector buried region 12, a collector electrode 38 connected to the N ⁺ sinker 16 for taking out the collector electrode is formed. The N ⁺ sinker 16 is formed between the collector buried region 12 and the collector electrode (3
8) to reduce the collector resistance.

As described above, the MIS-C1 is constituted by using two upper electrodes 31 and 32, and is constituted by one lower electrode 33. For example, the upper electrode 31 is used as one terminal, and the upper electrode 31 is used as one terminal. By connecting the electrode 32 and the lower electrode 33 in common to form the other terminal, a capacitor in which two capacitors are connected in parallel can be formed, and a capacitor having a large capacitance value can be obtained.

The second insulating film (dielectric film) of the capacitor located on the upper portion used for the capacitor having the MIS-C (1) structure
_{Since the} 3N4 film 21 is formed above the Poly-R2, the absorption of hydrogen by the Ti-based barrier metal is prevented, and the fluctuation of the resistance characteristics is reduced. Thus, the MIS
The second Si ₃ N 4 film 21 of the insulating film formed on the upper part of the insulating film (dielectric film) used for −C1 is formed of Poly-R2
Provided at the upper part of the poly-R2,
And the process steps need not be added exclusively to the Poly-R (2), so that the number of steps does not needlessly increase.

Second Embodiment Next, FIGS. 2 to 5 show MIS-C (MIS capacity) 4
8, Poly-R (Poly-Si resistor) 49 and NPN
A method for manufacturing a semiconductor device having a Tr (NPN (bipolar) transistor) 50 will be described. As shown in FIG. 2A, a 330 nm-thick SiO ₂ film (not shown) is formed on a P-type semiconductor substrate (P-sub) 51 by a thermal oxidation method or the like. Using a resist pattern (not shown) formed by lithography as a mask, the SiO ₂ film is etched and removed, and the MIS-C48 and Poly-R49 are removed.
And an element region such as an NPN transistor (50) is opened. After that, the resist is removed. Here, the P-type semiconductor substrate (P-type semiconductor base) 51 may be of a planar shape, or may be of another spherical shape, for example.

Next, a vapor phase diffusion (1200) using antimony oxide (Sb ₂ O ₃ ) (not shown) as a solid diffusion source is formed on the main surface of the P-type semiconductor substrate 51 at the opening of each element region.
C., 1 hour) to form N containing antimony Sb as an impurity.
A high concentration collector buried region (N-BL) 52 of the mold is formed. The sheet resistance of the high concentration collector buried region 52 is 20 to 50 Ω / □, and the depth is about 1 to 2 μm.

After the SiO ₂ film is removed by wet etching using hydrofluoric acid or the like, a photoresist is formed on the entire surface, and an opening is formed by patterning a base region including an emitter region and an active element region including a collector region. Using this patterned photoresist as a mask, impurities are introduced into the high concentration collector buried region 52 by ion implantation of phosphorus ions P ⁺ or the like.

The ion implantation conditions for introducing the phosphorus ion P ⁺ impurity include, for example, an ion implantation energy of 20
Up to 80 keV, dose amount 5 × 10 ¹² -1 × 10 ¹⁴ pieces / c
m ² .

After the photoresist is removed, an N-type epitaxial layer (N-epi layer) 53 having a resistivity of about 0.3 to 5.0 .OMEGA. Deposits on the P-sub (51).

Subsequently, an SiO ₂ film having a thickness of about 50 nm is deposited on the surface of the P-sub 51, and then a silicon nitride film (not shown) is formed on the SiO ₂ film by CVD to a thickness of 100 nm.
m. The above SiO ₂ film is LOCOS
Buffer film when performing the method, and silicon nitride film is LOC
It is used for a mask when performing the OS method. Also S
The thickness of the iO ₂ film and the silicon nitride film is determined by the length of the bird's beak for element isolation formed by the LOCOS method,
It is determined by a range or the like in which generation of stress and crystal defects caused by the OS method can be prevented.

A photo-resist film (not shown) is deposited on the silicon nitride film, and patterned to form a device isolation region 54.
Open the portion corresponding to. Then, using this photoresist pattern, a silicon nitride film, a SiO ₂ film, a P-s
The surface of the ub 51 is sequentially etched. P-sub51
Of the element isolation region 5 by the LOCOS method.
The thickness of the P-type semiconductor substrate (P-sub) 51 after the formation of the semiconductor substrate 4 is made about に す る of the film thickness of the element isolation region 54 so that the surface of the substrate 51 becomes flat.

Thereafter, the photoresist (pattern) is removed, and an element isolation region (LOCOS) 54 is formed. The element isolation region 54 is formed of a SiO ₂ film on the surface side of the P-sub 51, which is the element formation surface, using, for example, steam oxidation at 1000 to 1050 ° C. The film thickness of the element isolation region 54 is, for example, 0.8 to 1.5 μm. Next, the silicon nitride film is removed by wet etching using hot phosphoric acid.

A photoresist film (not shown) is applied, and N ⁺ sinker 56 and N which is a part of the lower electrode of MIS-C 48 are coated.
A window for forming a p-type impurity region (same as N ⁺ sinker) 56 is opened, and using this as a mask, ion implantation energy is 40 to 400 keV, and dose is 1 × 10 ¹⁵ / c.
N-type impurities are ion-implanted under the condition of m ² to form an N ⁺ sinker 56 and an N-type impurity region 56, respectively.

Next, the photoresist is removed, and an SiO ₂ film (not shown) is formed to a thickness of 100 to 600 n by a CVD method or the like.
m, and a photoresist film (not shown) is applied on the upper surface. Then, etching is performed by the RIE method from the upper surface side of the photoresist film until the surface of the P-sub 51 becomes flat. After planarization, a SiO ₂ film (not shown) having a thickness of about 10 to 30 nm is formed by a thermal oxidation method, and a photoresist (not shown) is applied.
An opening is formed in the photoresist to form a P ⁺ element isolation layer 55 substantially at the center of the element isolation region 54 on the sub-51 (51).

Using this photoresist as a mask, a P-type impurity is ion-implanted to form a P ⁺ element isolation layer (ISO) 55 below the element isolation region 54. When the ion implantation conditions are, for example, boron ions B ⁺ , the ion implantation energy is 200 to 500 keV, and the dose is 1 × 10 ^13.
１1 × 10 ¹⁴ particles / cm ² . Subsequently, an SiO ₂ film 57 is deposited to a thickness of 50 to 200 nm using a CVD method or the like.

After the SiO ₂ film 57 is deposited on the entire surface, a part of the element, for example, a part of the active region of the NPN Tr 50 and a region corresponding to the capacitance of the MIS-C 48 are selectively opened. Particularly, in the capacitance of the MIS-C 48, a region (area) defined by the capacitance value is opened on the lower electrode of the N-type impurity region 56. Subsequently, a Si ₃ N ₄ film 58 as a first insulating film (dielectric film) is deposited on the entire surface, and the first insulating film 5 is formed.
8 except for the area corresponding to the MIS-C 48 of FIG.

As shown in FIG. 2B, the Poly-R
A Poly-Si (polysilicon) film 59 for (49) is deposited on the entire surface. This Poly-Si film 59 is, for example,
Then, boron ions B ⁺ or BF ₂ ⁺ ions of impurity ions are implanted with an ion implantation energy of ²⁰ to 100 keV and a dose of 1 × 10 ¹⁵ to 1 × 1.
It implants under the condition of 0 ¹⁶ pieces / cm ² . By processing the Poly-Si film 59 by photolithography and dry etching, the Poly-Si film 5 serving as a diffusion source of a P-type impurity in a base extraction region of the NPNTr ((NPN (bipolar) transistor) 50) and a graft base region 63 is formed.
9. A part of the upper electrode 71 of MIS-C48 or Poly-
An R49 resistor is formed. Note that this Poly-Si
The film 59 may be formed using a polysilicon film containing boron (P-type impurity).

Further, as shown in FIG. 3C, an insulating film such as a first SiO ₂ film (60) is
A thickness of about 500 nm is deposited, and only a region (area) corresponding to a set capacitance value for the MIS-C (48) is opened using a photoresist as a mask. Thereafter, a Si ₃ N ₄ film 61 used as a second insulating film (second insulating film) for preventing the characteristic fluctuation of the Poly-R 49 and for the MIS-C (48) capacitor.
Is formed by a CVD method. The thickness of the Si ₃ N ₄ film 61 is mainly determined by the capacitance value. However, the film thickness can be changed in consideration of the capacitance formed by the lower Si ₃ N ₄ film 58, and in this case, the film thickness can be set freely.

As shown in FIG. 3D, the Si ₃
An insulating film such as a second-layer SiO ₂ film (62) is formed on the N ₄ film 61 by a CVD method or the like. Subsequently, as shown in FIG. 4E, patterning for forming an NPN Tr emitter is performed, and a first SiO ₂ film 60 / Si ₃ N ₄ film 61 is formed.
The / second-layer SiO ₂ film 62 and the Poly-Si (polysilicon) film 59 for the Poly-R (49) are processed respectively.

After processing the Poly-Si film 59, the CV
The SiO ₂ film 62 is deposited to a thickness of 400 nm to 1 μm by the D method or the like, and is etched back over the entire surface by the RIE method, thereby forming a sidewall 65 made of an insulating film on the step side wall of the opening. Subsequently, as shown in FIG. 4F, a Poly-Si film 66 containing an N-type impurity is deposited on the entire surface. This is done by depositing a Poly-Si film containing an N-type impurity or by forming an impurity. Poly-S not containing
It can also be formed by ion-implanting an N-type impurity such as arsenic As or phosphorus P after forming the i-film. In the case of arsenic As ions, the ion implantation energy 4
0-70 kev, dose 1 × 10 ¹⁵ -1 × 10 ¹⁶ /
cm ² . Thereafter, a region corresponding to the upper electrode (66) of the MIS-C48 and a region corresponding to the emitter electrode 66 of the NPN Tr 50 are patterned and processed.

Next, the cap layer Si
O ₂ film is deposited to a thickness of about 300 to 500 nm,
A heat treatment at about 00 ° C. is performed for 10 minutes to 60 minutes, or a heat treatment at 1000 ° C. is performed using an RTA (Rapid Thermal Anneal) method.
A heat treatment is performed for a few seconds at a temperature of about 1200 ° C. to remove N-type impurities from the N-type Poly-Si film 66 to the base region 6.
4 to form an emitter region 67. Each of the heat treatment methods can be used alone, but of course, the heat treatment can be performed in combination of both. Subsequently, the above-described SiO ₂ film of the cap layer is removed by WET etching or the like. Here, the second upper electrode (66) of the MIS-C48 is a poly-Si for emitter of the NPN Tr50.
It is also used as the film 66.

Thereafter, the N-poly-Si film (66) is
The emitter electrode 77 of the PNTr 50 and the MIS-C48
Is formed by a lithography process and processed by RIE.

Then, as shown in FIG.
r50 base electrode 76, emitter electrode 77, collector electrode 78, MIS-C48 lower electrode 73, upper electrode 7
Patterning for taking out each electrode (74, 75) of 1, 72 and Poly-R49 is formed and processed by a lithography process, and a metal wiring such as Al is deposited. Although it is necessary to finally passivate, these can be formed using a known technique. Also, MIS-C
When the lower electrode 73 and the upper electrode 72 are finally connected by a metal wiring such as Al, the MIS-C is connected in parallel, the capacitance value increases, and high capacitance can be realized.

As described above, Poly-R49 and A
1st layer SiOx based insulating film / Si ₃
An N ₄ film / second-layer SiOx-based insulating film is formed in a laminated structure, and MIS-C48 is formed on a P-type semiconductor substrate / first-layer Si
By forming a laminated structure of ₃ N ₄ film / second layer conductive film, MIS-C48 with and prevent the hydrogen is absorbed into the Ti-based barrier metal to reduce the variation in the electrical characteristics of Poly-R49 Can be realized with a high capacity. As described above, the second insulating film formed on the upper part of the insulating film (dielectric film) used for the capacitance of the MIS-C48 is P
By being provided at the upper part of the poly-R49 and also serving as the upper part,
Variations in the electrical characteristics of Poly-R49 can be reduced. As described above, the present invention has been described based on the embodiments, but the present invention is not limited to these embodiments at all, and the process conditions and the structure can be appropriately changed within the technical idea of the present invention. is there.

[0051]

Thus, according to the present invention, Poly-R
A structure in which a first-layer SiOx-based insulating film / Si ₃ N ₄ film / second-layer SiOx-based insulating film is laminated as an interlayer film between the P-type semiconductor substrate and the first-layer Si ₃ N ₄ film /
By forming the MIS-C having a laminated structure of the second conductive film, Po which absorbs hydrogen in the Ti-based barrier metal is formed.
It is possible to prevent ly-R characteristic fluctuations and at the same time increase the capacity of the MIS-C. As a result, a high-performance, highly-integrated, and highly-reliable semiconductor element or circuit semiconductor device can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic sectional structural view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a schematic sectional structural view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 3 is a schematic sectional structural view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a schematic sectional structural view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a schematic sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a schematic sectional structural view showing a method of manufacturing a conventional semiconductor device.

FIG. 7 is a schematic sectional structural view showing a method of manufacturing a conventional semiconductor device.

FIG. 8 is a schematic sectional structural view showing a method for manufacturing a conventional semiconductor device.

FIG. 9 is a schematic sectional structural view showing a method for manufacturing a conventional semiconductor device.

FIG. 10 is a schematic cross-sectional structure diagram showing a method for manufacturing a conventional semiconductor device.

[Explanation of symbols]

1, 48, 103... MIS-C (MIS capacity), 2, 4
9, 104... Poly-R (polysilicon resistor, Pol
y-Si resistance), 3, 50, 101 ... NPNTr (NP
N (bipolar) transistor), 11, 51, 111
... P-sub (P-type semiconductor substrate), 12, 52, 112
... N ⁺ buried layer (N-BL, collector buried region), 13, 53, 113 ... N-epi layer (N-type epitaxial layer), 14, 54, 114 ... field oxide film (LOCOS, element isolation region), 15 , 55, 115 ...
Impurity layer (P ⁺ element isolation layer, ISO), 16, 56, 1
16 ... N ⁺ sinker (N-type impurity region, PLG), 1
8, 58, 61: Si ₃ N ₄ film (insulating film, dielectric film), 1
9, 26, 59, 119... Polysilicon film (poly-
Si film), 23, 63, 123 ... graft base (region), 24, 64, 124 ... base region (intrinsic base region, intrinsic base region), 31, 32, 7
1, 72 ... upper electrode, 33, 73, 136 ... lower electrode,
36, 76, 130, 135 ... base electrode, 37, 7
7, 131 ... emitter electrode, 38, 78, 132, 13
4: Collector electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/331 29/73 F term (Reference) 5F003 BA93 BA97 BB06 BC08 BJ18 BJ20 BZ05 5F032 AA13 CA01 CA14 DA02 DA12 DA24 DA34 DA43 DA45 DA53 DA74 5F038 AC03 AC05 AC15 AC16 AR09 AZ10 EZ12 EZ13 EZ14 EZ15 EZ16 EZ17 EZ20 5F082 AA08 BA04 BA07 BA26 BC01 BC13 BC18 DA10 EA06 EA09 EA12 EA27 EA33

Claims (23)

[Claims] A first impurity region of a first conductivity type formed in a semiconductor substrate; a first insulating film formed on the first impurity region of the first conductivity type; A first conductive film formed on the first insulating film, a second insulating film formed on the first conductive film, and a first electrode formed on the second insulating film A second electrode opened in the second insulating film and connected to the first conductive film; and a third electrode connected to the first impurity region of the first conductivity type.
A semiconductor device comprising: 2. The semiconductor device according to claim 1, wherein said first insulating film and said second insulating film are formed of a silicon nitride film.
13. The semiconductor device according to claim 1. 3. The method according to claim 1, wherein the first electrode has a multilayer structure of a polysilicon film and a metal film, and the polysilicon film has the same polysilicon film as an electrode film of the bipolar transistor. The semiconductor device according to claim 1. 4. The semiconductor device according to claim 1, wherein said first electrode and said third electrode are connected to form an MIS capacitor. 5. The semiconductor device according to claim 1, wherein said second insulating film is deposited on a resistor formed on said semiconductor substrate to form an interlayer film. 6. A first insulating film for element isolation formed in a semiconductor substrate, a second insulating film formed on the first insulating film for element isolation, and on the second insulating film. A first conductive film formed on the first conductive film, a second insulating film formed on the first conductive film, and a plurality of openings formed in the second insulating film and connected to the first conductive film. A semiconductor device comprising: 7. The semiconductor device according to claim 6, wherein said second insulating film is made of a silicon nitride film. 8. The semiconductor device according to claim 6, wherein said first conductive film is made of a polysilicon film, and said polysilicon film is made of the same polysilicon film as an electrode film of the bipolar transistor. Semiconductor device. 9. The semiconductor device according to claim 6, wherein said second insulating film is formed of an insulating film used for a capacitor formed on said semiconductor substrate. 10. A method of manufacturing a semiconductor device, comprising: forming a first conductive type semiconductor layer on a semiconductor substrate; and selectively forming an element isolation insulating film in the first conductive type semiconductor layer. Forming a first impurity region by introducing a first impurity into the semiconductor layer of the first conductivity type; depositing a first insulating film over the entire surface; Forming a second insulating film after opening the first insulating film on the region; depositing a polysilicon film over the entire surface, processing the polysilicon film into a predetermined shape, and then depositing a third insulating film; A step of depositing a fourth insulating film and forming a conductive film after opening the third insulating film; a step of processing the conductive film to form a first electrode; Forming a second electrode by opening a film and the fourth insulating film; and forming the first, third, and third electrodes. Forming a third electrode by opening a fourth insulating film. 11. The method according to claim 10, wherein said second insulating film and said fourth insulating film are formed of a silicon nitride film. 12. The semiconductor device according to claim 1, wherein said first electrode has a multilayer structure of said polysilicon film and a metal film, and said polysilicon film is formed of the same polysilicon film as an electrode film of a bipolar transistor. The method of manufacturing a semiconductor device according to claim 10. 13. The MIS capacitor formed by connecting the first electrode and the third electrode.
0. A method for manufacturing a semiconductor device according to item 0. 14. The method according to claim 10, wherein said fourth insulating film is deposited on a resistor formed on said semiconductor substrate to form an interlayer film. 15. A method of manufacturing a semiconductor device, comprising: a step of forming a first conductivity type semiconductor layer on a semiconductor substrate; and selectively forming an element isolation insulating film in the first conductivity type semiconductor layer. Forming a first impurity region by introducing a first impurity into the semiconductor layer of the first conductivity type; depositing a first insulating film over the entire surface; After opening the first insulating film on the region, a second
Depositing a polysilicon film over the entire surface, processing the polysilicon film into a predetermined shape of a capacitance region and a resistance region, and then depositing a third insulation film; A step of depositing a fourth insulating film after processing the opening of the insulating film and processing it into a predetermined pattern to form a conductive film; a step of processing the conductive film to form a first electrode; Forming an opening in an insulating film and the fourth insulating film to form a second electrode of the capacitor and a third electrode of the resistor; opening the first, third and fourth insulating films; Forming a fourth electrode of the capacitor. 16. The semiconductor device according to claim 1, wherein said second insulating film and said fourth insulating film are formed of a silicon nitride film.
6. The method for manufacturing a semiconductor device according to item 5. 17. The semiconductor device according to claim 17, wherein said first electrode is formed in a multilayer structure of said polysilicon film and a metal film, and said polysilicon film is formed of the same polysilicon film as an electrode film of a bipolar transistor. Item 16. A method for manufacturing a semiconductor device according to item 15. 18. The MIS capacitor according to claim 1, wherein the first electrode and the third electrode are connected to form an MIS capacitor.
6. The method for manufacturing a semiconductor device according to item 5. 19. The method according to claim 15, wherein said fourth insulating film is deposited on a resistor formed on said semiconductor substrate to form an interlayer film. 20. A method of manufacturing a semiconductor device having a bipolar transistor, a polysilicon resistor and a MIS capacitance, comprising: forming an SiOx-based insulating film on a semiconductor substrate and patterning the insulating film to form the MIS capacitance; A first step of opening a first connection hole for forming the first connection hole; and a Si ₃ N _{4 of} a first dielectric film filling the first connection hole.
A second step of forming a film and patterning the Si ₃ N ₄ film; a third step of opening a base extraction electrode window of the bipolar transistor; forming a first conductive film on the entire surface; A fourth step of patterning the conductive film to form a base take-out electrode covering the base take-out electrode window and an electrode region of polysilicon resistance and MIS capacitance; and depositing a first-layer interlayer insulating film of the SiOx-based material. , The 1
A fifth step of opening a second connection hole for forming the MIS capacitance by patterning a first-layer interlayer insulating film; a second dielectric film filling the connection hole for forming the MIS capacitance; and the SiOx-based material. A material is coated with a second interlayer insulating film, and the second interlayer insulating film is patterned to form the MI.
Sixth forming area for taking out upper electrode of S capacitor
A seventh step of depositing and patterning a second conductive film to form an emitter extraction electrode of the bipolar transistor and an upper electrode region of the MIS capacitor; and a first interlayer insulating film, An eighth step of patterning the dielectric film and the second interlayer insulating film to open connection holes respectively connected to the base extraction electrode, the polysilicon resistor and the MIS capacitor, and an upper wiring for filling the connection holes And a ninth step of forming a semiconductor device. 21. The method according to claim 19, wherein the first and second dielectric films are made of Si ₃ N _4.
The method for manufacturing a semiconductor device according to claim 20, wherein the semiconductor device is formed of a film. 22. The method according to claim 20, wherein the first and second conductive films are formed of a polysilicon film. 23. The method of manufacturing a semiconductor device according to claim 20, wherein said upper wiring is formed by laminating a Ti-based barrier metal and a conductive material film.