JPH10170952A - Liquid crystal panel substrate and its manufacturing method, liquid crystal panel, and projection type display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a high numerical aperture by forming a sheet layer that consists of an electrically conductive layer, in at least below the region connected to the pixel electrodes of the semiconductor layer (a polysilicon layer) which is to be the active layer of a thin film transistor(TFT). SOLUTION: After forming the polysilicon layer on the surface of a substrate 1, a patterning is conducted by an etching to form the drain region of the TFT. Then, a land shaped sheet layer 2 is formed on the region. In the polysilicon, which constitutes the layer 2, impurity, for example phosphorus, is doped and the resistance is made lower. Then, a second polysilicon layer, which constitutes the channel region of the TFT, is deposited over the layer 2 and the substrate 1. Then, a patterning is conducted by an etching so as to form a land shaped polysilicon layer 3, which is to be the source, the drain and the channel regions of the TFT, is formed. Having completed the above, thermal oxidation is conducted to form a gate insulating film 4 on the surface of the layer 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display and an active matrix type liquid crystal display, and more particularly to an active matrix in which a pixel electrode is driven by a polysilicon thin film transistor (hereinafter referred to as a TFT) formed on a substrate. TECHNICAL FIELD The present invention relates to a substrate used in a liquid crystal display device, a method for manufacturing the same, and a technique suitable for use in a projection display device to which the substrate is applied.

[0002]

2. Description of the Related Art Conventionally, as an active matrix type liquid crystal display device, pixel electrodes are formed in a matrix on a glass substrate, and a TFT using amorphous silicon or polysilicon is formed corresponding to each pixel electrode. ,
A liquid crystal display device having a configuration in which a liquid crystal is driven by applying a voltage to each pixel electrode by a TFT has been put to practical use.
Among the active matrix type liquid crystal display devices, a device using a polysilicon TFT is suitable for high integration because transistors constituting peripheral circuits such as a shift register and a driving circuit can be formed in the same process. Have been.

FIGS. 14 and 15 show the polysilicon T
1 shows a planar layout and a cross-sectional structure of a conventional example of a liquid crystal panel substrate using FT. FIG. 15 is a cross section taken along line AA ′ in FIG.

[0004] As shown in FIG.
And data lines 12 are arranged in a matrix,
A pixel electrode 10 made of an ITO film is formed in a rectangular frame divided by a scanning line 11 and a data line 12. TF for applying a voltage on the data line 12 to the pixel electrode 10
T is provided at one of the corners of the pixel electrode (the lower left corner in FIG. 14). In FIG. 15, 1 is a substrate made of glass or the like, 3 is a polysilicon layer serving as an active layer of a TFT formed in an island shape on the surface of the substrate 1, and 4 is formed on the polysilicon layer 3 by thermal oxidation. This is a gate insulating film. Reference numeral 5 denotes a gate electrode formed of a second polysilicon layer formed substantially at the center of the polysilicon layer 3 with a gate insulating film 4 interposed therebetween. The gate electrode 5 is formed so as to protrude from the scanning line 11 as shown in FIG. 6
Is a first interlayer insulating film formed so as to cover the scanning lines 11, 12 is a data line formed on the first interlayer insulating film 6, and the data line 12 is formed of an aluminum layer or the like. The first interlayer insulating film 6 and the gate insulating film 5 are connected to the polysilicon layer 3 through contact holes 7a formed by opening the same. Reference numeral 9 denotes a second interlayer insulating film formed so as to cover the upper part of the data line 12, and the pixel electrode 10 is formed on the second interlayer insulating film 9, and includes a first interlayer insulating film 6 and a second interlayer insulating film. 9 and the gate insulating film 4 are connected to the polysilicon layer 3 through contact holes 7b formed by opening.

[0005]

In a conventional active matrix type liquid crystal display device using a polysilicon TFT, from the viewpoint of improving the aperture ratio of a liquid crystal panel,
It is desired that the opening areas of the contact holes 7a and 7b are formed as designed. Therefore, it has been considered that the contact holes 7a and 7b are formed by using anisotropic dry etching. However, in dry etching, the selectivity between the insulating film (the gate insulating film 4, the first interlayer insulating film 6, and the second interlayer insulating film 9) and the polysilicon layer 3 serving as an active layer cannot be sufficiently obtained, and Since the thickness of the insulating film varies by about 10 to 20%, it is difficult to form a contact hole with high accuracy up to the surface of the polysilicon layer 3 by controlling the amount of etching with time. In some cases, the insulating film may remain, or may pass through the polysilicon layer due to over-etching.

Therefore, conventionally, dry etching is performed by setting the time so that the contact hole stops short of the surface of the polysilicon layer 3 while taking into account the error in the thickness of the insulating film. At least one minute or more of wet etching was performed to reach the surface of the layer 3. However,
Since the wet etching is an isotropic etching, the insulating film is also etched in the lateral direction, and the opening area of the contact hole becomes larger than a designed value.
Particularly, the drain-side contact hole 7b formed over the first interlayer insulating film 6, the second interlayer insulating film 9, and the gate insulating film 5 is formed because the interlayer insulating film 9 is formed on the data line 12 made of aluminum or the like. Since it has the property of being easily etched because it cannot be formed by a high temperature treatment of 500 ° C. or more, there is a problem that the aperture area is increased by wet etching.

Therefore, a black matrix as a light-shielding layer provided on the opposite substrate must be formed to be large enough to completely cover the contact holes, thereby lowering the aperture ratio of the liquid crystal panel.
It has been clarified that if the contact hole is formed larger than necessary, the pixel electrode 10 comes into contact with the data line 12 to cause a short-circuit defect.

Incidentally, a method of increasing the thickness of the polysilicon layer 3 in advance to prevent the polysilicon layer from coming through due to the dry etching is conceivable. However, in such a case, the thickness of the channel region of the TFT becomes large. As a result, desired on / off characteristics cannot be obtained, and in particular, a new problem that an increase in off leak current due to light is caused.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technique capable of preventing a polysilicon layer below a contact hole on a drain side (a region connected to a pixel electrode of a TFT) of a pixel driving TFT. It is in.

Another object of the present invention is to provide a pixel driving TFT.
The present invention is to provide a technique capable of preventing a leakage current of a TFT while preventing a polysilicon layer below a drain-side contact hole from coming through.

Still another object of the present invention is to provide a technique capable of sufficiently securing an aperture ratio even when a pitch of pixels provided in a matrix in a display area is reduced in accordance with a higher definition of a liquid crystal panel. Is to provide.

Still another object of the present invention is to provide a liquid crystal panel and a projection type display device capable of performing bright and high-contrast display.

[0013]

According to the present invention, in order to achieve the above object, pixel electrodes are formed in a matrix on a substrate, and a TF is provided corresponding to each pixel electrode.
In a liquid crystal panel substrate in which T is formed and a voltage is applied to the pixel electrode via the thin film transistor, the liquid crystal panel is connected to a pixel electrode of a semiconductor layer (polysilicon layer) to be an active layer of the thin film transistor. A sheet layer made of a conductive layer such as a polysilicon layer is formed below the region to be formed. The thickness of the sheet layer is preferably 500 to 1500 angstroms, more preferably 800 to 1200 angstroms.

Further, according to the present invention, pixel electrodes are arranged in a matrix on a substrate, and TFTs are formed corresponding to the respective pixel electrodes, and a voltage is applied to the pixel electrodes via the TFTs. In the manufacturing process of the liquid crystal panel substrate configured as described above, the semiconductor layer (polysilicon layer) serving as the active layer of the TFT is formed particularly below the drain side.
A sheet layer made of a conductive layer such as a polysilicon layer is formed in advance, and dry etching is performed to form contact holes for the source and drain electrodes of the TFT. On the other hand, the time is set such that over-etching is performed in consideration of the thickness variation.

According to the above-described means, a contact hole penetrating through the insulating film can be surely formed by dry etching, and the contact hole can be prevented from passing through the drain region by the sheet layer. Since it is not necessary to perform wet etching for a long time, a contact hole having a small opening area can be formed by suppressing the lateral spread of the contact hole.
As a result, a sufficient aperture ratio can be ensured even if the pixel pitch becomes smaller as the definition of the liquid crystal panel increases.

Further, a light-shielding film such as tungsten silicide may be formed under the semiconductor layer, which is the active layer of the TFT, particularly under the channel region. Accordingly, it is possible to suppress the light reflected on the back surface of the liquid crystal panel from passing through the channel region and causing a leak current to flow. When a light-shielding film is provided below the channel region, the sheet layer below the drain region may be formed of the same material as the light-shielding film.
As a result, the leakage current can be suppressed without increasing the number of process steps, and by selecting a material having a high selectivity with respect to the semiconductor layer forming the active layer, the sheet layer can be formed when forming the contact hole. By using it as an etch stopper, it is possible to further prevent the drain region from coming through.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings together with a manufacturing process.

FIGS. 1 and 2 are sectional views showing a first embodiment of a liquid crystal panel substrate to which the present invention is applied, in the order of manufacturing steps. 1 and 2 show a cross-sectional structure of one pixel portion among pixels arranged in a matrix.

In FIG. 1, reference numeral 1 denotes a substrate such as a quartz substrate or a hard glass substrate. In this embodiment, a polysilicon layer having a thickness of 500 to 1500 angstroms, desirably 800 to 1200 angstroms is formed on the surface of a substrate 1 by a low pressure CVD method or the like, and then patterned by etching to form a TFT to be formed later. An island-shaped sheet layer 2 is formed in a portion to be a drain region (FIG. 1A). The polysilicon constituting the sheet layer 2 may be made to have low resistance by doping impurities such as phosphorus.

Next, a second polysilicon layer constituting a channel region of the TFT is deposited on the sheet layer 2 and the substrate 1 to a thickness of 1000 to 2000 angstroms, preferably about 1500 angstroms by a low pressure CVD method or the like. After that, patterning is performed by etching to form an island-shaped polysilicon layer 3 to be the source, drain and channel regions of the TFT. Then, a gate insulating film 4 having a thickness of 800 to 1500 angstroms is formed on the surface of the polysilicon layer 3 by performing thermal oxidation (FIG. 1B). By thermal oxidation, the channel region is brought to a thickness such as 300 to 1500 Angstroms, preferably 350 to 550 Angstroms. The optimal thickness, including the channel region and the underlying sheet layer 2, is between 1200 and 2000 angstroms, preferably 1500 angstroms.

Thereafter, the third polysilicon layer constituting the gate electrode of the TFT and the scanning line is formed on the gate insulating film 4 and the substrate 1 by a thermal CVD method or the like.
After forming to a thickness of 5000 angstroms, patterning is performed by etching to form a gate electrode 5 located substantially at the center of the channel region. then,
Using the gate electrode as a mask, a region to be a source region and a drain region, which is self-aligned with the active layer of the TFT, is formed by ion implantation of an impurity (for example, phosphorus).
At this time, no impurity is introduced into the channel region below the gate electrode 5, and that portion remains as the channel region 3c (FIG. 1C).

Regarding the formation of the source / drain regions,
Using the gate electrode as a mask, an impurity (phosphorus) of 1 × 10
After implantation at a low concentration at a dose of ¹³ / cm ^{2 to} 3 × 10 ¹³ / cm ^2, a mask layer wider than the width of the gate electrode 5 is formed on the gate electrode 5 to further remove impurities (phosphorus). By implanting at a dose of 1 × 10 ¹⁵ / cm ^{2 to} 3 × 10 ¹⁵ / cm ^2, the region of the semiconductor layer where the mask layer is formed becomes a lightly doped drain (L
DD) structure. In this case, source / drain regions are formed by low-concentration regions 3d and 3e in which impurities are implanted at a low concentration adjacent to channel region 3c and high-concentration regions 3a and 3b in which impurities are implanted at a high concentration outside thereof. And the high concentration regions 3a and 3b become contact regions. In addition, a pattern is formed using a mask wider than the width of the gate electrode 2 without performing lightly doping, followed by ion implantation to form a source / drain and then over-etching the gate electrode, thereby offsetting. You may make it become a structure.
Instead of the LDD structure or the offset structure, a gate-self-aligned type in which high-concentration impurity ions are simply implanted using the gate electrode as a mask may be used. However, the off-state leakage current is further reduced by using the LDD structure or the offset structure. Can be reduced.

Although not shown, when forming the gate electrode 5, a scanning line continuous with the gate electrode 5 is also formed at the same time. It is desirable that the distance l between the end of the gate electrode 5 and the end of the sheet layer 2 is set to be 2 μm or more in order to prevent deterioration of TFT characteristics. As the material of the gate electrode 5 and the scanning line, besides polysilicon, a high melting point metal such as Mo, Ti, W, or MoSi,
A metal silicide such as WSi or a multilayer structure of polysilicon and metal silicide may be used. The gate electrode 5 is not limited to the two-layer structure as described above, and may have three or more layers. For example, the gate electrode 5 is formed of a polysilicon layer having good adhesion, a metal silicide layer such as tungsten silicide having a low resistance on the polysilicon layer, and a polysilicon layer on the polysilicon layer to prevent the metal silicide layer from peeling off. It may be formed so as to cover the layer and the metal silicide layer.

Next, a first interlayer insulating film 6 such as a phosphorus-free silicate glass film (NSG film) is formed on the gate electrode 5, the gate insulating film 4 and the substrate 1 by high pressure CVD.
After being formed to a thickness of 9000 to 11000 angstroms by a method or the like, contact holes 7a are formed in the gate insulating film 4 and the first interlayer insulating film 6 above the source region 3a by dry etching (FIG. 1D). . At this time, although not particularly limited, it is preferable to first form a contact hole immediately before the surface of the source region by anisotropic dry etching, and then perform wet etching for a short time to remove the oxide film on the surface of the source region. High pressure CV
The first interlayer insulating film formed by the method D has a reduced pressure CV
Since the contact hole is denser than the second interlayer insulating film formed by the method D, the contact hole is not expanded in the lateral direction by wet etching, and the contact portion surface is not roughened unlike dry etching. As anisotropic dry etching, for example, CHF3 (Freon)
Reactive ion etching, chemical dry etching, plasma etching, or the like using SF6 or SF6 as an etching gas can be considered. The etching rate may be changed by changing the mixing ratio.

Thereafter, a low-resistance conductive layer of aluminum or the like is formed on the entire surface by sputtering, and patterning is performed to form a source electrode 8 that is in contact with the source region 3a through the contact hole 7a. At this time, although not shown, a data line 12 for supplying a voltage applied to the pixel electrode is formed on the first interlayer insulating film 6 at the same time. Then, a second interlayer insulating film 9 such as a silicate glass film (BPSG film) containing boron and phosphorus is formed thereon to a thickness of 8000 to 12000 angstroms by a low pressure CVD method (FIG. 2E).

Next, a contact hole 7b for contacting a pixel electrode is formed in the first interlayer insulating film 6 and the second interlayer insulating film 9 above the drain region 3d by anisotropic dry etching (FIG. 2F). ). In the dry etching, the etching amount is controlled by time or the like, and the conditions are set such that the insulating films 6 and 9 are over-etched in consideration of the thickness variation. by this,
The contact hole 7 which reaches the drain region 3d surely
b is formed, and even if over-etching occurs and the contact hole 7b passes through the drain region 3d made of polysilicon, the sheet layer 2 is provided thereunder, so that the contact hole 7b passes through the sheet layer 2. It is possible to control so that the contact hole 7b is not formed so deeply. In addition, as the anisotropic dry etching, for example, reactive ion etching, chemical dry etching, plasma etching, or the like using CHF ₃ or SF ₆ as an etching gas can be considered.
For example, in the case of dry etching using a mixed gas of CHF ₃ , SF ₆ and He, the conditions are 1600 to 1700 mTorr
And a power of 100 to 500 W. The rate at the time of dry etching is B
5500 angstroms / min ± 1 for PSG film
500 angstroms / min, 28 for NSG film
00 angstrom / min ± 1500 angstrom / min, and 400 angstrom / min for the polysilicon layer.

The contact holes 7b of the first interlayer insulating film 6 and the second interlayer insulating film 9 above the drain region contact portion 3b may be short-time (eg, 10 seconds to 1 minute) after dry etching, if necessary. By performing wet etching, a taper may be formed in the contact hole 7b as shown in the figure. With this taper, the coverage of the ITO film forming the pixel electrode with respect to the contact hole 7b can be improved.

After the formation of the contact hole 7b, an ITO film is formed on the surface of the second interlayer insulating film 9 by sputtering or the like to a thickness of 1000 to 2000 angstroms, and then patterned to form a transparent film. The pixel electrode 10 is formed (FIG. 2G). In an actual product, an alignment film made of polyimide or the like is formed on the pixel electrode 10 and the second interlayer insulating film 9 by about 200 to 1000.
It is formed to a thickness of about Å and rubbed (alignment treatment) to complete a liquid crystal panel substrate.

Further, in the liquid crystal panel substrate of the embodiment, a transparent conductive film (I
A color filter layer corresponding to the counter electrode and the pixel electrode made of TO) and a glass substrate on the incident side on which a black matrix surrounding the color filter layer is formed are arranged at appropriate intervals, and the periphery is sealed with a sealing material. TN (Tw
isted Nematic) liquid crystal or SH (Super Homeotropi)
c) A liquid crystal panel is formed by filling a type liquid crystal or the like.

FIG. 3 shows an example of a planar layout configuration of one pixel portion of a liquid crystal panel substrate to which the present embodiment is applied. In FIG. 1, reference numeral 11 denotes a scanning line formed so as to extend along one boundary of pixels arranged in a matrix, and an intersection (a portion indicated by hatching H) between the scanning line 11 and a channel region. Is a gate electrode, and a channel region is formed below the gate electrode. Reference numeral 12 denotes a data line formed along the other boundary of the pixel in a direction orthogonal to the scanning line 11. In this embodiment, the source electrode 8 is formed so as to protrude from the data line 12. Moreover, the source-side contact hole 7a and the drain-side contact hole 7b are provided so as to be located in pixels adjacent to each other with the scanning line 11 interposed therebetween. In FIG. 3, reference numeral 13 denotes a black matrix provided on the opposite substrate, and the inside of the black matrix 13 is a region through which light is transmitted.

Further, in this embodiment, although not particularly limited, in order to increase the capacitance connected to the drain of the TFT, the second polysilicon layer constituting the channel region is replaced with a signal line 3a as shown by reference numeral 3a. Along the line 12, a part of the preceding scanning line 11 also extends downward along the data line 12 as indicated by reference numeral 11 a. As a result, the capacitance between the extended portion 3a made of the second polysilicon layer and the extended portion 11a of the scanning line 11 (the gate insulating film is made of a dielectric) is applied to each pixel electrode as a storage capacitance. Is applied to the drain of the TFT.

According to this embodiment, since the contact hole 7b on the drain region side is formed by dry etching, the lateral spread of the contact hole can be suppressed as much as possible. As a result, the size of the black matrix as a light-shielding layer provided on the opposite substrate can be reduced, the aperture ratio can be increased, and a short-circuit defect between the pixel electrode and the signal line (12) can be avoided. Become.

Next, in order to make it easier to understand the effect of the present embodiment, the case where the contact hole 7b is formed in the drain region by anisotropic dry etching or mainly by dry etching as in the above embodiment is described. The difference in the case where the etching is performed in combination with the wet etching will be described with reference to FIG.

The contact hole 7 shown in FIG.
a and 7b show mask patterns at the time of design. When a contact hole is formed in the interlayer insulating film by dry etching or mainly by dry etching using such a mask pattern, as shown by reference numerals 7a 'and 7b' in FIG. A contact hole is formed. On the other hand, when a contact hole is formed in the interlayer insulating film using a similar mask pattern by a combination of dry etching and wet etching for one minute or longer, reference numerals 7a ″ and 7a in FIG.
4 (a) and 4 (b). As is apparent from a comparison between FIGS. 4 (a) and 4 (b), when wet etching for 1 minute or more is used in combination, the contact on the drain region side is particularly increased. The outermost diameter L of the hole 7b is considerably larger than the design value.

As a result, a black matrix as a light shielding layer provided on the opposite substrate is formed in the contact hole 7.
b must be formed so as to completely cover b.
As a result, the aperture ratio of the liquid crystal panel is reduced, and when the contact hole is formed larger than necessary, the pixel electrode 10 formed inside the contact hole is reduced.
(Refer to FIG. 1g.) There is a possibility that a short-circuit defect may occur in which the mask is in contact with the signal line 12 (in particular, the misalignment of the mask for forming the signal line 12 and the misalignment of the mask for forming the contact hole approach each other. However, according to the above embodiment, a contact hole having a small diameter close to the mask pattern can be formed, thereby preventing such a short-circuit defect from occurring. can do. According to experiments by the present inventors, the design value (length of one side) of the contact hole 7b is 3
In the case of μm, 3-4
While a contact hole having a diameter of μm was obtained, it was found that the diameter was increased to 12 μm when the hole was opened by a method using both conventional dry etching and wet etching for one minute or more.

FIG. 5 shows a second embodiment of the present invention. This embodiment is almost the same as the first embodiment, except that the polysilicon layer 3 serving as an active layer is formed so that the channel region (H) of the TFT is located below the signal line 12. And the point that the extended portion 3a of the polysilicon layer 3 and the extended portion 11a of the scanning line 11 that constitute the storage capacitor are formed avoiding the TFT portion. Also in this embodiment, since the sheet layer 2 is provided below the contact hole 7b, the contact hole 7b can be formed by anisotropic dry etching, thereby suppressing the lateral spread of the contact hole. The aperture ratio can be increased. Moreover, in this embodiment, T
Since the channel portion (H) of the FT is disposed below the signal line 12, the data line 12 becomes a light-shielding layer, so that light from the incident side passes through the channel portion and a leak current flows. Can be prevented. Therefore, the size of the black matrix provided on the counter substrate can be reduced or omitted, and the aperture ratio can be further increased.

FIG. 6 shows a third embodiment of the present invention, and FIG.
(A) shows a case where a contact hole 7b is formed by anisotropic dry etching in the third embodiment, and (b) shows a case where a contact hole is formed by using both dry etching and wet etching for one minute or more. The results of the respective cases are shown below. This third embodiment (FIG. 6)
It has almost the same configuration as the first embodiment (see FIG. 3) and can be formed by the same process. The only difference is that the pitch of the pixels in the X direction (the direction along the scanning line 11) is reduced. In FIG. 6, reference numeral 13 denotes a boundary between the counter substrate and the black matrix.

When the conventional method of forming a contact hole by using both dry etching and wet etching for one minute or more is applied, the drain side contact hole 7b
The diameter of the pixel becomes large, the aperture ratio is remarkably reduced, and a short circuit defect with a signal line occurs. As the pixel pitch becomes smaller, it is more difficult to obtain a liquid crystal panel having an aperture ratio of a practical level (40% or more). However, by applying the present invention, even if the liquid crystal panel substrate has a short pixel pitch in the X direction as compared with the Y direction (direction along the data line 12) as shown in FIG. It can be easily understood from FIG.

FIG. 8 shows a fourth embodiment of the present invention. In this embodiment, a light-shielding film 14 made of a metal silicide such as tungsten silicide is provided below a channel region 3c and a source region 3a of a polysilicon layer 3 serving as an active layer of a TFT, and below a drain region 3d. The sheet layer 2 is composed of a metal silicide layer formed in the same step as the light shielding layer 14. Since the light-shielding film 14 is made of a conductive layer, an insulating film 15 such as silicon oxide is formed on the surface thereof. In this embodiment, since the light-shielding film 14 is disposed below the polysilicon layer 3 as described above, the light-shielding film 14 is disposed from the bonding surface with the polarizing plate 16 (not shown) bonded to the back surface of the substrate. Can be prevented from passing through the polysilicon layer 3 as an active layer of the TFT, thereby suppressing leakage current.
Moreover, since the light-shielding film 14 and the sheet layer 2 are formed of the same layer, the effect of suppressing the leak current can be obtained without increasing the number of process steps. Further, by selecting a material having a high selectivity with respect to polysilicon as the material of the sheet layer 2, the sheet layer 2 is formed in the contact hole 7.
By acting as an etch stopper at the time of forming b, it is possible to prevent the contact hole from passing through the drain region.

It is more desirable that the surface of the light shielding film 14 be subjected to an antireflection treatment. The light-shielding film 14 is formed on the glass substrate 10 by sputtering or the like to a thickness of about 500 to 3,000 angstroms, preferably about 1,000 to 2,000 angstroms, and then formed into a desired shape by patterning by dry etching or wet etching. . As a material of the light shielding film 14, a high melting point metal or metal silicide that can withstand a temperature of 1000 ° C. or more is selected. Specifically, in addition to tungsten silicide (WSi), Mo, MoSi,
Any conductive material, such as Cr or CrSi, through which light is hardly transmitted may be used.

The present embodiment has an effect that, with such a configuration, it is possible to suppress the light reflected on the back surface of the liquid crystal panel from passing through the channel region and flowing the leak current.

Since a light-shielding film can be provided below the channel region, the sheet layer below the drain region can be formed of the same material as the light-shielding film. Therefore, the leakage current can be suppressed without increasing the number of process steps, and the sheet layer can be etched at the time of forming contact holes by selecting a material having a high selectivity with respect to the semiconductor layer forming the active layer. There is an effect that it can be used as a stopper to further prevent the drain region from coming through.

Next, the relationship between the pixel pitch, the diameter of the drain side contact hole 7b, and the aperture ratio of the liquid crystal panel will be described.

FIG. 10 is a table showing the result of examining the effect of the diameter L of the contact hole 7b on the aperture ratio of the liquid crystal panel in relation to the pixel pitch, and FIG. 11 is a graph showing the result. is there.

10 and 11 that the smaller the pixel pitch, the greater the effect of the diameter L of the contact hole 7b on the aperture ratio of the liquid crystal panel.
That is, for example, if the pixel pitch is 100 μm, even if the diameter L of the contact hole 7b increases from 3 μm to 12 μm, the aperture ratio of the liquid crystal panel becomes 90.2% to 8%.
It only drops to 8.8%, and the effect on the aperture ratio is extremely small. However, when the pixel pitch becomes 50 μm, the diameter L of the contact hole 7b becomes 3 μm to 12 μm.
When the pixel pitch becomes 40 μm, the diameter L of the contact hole 7b increases from 3 μm to 12 μm when the aperture ratio of the liquid crystal panel is reduced from 80.7% to 75.2%, which is about 5%. In addition, the aperture ratio of the liquid crystal panel is reduced by about 10% from 76.0% to 67.6%, which indicates that the effect on the aperture ratio is extremely large.

From the above, it can be said that the effect of the present invention is great when applied to a liquid crystal panel substrate having a pixel pitch of 50 μm or less. For example, a VGA (video graphic array) for a 1.3-inch diagonal liquid crystal display device
Since the pixel pitch becomes about 40 to 45 μm, when the drain side contact hole is formed by a method using both conventional dry etching and wet etching for one minute or more, the diameter increases to 12 μm, so that the aperture ratio becomes 70 μm.
%, But when the present invention is applied and an aperture is opened by anisotropic dry etching or dry etching within 1 minute, the diameter does not increase so much that the aperture ratio becomes 75% or more and the aperture ratio becomes 10% or more. %.

FIG. 12 shows an example of a system configuration of a substrate on the TFT side of a liquid crystal panel to which the present invention is applied. In the figure, reference numeral 90 denotes scanning lines 11 arranged so as to cross each other.
Each pixel 90 is a pixel electrode 10 made of ITO or the like, and a TFT 91 for applying a voltage to the pixel electrode 10 according to an image signal on the data line 12. Consists of TFT in the same row
Reference numeral 91 denotes a gate electrode connected to the same scanning line 11,
The drain is connected to the corresponding pixel electrode 10. The sources of the TFTs 91 in the same column are connected to the same data line 12. In this embodiment, peripheral circuits (X, Y shift registers and sampling means) 50,
The transistor forming the pixel circuit 60 is formed of a so-called polysilicon TFT having a polysilicon layer as an active layer, similarly to the TFT driving the pixel. The transistors forming the peripheral circuits 50 and 60 are formed together with the pixel driving TFT by the same process. , Formed simultaneously.

In this embodiment, a shift register (hereinafter referred to as an X shift register) 51 for sequentially selecting the signal lines 12 is arranged on one side (upper side in the figure) of the display area (pixel matrix). On another side, a shift register (hereinafter referred to as a Y shift register) 61 for sequentially selecting and driving the scanning lines 11 is provided. A buffer 63 is provided at the next stage of the Y shift register 61 as necessary.

The other end of each data line 12 is provided with a sampling switch 52 composed of a TFT, and these sampling switches 52 are connected to external terminals 7.
4, 75, and 76, which are connected between video signal lines 54, 55, and 56 for transmitting data signals and data signals, and are sequentially turned on / off by sampling signals output from the X shift register 51. It is configured as follows. X shift register 51 receives clock signals CLX and / CLK externally input through terminals 72 and 73.
Sampling signal X1, which selects all the data lines 12 one by one in order during one horizontal scanning period based on
X2, X3, .DELTA.Xn are formed and supplied to the control terminal of the sampling switch 52. On the other hand, the Y shift register 61 is operated in synchronization with clock signals CLY and / CLY input from the outside via terminals 77 and 78, and sequentially drives the scanning lines 11.

FIG. 9 shows a sectional structure of a liquid crystal panel 30 to which the liquid crystal panel substrate of the present embodiment is applied. As shown in the drawing, on the front side of the liquid crystal panel substrate 1, an incident side having a counter electrode 33 made of a transparent conductive film (ITO) to which a counter electrode potential is applied and a color filter layer (including a black matrix) 13 is provided. Glass substrates 35 are arranged at appropriate intervals, and a TN (Twisted Nematic) liquid crystal or SH (S
The liquid crystal panel 30 is filled with an upper homeotropic type liquid crystal 37 or the like. In addition, the peripheral circuit 50,
The upper part of 60 is configured to be shielded from light by, for example, a black matrix provided on the counter substrate 35.
The position where the sealing material is provided is determined so that the pad 70 as an external terminal for inputting a signal from the outside is located outside the sealing material 36.

FIG. 13 shows an example of the configuration of a video projector as an example of a projection display apparatus in which the liquid crystal panel of this embodiment is applied as a light valve.

In FIG. 13, 370 is a light source such as a halogen lamp, 371 is a parabolic mirror, 372 is a heat ray cut filter, 373, 375, and 376 are dichroic mirrors for blue reflection, green reflection, and red reflection, respectively.
4,377 is a reflection mirror, 378,379,380 are light valves made of the liquid crystal panel of the above embodiment, and 383 is a dichroic prism.

In the video projector of this embodiment, the white light emitted from the light source 370 is condensed by the parabolic mirror 371, passes through the heat ray cut filter 372, blocks the infrared rays, and only visible light is emitted. The light enters the dichroic mirror system. Then, first, blue light (wavelength of approximately 50 nm or less) is reflected by the blue reflecting dichroic mirror 373, and the other light (yellow light) is transmitted. The reflected blue light changes its direction by the reflection mirror 374 and enters the blue modulation light valve 378.

On the other hand, the light transmitted through the blue reflecting dichroic mirror 373 is reflected by the green reflecting dichroic mirror 3.
75, the green light (wavelength of about 500 to 600 nm) is reflected, and the other light, red light (about 600 nm)
nm or more) is transmitted. Dichroic mirror 3
The green light reflected at 75 is a green modulated light valve 379
Incident on. The red light transmitted through the dichroic mirror 375 changes its direction by the reflection mirrors 376 and 377 and enters the red modulation light valve 380.

The light valves 378, 379, 380 are
Blue, green, supplied from a video signal processing circuit (not shown)
The light that is driven by each of the red primary color signals and is incident on each light valve is modulated by each light valve and then combined by the dichroic prism 383. The dichroic prism 383 is formed such that the red reflection surface 381 and the blue reflection surface 382 are orthogonal to each other. Then, the color image synthesized by the dichroic prism 383 is enlarged and projected on a screen by the projection lens 384 and displayed.

The liquid crystal panel substrate of this embodiment has a high aperture ratio, and in the video projector using the liquid crystal panel using the same as a light valve, a bright and high-contrast display image can be obtained.

[0057]

As described above, according to the present invention, pixel electrodes are arrayed and formed in a matrix on a substrate, and TFTs are formed in correspondence with the respective pixel electrodes. A semiconductor layer (polysilicon layer) serving as an active layer of the thin film transistor in a liquid crystal panel substrate configured to apply a voltage to a pixel electrode;
In particular, since a sheet layer made of a conductive layer such as a polysilicon layer is formed below a region connected to the pixel electrode, a contact hole that penetrates the insulating film can be surely formed by dry etching. In addition, the sheet layer can prevent the contact hole from passing through the drain region, and the wet etching for a long time (1 minute or more) is not required. There is an effect that a contact hole having a small hole area can be formed.

Further, even when the pixel pitch is reduced with the increase in the definition of the liquid crystal panel, the aperture ratio can be sufficiently ensured, and a high aperture ratio can be obtained even in a liquid crystal panel having a small pixel pitch. Obtainable.

Further, according to the present invention, a liquid crystal panel substrate having the above-mentioned advantages can be obtained, so that a bright and high-contrast liquid crystal panel and a projection display device can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one embodiment (first half) of a method for manufacturing a liquid crystal panel substrate according to the present invention in the order of steps.

FIG. 2 is a sectional view showing one embodiment (second half) of the method for manufacturing a liquid crystal panel substrate according to the present invention in the order of steps.

FIG. 3 is a plan layout view of a first embodiment of a liquid crystal panel substrate to which the present invention is applied.

FIG. 4 is an enlarged plan view of a main part showing a difference in size of a contact hole between a liquid crystal panel substrate to which the first embodiment is applied and a liquid crystal panel substrate to which a conventional method is applied.

FIG. 5 is a plan layout view of a liquid crystal panel substrate according to a second embodiment of the present invention.

FIG. 6 is a plan layout view of a liquid crystal panel substrate according to a third embodiment of the present invention.

FIG. 7 is an enlarged plan view of a main part showing a difference in size of a contact hole between a liquid crystal panel substrate to which the third embodiment is applied and a liquid crystal panel substrate to which a conventional method is applied.

FIG. 8 is a sectional view of a liquid crystal panel substrate according to a fourth embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a configuration example of a liquid crystal panel using the liquid crystal panel substrate according to the present invention.

FIG. 10 is a table showing the results of examining the effect of the diameter of a drain-side contact hole on the aperture ratio of a liquid crystal panel in relation to the pixel pitch.

FIG. 11 is a graph showing the result of examining the effect of the diameter of a drain-side contact hole on the aperture ratio of a liquid crystal panel in relation to the pixel pitch.

FIG. 12 is a block diagram showing a system configuration example of a liquid crystal panel substrate suitable for applying the present invention.

FIG. 13 is a schematic configuration diagram of a video projector as an example of a projection display device in which an LCD using the liquid crystal panel substrate of the embodiment is applied as a light valve.

FIG. 14 is a plan layout view showing an example of a conventional liquid crystal panel substrate.

FIG. 15 is a cross-sectional view of an example of a conventional liquid crystal panel substrate.

[Explanation of symbols]

Reference Signs List 1 substrate 2 sheet layer 3 polysilicon layer (active layer) 4 gate insulating film 5 gate electrode 6 first interlayer insulating film 7a source side contact hole 7b drain side contact hole (pixel electrode contact hole) 8 source electrode 9 second layer Insulating film 10 Pixel electrode 11 Scanning line 12 Data line 13 Black matrix 14 Light shielding film 15 Insulating film 16 Polarizing plate 30 Liquid crystal panel 33 Counter electrode 35 Counter substrate 36 Sealing material 37 Liquid crystal 50, 60 Peripheral circuit 51 X shift register 52 Sampling switch 54 to 56 Video signal line 61 Y shift register 70 Pad 72 to 78 External terminal 90 Pixel 91 Pixel driving TFT 370 Lamp 373, 375, 376 Dichroic mirror 374, 377 Reflection mirror 378, 379, 380 Light valve 3 83 Dichroic prism 384 Projection lens

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/336 H01L 29/78 619B

Claims (13)

[Claims] 1. A configuration in which pixel electrodes are arranged in a matrix on a substrate, and thin film transistors are formed corresponding to the respective pixel electrodes, and a voltage is applied to the pixel electrodes via the thin film transistors. The liquid crystal panel substrate according to claim 1, wherein a conductive sheet layer is provided at least below a connection region of the semiconductor layer serving as an active layer of the thin film transistor and the pixel electrode. 2. The liquid crystal panel according to claim 1, wherein a light-shielding film separated from the sheet layer is formed at least below a channel region of a semiconductor layer serving as an active layer of the thin film transistor. Substrate. 3. The light-shielding film according to claim 1, wherein the sheet layer and the light-shielding film are formed of the same material, and an insulating film is formed between the light-shielding film and the semiconductor layer.
Or the liquid crystal panel substrate according to 2. 4. The semiconductor device according to claim 1, wherein at least a portion serving as a channel region of the semiconductor layer serving as an active layer of the thin film transistor is disposed below a signal line for transmitting an image signal to a source region of the transistor. 4. The liquid crystal panel substrate according to 1, 2, or 3. 5. A pixel provided on the substrate has a pitch in at least one direction of 50 μm or less, and the outermost diameter of a contact hole formed in an insulating film above the corresponding drain region is 4 μm or less. The liquid crystal panel substrate according to claim 1, 2, 3, or 4, wherein: 6. A structure in which pixel electrodes are formed in a matrix on a substrate, and thin film transistors are formed corresponding to the respective pixel electrodes, and a voltage is applied to the pixel electrodes via the thin film transistors. Forming a conductive sheet layer in advance in at least a region of a semiconductor layer serving as an active layer of the thin film transistor below a region connected to the pixel electrode; Forming the semiconductor layer, and after forming an insulating film on the semiconductor layer, forming a contact hole in the insulating film in order to connect the semiconductor layer and the pixel electrode, The step of forming the contact hole is performed by dry etching, and the amount of the etching is controlled by time. Method of manufacturing a substrate for a liquid crystal panel, characterized in that so as to set such conditions the over-etching in consideration of Minobaratsuki. 7. The sheet layer has a thickness of 500 to 1500.
7. The method according to claim 6, wherein the thickness is in the range of 800 to 1200 angstroms. 8. The method according to claim 6, wherein the sheet layer is formed of a polysilicon layer. 9. The method according to claim 6, wherein the dry etching is reactive ion etching, chemical dry etching, or high-density plasma etching. 10. Before the step of forming the sheet layer,
10. The liquid crystal panel according to claim 6, further comprising a step of forming a light-shielding film separated from the sheet layer at least below a channel region of a semiconductor layer serving as an active layer of the thin film transistor. Method of manufacturing substrates. 11. The etching step comprises: CHF3 and S
Using a mixed gas of F6 and He, 1600-1700mTo
7. The method according to claim 6, wherein the dry etching is performed at a pressure of rr and a power of 100 to 500 W. 12. The liquid crystal panel substrate according to claim 1, 2, 3, 4, or 5, and a transparent substrate having a counter electrode are arranged at an appropriate distance, and the liquid crystal panel substrate is A liquid crystal panel, wherein a liquid crystal is sealed in a gap with the transparent substrate. 13. A light source, a liquid crystal panel configured to modulate and transmit or reflect light from the light source, and projection for condensing and modulating the light modulated by these liquid crystal panels. A projection display device comprising: an optical unit.