JPH10163899A - Radio receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a straight receiving method that has an excellent selectivity characteristic. SOLUTION: An AM radio receiver consists of a straight tuning part 2, a detection circuit, a low frequency amplifier and a speaker. Inside the part 2, plural sampling tuning circuits 11a to 11c are cascaded and reference clocks which respectively have a different frequency are supplied to each sampling tuning circuit 11a to 11c. These reference clocks are controlled so that frequency difference may always be constant even when a frequency changes. In this way, sampling tuning circuits are cascaded, the bandwidth of the part 2 is widened, also, a Q can be set to be high enough to tune in a reference clock and to perform digital tuning, and tuning can have an excellent selectivity characteristic.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio receiver of a straight reception system for amplifying a signal received by an antenna without converting it into an intermediate frequency signal and performing detection processing.

[0002]

2. Description of the Related Art There are two types of reception methods for radio receivers: a straight reception method in which a signal received by an antenna is tuned and detected without frequency conversion, and a signal received by an antenna is converted into an intermediate frequency signal having a constant frequency. After that, there is a superheterodyne method in which tuning and detection processing are performed. In the straight reception system, since a high-frequency signal is amplified as it is, self-oscillation is caused by coupling between circuits and the like, and the operation tends to be unstable. Also, since the tuning frequency of the tuning circuit must be changed according to the reception frequency, the Q of the tuning circuit cannot be set too high due to the circuit configuration, and the frequency selectivity characteristic deteriorates.

On the other hand, in the superheterodyne method, since the signal is once converted into a low-frequency intermediate frequency signal, there is no possibility of oscillation even if the received signal is greatly amplified.
In addition, since the intermediate frequency is always constant irrespective of the reception frequency, Q of the tuning circuit can be set sufficiently high, and the frequency selectivity characteristics are improved. For this reason, recently, superheterodyne radio receivers have become the mainstream.

[0004]

However, in the superheterodyne method, when a signal of frequency f1 is received, it is converted to an intermediate frequency (f0-f1) using a local oscillation signal of frequency f0. (F0
If a broadcast wave of (+ f1) exists, interference occurs with the broadcast wave. If the local oscillation signal contains a harmonic component, so-called whistle interference may occur. As described above, as long as the superheterodyne method is adopted, there is a certain limit in improving the reception characteristics. Further, the superheterodyne method requires a process of once converting to an intermediate frequency, and has a problem that the configuration of the receiver is complicated.

The present invention has been made in view of the above points, and an object of the present invention is to provide a radio receiver of a straight reception system having excellent selectivity characteristics.

[0006]

According to a first aspect of the present invention, there is provided a radio receiver in which sampling tuning circuits are connected in cascade, and the frequency of a reference clock supplied to each sampling tuning circuit is set to a predetermined value. Since the shifts are made one by one, the bandwidth can be set wide, and the bandwidth does not change even if the tuning frequency is changed.

In the radio receiver according to the second aspect, since each sampling tuning circuit is cascaded with an amplifier interposed therebetween, a desired bandwidth can be obtained by adjusting the gain of the amplifier.

According to a third aspect of the present invention, there is provided a radio receiver having a simple configuration in which an antenna is connected to an input side of a high-frequency amplifier circuit in which a sampling tuning circuit and an amplifier are cascaded, and a detection circuit is connected to an output side. Can be configured. Also,
Since no adjustment part is required and the number of components is reduced, a receiver excellent in reliability, maintainability and cost performance can be obtained.

According to a fourth aspect of the present invention, the number of connection stages of the sampling tuning circuit and the frequency of the reference clock are set so as to obtain an optimum bandwidth for receiving AM broadcast.

According to a fifth aspect of the present invention, the number of connection stages of the sampling tuning circuit and the frequency of the reference clock are set so as to obtain an optimum bandwidth for receiving FM broadcast.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a radio receiver according to the present invention will be specifically described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of a radio receiver. The radio receiver shown in FIG. 1 is a receiver of a straight reception system for receiving a desired AM broadcast wave without converting it into an intermediate frequency, and includes an antenna 1, a straight tuning unit 2, a detection circuit 3, a low frequency It includes an amplifier circuit 4 and a speaker 5.

The straight tuning section 2 selectively amplifies only broadcast waves in a frequency band desired to be selected from broadcast waves received by the antenna 1. The detailed configuration of the straight tuning section 2 will be described later. The detection circuit 3 detects the modulated wave signal output from the straight tuning unit 2 and extracts a low frequency signal. The extracted low-frequency signal is amplified by the low-frequency amplifier circuit 4 and then output from the speaker 5 as sound.

FIG. 2 is a block diagram showing a detailed configuration of the straight tuning section 2. As shown in FIG. As shown, the straight tuning section 2 includes sampling tuning circuits 11a to 11c, amplifiers 12a to 12c, and clock generating circuits 13a to 13c.
And a control circuit 14, and each of the sampling and tuning circuits 11a to 11c includes an amplifier 12a to 12c, respectively.
They are connected in cascade with c in between. Clock generation circuit 13
a to 13c are sampling tuning circuits 11a to 1 respectively.
1c, each sampling tuning circuit 11
Reference clocks having different frequencies are supplied to a to 11c.

FIG. 3 shows sampling tuning circuits 11a to 11a.
It is a circuit diagram which shows the detailed structure of 1c. As shown in the figure, the sampling tuning circuits 11a to 11c include a ring counter 401 having 16 outputs and a ring counter 40.
A MOS transistor 402 connected to each output of
It is configured to include a capacitor 403 connected to the drain terminal of each MOS transistor 402, and a resistor 404 and a capacitor 405 connected in parallel.

FIG. 4 is a waveform diagram showing a change in the output of the ring counter 401. As shown in the figure, the ring counter 401 outputs a pulse once every 16 periods of the reference clock output from the clock generation circuits 13a to 13c in FIG. More specifically, the ring counter 401
Outputs a pulse having a period 16 times the reference clock from each output terminal. Also, the phase of the pulse output from each output terminal is shifted by one reference clock.

Each output of the ring counter 401 is input to the gate terminal of the corresponding MOS transistor 402, as shown in FIG. Since the phases of the pulses output from the respective output terminals of the ring counter 401 are shifted from each other, the timing at which the MOS transistor 402 is turned on is also different, and the capacitor 403 connected to the MOS transistor 402 turns on the MOS transistor 402. -Repeat charge / discharge according to turning off.

For example, when a signal having the same frequency as the pulse signal output from the ring counter 401, that is, a signal having a cycle 16 times as long as the reference clock is input to the sampling tuning circuits 11a to 11c, the signal shown in FIG. The voltage at the point changes stepwise as shown in FIG. On the other hand, when a signal having a frequency different from the frequency of the pulse signal is input to the sampling tuning circuits 11a to 11c, the voltage at the point a in FIG. 3 changes in each cycle, and the potential at the point a eventually becomes zero. It converges to the potential. Therefore, the sampling tuning circuits 11a to 11c shown in FIG.
Only frequency components equal to the frequency of the pulse signal output from 1 can be extracted.

Since the line at point a in FIG. 3 has a high impedance, if it is directly connected to a subsequent circuit having a low input impedance, the output waveform may not be able to be taken out as it is. For this reason, it is desirable that the line at the point a is once received by the FET 406 as shown in FIG. 3, and the source terminal of the FET 406 is connected to a subsequent circuit. In addition,
The capacitor 407 in FIG. 3 is for cutting the DC component of the input signal, and the resistors 408 and 409 are FE
This is for giving an appropriate bias to T406.

As described above, the sampling tuning circuits 11a to 11c whose detailed configuration is shown in FIG.
Since the circuit is composed of only components that are easily converted to semiconductors, such as the MOS transistor 01 and the MOS transistor 402, the entire circuit can be easily formed into a chip. Also, according to the circuit of FIG.
By increasing the number of outputs of the ring counter 401, the number of samplings in one cycle can be easily increased, thereby improving the tuning accuracy.

The sampling tuning circuits 11a to 11
Q of c is represented by Q = πfCRN (C is the capacitance of the capacitor 403, R is the resistance value of the resistor 404, and N is the number of samplings).
Becomes larger, so that even if the tuning frequency is changed, the bandwidth Δf
= F / Q can be made constant, and tuning can be performed with the same accuracy over a wide range of frequencies.

In the sampling tuning circuits 11a to 11c shown in FIG. 3, a CMOS transistor 402 'may be used instead of the MOS transistor 402 as shown in FIG. The use of the CMOS transistor 402 'makes the transistor less susceptible to parasitic capacitance. Further, since all the elements constituting the sampling tuning circuits 11a to 11c can be formed by a CMOS process,
The process for chip formation can be simplified.

The straight tuning section 2 shown in FIG. 1 is composed of sampling tuning circuits 11a to 11c whose detailed configuration is shown in FIG.
Are cascaded in three stages with the amplifiers 12a to 12c interposed therebetween, and the frequency of the reference clock input to each of the sampling tuning circuits 11a to 11c is slightly shifted.

For example, when the tuning frequency is f0 kHz, the frequency of each reference clock output from each of the clock generation circuits 13a to 13c is 16 × (f0 kHz).
-Δf) kHz, 16 × f0 kHz, 16 × (f0 + Δ
f) Set to kHz. The frequency characteristics of the sampling tuning circuits 11a to 11c in this case are shown in FIG.
(A) to (c). In FIG. 6,
The horizontal axis indicates the frequency f, and the vertical axis indicates the signal intensity I.

Therefore, the modulated wave signal from the antenna 1 is first input to the sampling tuning circuit 11a (f
0-Δf) A component having a center frequency of kHz is extracted,
Next, after the signal is once amplified by the amplifier 12a, it is input to the sampling tuning circuit 11b to extract a component having a center frequency of f0 kHz, and is then amplified by the amplifier 12b and then input to the sampling tuning circuit 11c ((f0 +
Δf) A component having a center frequency of kHz is extracted. As a result, the frequency characteristic of the signal output from the straight tuning unit 2 is as shown in FIG.

When receiving an AM broadcast, it is desirable to set the above-mentioned Δf to about 1 kHz, so that the above-mentioned bandwidth is always obtained even if the tuning frequency is changed.
The control circuit 14 adjusts the frequency of the reference clock output from each of the clock generation circuits 13a to 13c.

As described above, the straight tuning section 2 shown in FIG.
Since the three sampling tuning circuits 11a to 11c are cascaded and the tuning frequencies of the sampling tuning circuits 11a to 11c are slightly shifted, the bandwidth can be wider than that in the case where only one sampling tuning circuit is provided. It is possible to set an optimum bandwidth for an AM radio receiver. Therefore, the antenna 1 is connected to the input end of the straight tuning section 2.
Can realize an AM radio receiver with a simple configuration in which the detection circuit 3 is connected to the output end, and does not include a circuit such as an LC resonance circuit that tends to cause variations in electrical characteristics, thereby reducing component costs. A radio receiver that does not require adjustment, does not require adjustment, and is excellent in reliability and maintainability can be obtained. Also,
The frequencies of the reference clocks supplied to the sampling tuning circuits 11a to 11c are shifted by the same amount from each other, and the shift amount does not change even if the tuning frequency is changed. Therefore, the bandwidth is always controlled irrespective of the tuning frequency. it can. Further, as shown in the circuit of FIG. 3, the sampling tuning circuits 11a to 11c can accurately extract only the same frequency component as the pulse signal output from the ring counter 401.
A radio receiver having excellent selectivity characteristics can be obtained.

FIG. 7 shows each of the sampling and tuning circuits 11a to 11a.
Clock generating circuits 13a provided corresponding to the clocks 11c
It is a block diagram which shows the detailed structure of-13c. As illustrated, the clock generation circuits 13a to 13c include a voltage controlled oscillator 501, a programmable counter 502, a reference oscillator 503, a phase comparator 504, and a low-pass filter 505. Voltage controlled oscillator 5
01 outputs a reference clock, and the programmable counter 502 divides the frequency of the reference clock by a preset division ratio. The phase comparator 504 includes the programmable counter 50
2 is compared with the reference oscillation signal from the reference oscillator 503. As a result, a voltage corresponding to the phase difference is applied to the voltage controlled oscillator 501 via the low pass filter 505. The voltage controlled oscillator 501 includes a low-pass filter 5
The frequency of the reference clock is changed in accordance with the output voltage 05, and an oscillation operation is performed such that the output reference clock is synchronized with the reference oscillation signal.

Each of the clock generating circuits 13a to 13c
2, a control circuit 14 is connected, and a control signal output from the control circuit 14 is input to a programmable counter 502 inside each of the clock generation circuits 13a to 13c, and a frequency division ratio of each of the control signals is determined. Is set. Thereby, the reference clocks output from the clock generation circuits 13a to 13c are controlled so as to always change by the same amount.

For example, when an 954 kHz AM broadcast wave is received, the frequency division ratio of each programmable counter 502 in the clock generation circuits 13a to 13c is 9
53, 954, and 955. On the other hand, the frequency of the reference oscillation signal output from the reference oscillator 503 is set to 16 kHz. As a result, the frequencies of the reference clocks output from the clock generation circuits 13a to 13c are respectively 953 kHz × 16 = 15.248 MH.
z, 954 kHz x 16 = 15.264 MHz, 95
kHz × 16 = 15.280 MHz. These reference clocks are respectively input to the sampling tuning circuits 11a to 11c shown in FIG. 2 and are divided by 16, and as a result, selective tuning is performed within a range of ± 1 kHz with a center frequency of 954 kHz.

As described above, each sampling tuning circuit 11
clock generation circuits 13a to 13c corresponding to
Since c is provided so that the frequency of the reference clock output from each of the clock generation circuits 13a to 13c can be arbitrarily changed, the tunable frequency range is widened. In addition, since each of the clock generation circuits 13a to 13c is controlled by the control circuit 14, each of the sampling and tuning circuits 11a to 11c is controlled.
The tuning frequency of c can be simultaneously and accurately changed by the same amount. Even if the tuning frequency is changed, the bandwidth does not change, and stable tuning processing can always be performed with the same accuracy.

In the above embodiment, an example of a radio receiver capable of receiving an AM broadcast has been described.
The present invention is also applicable when receiving a broadcast. FIG. 8 is a block diagram of one embodiment of the FM radio receiver. The straight tuning section 2 'is configured in the same manner as in FIGS. 1 and 2, and the output of the straight tuning section 2' is input to the FM detection circuit 3 '. The FM detection circuit 3 'converts the FM modulated wave signal selected by the straight tuning section 2' into a stereo composite signal,
This stereo composite signal is input to the stereo demodulation circuit 6 and separated into an L signal and an R signal. These L signal and R signal are separately input to the de-emphasis circuits 7L and 7R, respectively, and after attenuating the high frequency part to improve the SN ratio,
Sound is output from the speakers 9L and 9R via the low-frequency amplifier circuits 8L and 8R.

Since the frequency of the FM broadcast wave is higher than that of the AM broadcast wave, the clock generation circuits 13a to 13b shown in FIG.
The frequency of the reference clock output from 13c and the frequency difference between each of the reference clocks need to be set to optimal values for receiving the FM broadcast. For example, it is desirable that the bandwidth of the straight tuning section 2 is set to about 150 to 200 kHz.

As shown in FIG. 2, when an AM broadcast is received, it is most preferable to cascade three stages of sampling and tuning circuits in consideration of the bandwidth and Q. Four or more stages may be used. In the above-described example, as shown in FIG.
Although the reference oscillator 503 is provided for each of a to 13c,
Since each reference oscillator 503 performs an oscillation operation at the same frequency, a common reference oscillator may be provided and shared.

[0035]

As described above in detail, according to the present invention, tuning is performed by cascading a plurality of sampling tuning circuits, so that the bandwidth is wider than when only one sampling tuning circuit is provided. be able to. Further, the conventional straight receiver system has a problem that Q cannot be set too high due to the variable tuning frequency. However, the present invention synchronizes digitally in synchronization with a reference clock. Can be set sufficiently high, and a radio receiver having excellent selectivity characteristics can be obtained. Furthermore, since the frequency of the reference clock input to each of the cascade-connected sampling tuning circuits is variably controlled in conjunction with each other, the bandwidth can be constantly controlled even when the tuning frequency is changed.

Unlike the superheterodyne system, since the conversion to the intermediate frequency is not performed, no trouble such as image interference or whistle interference occurs, and the circuit configuration of the entire receiver is different from that of the superheterodyne system. Can be simplified, and the cost of parts can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a radio receiver capable of receiving an AM broadcast.

FIG. 2 is a block diagram showing a detailed configuration of a straight tuning unit.

FIG. 3 is a circuit diagram showing a detailed configuration of a sampling tuning circuit.

FIG. 4 is a waveform diagram showing a change in output of a ring counter.

FIG. 5 is a CM used inside a sampling tuning circuit.
FIG. 13 illustrates an example of a transistor having an OS configuration.

6A to 6C are frequency characteristic diagrams of each sampling tuning circuit, and FIG. 6D is a frequency characteristic diagram of a straight tuning unit.

FIG. 7 is a block diagram illustrating a detailed configuration of a clock generation circuit.

FIG. 8 is a block diagram of an embodiment of a radio receiver capable of receiving FM broadcast.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Antenna 2 Straight tuning part 3 Detection circuit 4 Low frequency amplification circuit 5 Speaker 11a-11c Sampling tuning circuit 12a-12c Amplification circuit 13a-13c Clock generation circuit 14 Control circuit

Claims (5)

[Claims] A radio receiver for extracting only a frequency component desired to be tuned from a received signal received by an antenna and performing a detection process, wherein the radio receiver has a period that is an integral multiple of a reference clock and is synchronized with the reference clock. A plurality of cascaded sampling tuning circuits that extract only the same frequency components as the pulse signal from the received signal based on the result of sampling the received signal with the pulse signal obtained, A plurality of clock generation circuits provided correspondingly and supplying the reference clock to each sampling tuning circuit, wherein the frequency of the reference clock output from the clock generation circuit is shifted by a predetermined amount. Radio receiver. 2. The radio receiver according to claim 1, wherein each of the sampling tuning circuits is cascaded via an amplifier. 3. The high-frequency amplifier circuit according to claim 2, wherein the sampling tuned circuit and the amplifier connected in cascade form a high-frequency amplifier circuit, the antenna is connected to the input side of the high-frequency amplifier circuit, and the detection circuit is connected to the output side. A radio receiver characterized by being connected. 4. The method according to claim 3, further comprising an AM detection circuit for converting the AM modulated wave signal into a signal before modulation, wherein the number of connection stages of the sampling tuning circuit and the number of connection stages of the sampling tuning circuit are increased so as to obtain a bandwidth capable of receiving AM broadcast. The frequency of the reference clock is set, and the output of the high frequency
A radio receiver characterized by inputting to a detection circuit. 5. An FM broadcast according to claim 1, further comprising: an FM detection circuit for converting the selected FM modulated wave signal into a stereo composite signal in which an L signal and an R signal are combined. The number of connection stages of the sampling tuning circuit and the frequency of the reference clock are set so as to obtain a bandwidth capable of receiving the signal.
A radio receiver characterized by inputting to a detection circuit.