JP3676527B2 - Radio receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a radio receiver including a sampling tuning circuit that extracts only the same frequency component as a reference clock.
[0002]
[Prior art]
A tuning circuit is provided inside the radio receiver so that only a desired frequency radio wave can be selected. However, since only one tuning circuit is provided and the frequency selectivity is not good and noise cannot be completely removed, a plurality of tuning circuits are often provided inside the receiver. For example, in a superheterodyne AM receiver, a tuning circuit is provided in each of an antenna input circuit, a high frequency amplifier circuit, and an intermediate frequency amplifier circuit.
[0003]
[Problems to be solved by the invention]
By the way, when the antenna of the AM radio receiver is configured with a rod antenna like a car radio, the capacity of the antenna changes depending on the length of the antenna, and even if a tuning circuit is provided in the antenna input circuit, I can't get along well. For this reason, there is also proposed a circuit in which a high frequency signal from an antenna is received by an FET without being tuned and amplified by an FET without providing a tuning circuit at the first stage of the radio receiver, and is tuned on the subsequent stage side of the FET. . However, when tuning is not performed at the first stage of the radio receiver, various frequency radio waves are input to the tuning circuit provided on the rear stage side, so that desired frequency components are disturbed and cannot be extracted with high accuracy.
[0004]
Also, conventional AM / FM combined radio receivers are generally provided with separate tuning circuits for AM reception and FM reception, respectively, which increases the number of parts and hinders downsizing of the receiver. It was.
[0005]
Further, the conventional tuning circuit is generally configured to include an LC resonance circuit, and Q is always kept constant even when the tuning frequency changes. For this reason, the higher the tuning frequency, the wider the bandwidth, and there is a problem that the bandwidth changes according to the tuning frequency.
[0006]
The present invention has been created in view of the above points, and an object of the present invention is to provide a radio equipped with a tuning circuit that can be tuned with high accuracy over a wide band and can be used for both AM reception and FM reception. To provide a receiver.
[0007]
[Means for Solving the Problems]
In order to solve the above-described problem, a radio receiver according to claim 1 is provided with a sampling tuning circuit inside the receiver, and a received signal received by an antenna is input to the sampling tuning circuit, and a reference clock is selected from the received signals. Only the same frequency component is extracted. As a result, a tuning circuit can be configured without using a conventional LC resonance circuit, and it is not affected by the capacitance of the antenna. Therefore, the antenna can be directly connected to the sampling tuning circuit.
[0008]
The radio receiver according to claim 2 is provided with a plurality of capacitors corresponding to each pulse signal output from the pulse generating circuit, and charges corresponding to the signal level of the received signal are synchronized with each pulse signal. accumulate. By connecting one end of these capacitors to each other and leading them to the output terminal, only the same frequency component as the pulse signal is extracted.
[0009]
The radio receiver according to claim 3 is a receiver capable of receiving AM broadcasting, and a sampling tuning circuit is directly connected to an antenna, for example, and only frequency components desired to be selected are extracted from received signals received by the antenna. To do.
[0010]
The radio receiver according to claim 4 is a superheterodyne receiver capable of receiving FM broadcasts, and outputs only the intermediate frequency (for example, 10.7 MHz) component by inputting the output of the FM front end unit to the sampling tuning circuit. Then, the output of the sampling tuning circuit is input to the FM detector.
[0011]
The radio receiver of claim 5 is a receiver capable of receiving AM broadcast and FM broadcast, and switches the input of the sampling tuning circuit depending on which one is received. Specifically, when receiving FM broadcasting, an FM intermediate frequency signal, which is a result of frequency conversion performed by the FM front end unit, is input to the sampling tuning circuit, and the sampling tuning circuit is used as an intermediate frequency filter. On the other hand, when receiving an AM broadcast, the received signal received by the antenna is input to the sampling tuning circuit as it is to tune the tuning to the desired frequency. Further, the frequency of the reference clock is fixed at the time of FM broadcast reception, and the frequency of the reference clock is changed in accordance with the frequency desired for channel selection at the time of AM broadcast reception.
[0012]
The radio receiver according to claim 6 is a superheterodyne receiver capable of receiving AM broadcasts, and a frequency of a reference clock input to a sampling tuning circuit and a frequency of a local oscillation signal used for conversion to an intermediate frequency. The tracking error, which has been a problem in the past, does not occur.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a radio receiver to which the present invention is applied will be specifically described with reference to the drawings.
[0014]
FIG. 1 is a block diagram of an embodiment of a radio receiver. As shown in the figure, the radio receiver of the present embodiment includes an FM receiver 1 that receives FM broadcasts and an AM receiver 2 that receives AM broadcasts. The FM receiver 1 includes a high frequency amplification circuit 101, a mixing circuit 102, a local oscillation circuit 103, a tuning circuit 104, an intermediate frequency amplification circuit 105, an FM detection circuit 106, a stereo demodulation circuit 107, de-emphasis circuits 108L and 108R, a low frequency Amplifying circuits 109L and 109R and speakers 110L and 110R are included. On the other hand, the AM receiver 2 includes a high frequency amplifier circuit 201, a mixing circuit 202, a local oscillator circuit 203, a channel selection circuit 204, an intermediate frequency amplifier circuit 205, an AM detector circuit 206, a low frequency amplifier circuit 207, and a speaker 208. It is configured.
[0015]
The radio receiver shown in FIG. 1 includes an antenna 3, a clock generation circuit 4, a sampling tuning circuit 5, and a tuning oscillation circuit 6, which are used in both the FM receiving unit 1 and the AM receiving unit 2. The
[0016]
Next, the configuration and operation of the FM receiver 1 and the AM receiver 2 will be described in detail.
[0017]
(1) Configuration and operation of FM receiver
The high frequency amplifier circuit 101 of the FM receiver 1 selectively amplifies broadcast waves in a specific band among broadcast waves received by the antenna 3. The mixing circuit 102, the local oscillation circuit 103, and the channel selection circuit 104 constitute a frequency converter, and a carrier wave signal having a frequency fc outputted from the high frequency amplifier circuit 101 and a local oscillation having a frequency fL outputted from the local oscillation circuit 103. The signal is mixed, frequency conversion is performed without changing the modulation content, and an intermediate frequency signal of fL -fc is output. When receiving FM broadcasting, the frequency of the intermediate frequency signal is set to 10.7 MHz, for example. This frequency is always fixed when receiving FM broadcasts.
[0018]
FIG. 2 is a block diagram showing the detailed configuration of the local oscillation circuit 103 and the channel selection circuit 104, and shows an example in which electronic tuning of the PLL frequency synthesizer system is performed. The reference oscillation signal output from the reference oscillator 301 is, for example, divided by 4 by the prescaler 302 and input to the phase comparator 303 in the local oscillation circuit 103. Further, the local oscillation signal output from the voltage controlled oscillation circuit (VCO) 304 in the local oscillation circuit 103 is input to the prescaler 305 and divided, for example, by 4, and then divided by the programmable counter 306 according to the channel selection frequency. The frequency is divided by the frequency ratio and input to the phase comparator 303. The phase comparator 303 compares the phase of the output of the prescaler 302 with the phase of the output of the programmable counter 306, and inputs a voltage corresponding to the phase difference to the voltage controlled oscillation circuit 304 via the low-pass filter 307.
[0019]
As described above, the local oscillation signal output from the voltage controlled oscillation circuit 304 is controlled to synchronize with the reference oscillation signal. The control circuit 308 sets a frequency division ratio in the programmable counter 306 and causes the display unit 309 to display various information such as a channel selection frequency.
[0020]
The output of the mixing circuit 102 shown in FIG. 1 is input to the switch SW1. The switch SW1 is set to the contact p side when receiving FM broadcasting, and is set to the contact q side when receiving AM broadcasting. Therefore, when receiving FM broadcast, the output of the mixing circuit 102 is input to the sampling tuning circuit 5. The sampling tuning circuit 5 extracts only the intermediate frequency component from the output of the mixing circuit 102.
[0021]
FIG. 3 is a circuit diagram showing a detailed configuration of the sampling tuning circuit 5. As shown in the figure, the sampling tuning circuit 5 includes a ring counter 401 having 16 outputs, a MOS transistor 402 connected to each output of the ring counter 401, and a capacitor 403 connected to the drain terminal of each MOS transistor 402. And a resistor 404 and a capacitor 405 connected in parallel.
[0022]
FIG. 4 is a waveform diagram showing changes in the output of the ring counter 401. As shown in the figure, the ring counter 401 outputs a pulse at a rate of once every 16 periods of the reference clock output from the clock generation circuit 4 of FIG. More specifically, the ring counter 401 outputs a pulse having a period 16 times the reference clock from each output terminal. Further, the phase of the pulse output from each output terminal is shifted by one clock of the reference clock.
[0023]
Each output of the ring counter 401 is input to the gate terminal of the corresponding MOS transistor 402 as shown in FIG. Since the phases of the pulses output from the respective output terminals of the ring counter 401 are shifted from each other, the timing when the MOS transistor 402 is turned on is also different, and the capacitor 403 connected to the MOS transistor 402・ Repeat charge and discharge according to turning off.
[0024]
For example, when a signal Vin having the same frequency as the signal obtained by dividing the reference clock by 16 is input to the sampling tuning circuit 5, the voltage at point a in FIG. 3 changes stepwise as shown in FIG. On the other hand, when a signal having a frequency different from the signal obtained by dividing the reference clock by 16 is input to the sampling tuning circuit 5, the voltage at the point a in FIG. It converges to zero potential. Thus, by configuring the sampling tuning circuit as shown in FIG. 3, only the frequency component equal to the output frequency of the ring counter 401, that is, 1/16 the frequency of the reference clock, can be extracted.
[0025]
Since the line at point a in FIG. 3 has a high impedance, the output waveform cannot be extracted as it is when directly connected to a subsequent circuit having a low input impedance. For this reason, it is desirable that the point a line is once received by the FET 406 as shown in FIG. 3, and the source terminal of the FET 406 is connected to the circuit of the subsequent stage. 3 is for cutting the DC component included in the output Vin of the mixing circuit 102, and the resistors 408 and 409 are for applying an appropriate bias to the FET 406.
[0026]
As described above, the sampling tuning circuit 5 is composed of only components that are easily semiconductorized, such as the ring counter 401 and the MOS transistor 402, so that the entire circuit can be easily formed into a chip. In the circuit of FIG. 3, the tuning accuracy can be easily increased by increasing the number of outputs of the ring counter 401 and increasing the number of samples in one cycle. Conversely, when high-precision tuning is not required, the number of samplings in one cycle may be reduced, and the circuit scale can be reduced by reducing the number of samplings.
[0027]
Further, since the sampling tuning circuit 5 shown in FIG. 3 is digitally tuned, it is not affected by the temperature characteristics of the component parts and can always be tuned with stable accuracy. Further, since there is no amplifier circuit, there is no possibility of oscillation.
[0028]
The reference clock input to the sampling tuning circuit 5 is generated by the clock generation circuit 4 shown in FIG. The clock generation circuit 4 includes a voltage controlled oscillation circuit (VCO) 451, a programmable counter (PC) 452, a reference oscillator 453, a phase comparator 454, and a low-pass filter (LPF) 455. The voltage controlled oscillation circuit 451 outputs a reference clock, and the programmable counter 452 divides the reference clock by a preset division ratio. The phase comparator 454 performs phase comparison between the output of the programmable counter 452 and the reference oscillation signal from the reference oscillator 453, and inputs a voltage corresponding to the phase difference to the voltage controlled oscillation circuit 451 via the low-pass filter 455. The voltage controlled oscillation circuit 451 changes the frequency of the reference clock according to the output voltage of the low pass filter 455, and controls the reference clock to be synchronized with the reference oscillation signal.
[0029]
As described above, by combining the clock generation circuit 4 and the sampling tuning circuit 5 in which the frequency division ratio of the programmable counter 452 can be arbitrarily set, the tuning frequency can be easily changed, and a desired tuning frequency can be set. It can be set accurately. Further, Q of the sampling tuning circuit 5 shown in FIG. 3 is expressed by Q = πfCRN (C is the capacitance of the capacitor 403, R is the resistance value of the resistor 404, and N is the number of samplings), and the frequency of the reference clock is high. Since Q increases, the bandwidth Δf = f / Q can always be kept constant even if the tuning frequency is changed, and tuning can be performed with the same accuracy over a wide range of frequencies.
[0030]
The 10.7 MHz intermediate frequency signal that has passed through the sampling tuning circuit 5 is amplified by the intermediate frequency amplification circuit 105 and then input to the FM detection circuit 106 as shown in FIG. The FM detection circuit 106 converts the intermediate frequency signal into a stereo composite signal before modulation. This stereo composite signal is a combination of an L signal component, an R signal component, and a 19 kHz pilot signal. This stereo composite signal is input to the stereo demodulation circuit 107 and separated and reproduced into an L signal and an R signal.
[0031]
FIG. 5 is a block diagram showing a detailed configuration of the stereo demodulation circuit 107. As shown in the figure, the stereo demodulation circuit 107 includes a preamplifier 501, a phase comparator 502, a low-pass filter 503, a DC amplifier 504, frequency dividers 505 to 508, and a switching circuit 509. The output of the DC amplifier 504 is input to the tuning oscillation circuit 6. As will be described later, the tuned oscillation circuit 6 oscillates at a predetermined frequency, for example, 456 kHz, and the oscillation output is input to the frequency divider 505. The frequency dividers 505 to 507 divide the output of the tuning oscillation circuit 6 to generate a 38 kHz sine wave signal, and the frequency divider 508 further divides the frequency by 2 to generate a 19 kHz sine wave signal. The phase comparator 502 compares the phase of the pilot signal included in the stereo composite signal with the output of the frequency divider 508, and outputs a voltage corresponding to the phase difference. This output is input to the DC amplifier 504 via the low pass filter 503.
[0032]
6 is an example of a signal waveform diagram of each part in the stereo demodulation circuit 107. FIG. 6A is a waveform of a stereo composite signal input to the preamplifier 501, and FIG. 6B is an output of the frequency divider 507. 6C is a waveform of a signal obtained by shifting the phase of the output of the frequency divider 507 by a half cycle, FIG. 6D is a waveform of an L signal output from the switching circuit 509, and FIG. The waveform of the R signal output from the circuit 509 is shown.
[0033]
As shown in FIG. 6A, the stereo composite signal input to the stereo demodulation circuit 107 is obtained by modulating the L signal and the R signal with a 38 kHz subcarrier. For this reason, the 38 kHz switching signal is generated by the frequency dividers 505 to 507 in the stereo demodulation circuit 107, and the stereo composite signal is captured in synchronization with the generated switching signal. Thus, the L signal and the R signal can be extracted. In FIGS. 6D and 6E, the L signal is represented by a sine wave and the R signal is represented by a rectangular wave in order to simplify the description.
[0034]
FIG. 7 is a principle diagram for explaining the operating principle of a GIC (Generalized Impedance Converter) included in the tuned oscillation circuit 6 shown in FIG. As shown in the figure, the GIC 600 is composed of two operational amplifiers 601 and 602 and five impedances Z1 to Z5, and the impedance Z between 1-1 'shown in the figure is expressed by equation (1). .
[0035]
Z = (Z1, Z3, Z5) / (Z2, Z4) (1)
By assigning a capacitor to one of the impedances Z2 and Z4 and a resistance to the other impedances, the circuit of FIG. 7 equivalently exhibits the same property as the inductance.
[0036]
8 is a circuit diagram showing a detailed configuration of the tuning oscillation circuit 6 of FIG. 1, and FIG. 9 is an equivalent circuit diagram of FIG. As shown in FIG. 8, an FET 606 is connected between resistors 605 and 607. By controlling the gate voltage of the FET 606, the resistance value between the drain and source of the FET 606 is variably controlled. A switch SW2 shown in FIG. 1 is connected to the gate terminal of the FET 606. The switch SW2 is set to the contact r side when receiving FM broadcast, and is set to the contact s side when receiving AM broadcast. The line on the contact r side is connected to a DC amplifier 504 inside the stereo demodulation circuit 107 as shown in FIG. 5, and the tuned oscillation circuit 6 can change the oscillation frequency according to the output of the DC amplifier 504 when receiving FM broadcasting. Control.
[0037]
In addition, an equivalent parallel resonant circuit is configured by connecting a capacitor 608 in parallel with the GIC 600, and an input resistor 610 is connected to one end of the GIC 600 and the capacitor 608 via an FET 609. A switch SW3 is connected to the gate terminal of the FET 609. This switch SW3 is set to the contact t side when receiving FM broadcasts, and is set to the contact u side when receiving AM broadcasts.
[0038]
For example, when an n-channel-enhancement type MOSFET is used as the FET 609, the FET 609 is cut off when the gate terminal is set to a low level, and the resistance value of the input resistor 610 of the tuned oscillation circuit 6 shown in FIG. Become infinite.
[0039]
Incidentally, Q of the tuning oscillation circuit 6 shown in FIG.
[0040]
Q = R / (ωL) (2)
Here, R represents the resistance value of the input resistor 610, and L represents the inductance of the GIC 600. In order to oscillate the tuned oscillation circuit 6, it is necessary to set Q shown in the equation (2) to a predetermined value or more. Therefore, when the switch SW3 shown in FIG. 8 is set to the contact t side and the resistance value of the input resistor 610 is infinite, Q also becomes infinite, and the tuned oscillation circuit 6 stably oscillates. Therefore, by controlling the gate voltage of the FET 606 in this state, the tuning oscillation circuit 6 functions as a voltage-controlled oscillation circuit when receiving FM broadcasting.
[0041]
In the tuning oscillation circuit 5 shown in FIG. 8, the resistance value of the input resistor 610 is apparently changed by turning on / off the FET 609. Instead of providing the FET 609, a variable resistor is used as the input resistor 610. The resistance value may be adjusted.
[0042]
Further, as shown in FIG. 1, a switch SW4 is connected to the output Vout of the tuning oscillation circuit 6, and this switch SW4 is set to the contact point v side when receiving FM broadcast. Therefore, the output of the tuning oscillation circuit 6 is input to the frequency dividing circuit 505 in the stereo demodulation circuit 107 shown in FIG. 5 through the contact point v of the switch SW4.
[0043]
The L signal and the R signal separated and reproduced by the stereo demodulation circuit 107 are separately input to the de-emphasis circuits 108L and 108R, respectively, as shown in FIG. The sound is output from the speakers 110L and 110R via the low-frequency amplifier circuits 109L and 109R.
[0044]
(2) Configuration and operation of AM receiver
When receiving the AM broadcast, the switch SW1 shown in FIG. 1 is set to the contact q side. Therefore, the received signal received by the antenna 3 is input to the sampling tuning circuit 5 via the switch SW1. As described above, the sampling tuning circuit 5 extracts only the same frequency component as the reference clock from the received signal. When receiving an FM broadcast, the frequency of the reference clock output from the clock generation circuit 4 is always set to be fixed. However, when receiving an AM broadcast, the frequency of the reference clock depends on the frequency to be selected. Need to change. More specifically, at the time of AM reception, the frequency of the reference clock is set to a frequency that is 16 times the frequency for which tuning is desired (when the sampling number N is “16”).
[0045]
The output of the sampling tuning circuit 5 is input to a frequency converter including a mixing circuit 202, a local oscillation circuit 203, and a channel selection circuit 204, and is converted into an intermediate frequency signal of 450 kHz, for example. The local oscillation circuit 203 is configured in the same manner as the local oscillation circuit 103 of the FM receiver 1, and a local oscillation signal output from a voltage controlled oscillation circuit (VCO) (not shown) is a reference output from a reference oscillator (not shown). Performs processing to synchronize with the oscillation signal. The channel selection circuit 204 performs channel selection in the AM broadcast frequency range (for example, 530 to 1700 kHz).
[0046]
Note that the tuning frequency of the sampling tuning circuit 5 and the oscillation frequency of the local oscillation signal change in conjunction with each other. For example, when receiving a broadcast wave of the frequency f, the tuning frequency of the sampling tuning circuit 5 is set to f, The oscillation frequency of the local oscillation signal is set to, for example, f + 450 kHz.
[0047]
The intermediate frequency signal output from the mixing circuit 202 is input to the tuning oscillation circuit 6 shown in detail in FIG. When receiving the AM broadcast, the switch SW3 shown in FIG. 8 is set to the contact u side, the FET 609 is turned on, and the intermediate frequency signal from the mixing circuit 202 is applied to one end of the resistor 603 via the input resistor 610. The switch SW2 is set on the contact s side, and a voltage determined by the voltage dividing ratio of the resistors 7 and 8 is applied to the gate terminal of the FET 606. Therefore, by adjusting the voltage dividing ratio of the resistors 7 and 8 in advance, the tuning oscillation circuit 6 shown in FIG. 8 extracts only the intermediate frequency signal of 450 kHz from the signal input via the FET 609. Perform the action.
[0048]
When receiving the AM broadcast, the switch SW4 shown in FIG. 1 is set to the contact w side, and the signal passing through the tuning oscillation circuit 6 is input to the intermediate frequency amplifier circuit 205 via the contact w of the switch SW4 to adjust the gain. Is input to the AM detection circuit 206. The AM detection circuit 206 converts the intermediate frequency signal into a low frequency signal using a diode or the like, and the converted low frequency signal is amplified by the low frequency amplification circuit 207 and output from the speaker 208 as sound.
[0049]
As described above, in this embodiment, the AM broadcast wave is selectively tuned using the sampling tuning circuit 5 and is not tuned using the conventional LC resonance circuit. I do not receive it. Therefore, it is possible to connect the rod antenna directly to the sampling tuning circuit 5 as in a car radio or the like, and there is a possibility that unnecessary jamming radio waves may be mixed in the downstream circuit such as the frequency converter and the intermediate frequency amplifier circuit 205. Disappear. When receiving an AM broadcast, the PLL control changes the tuning frequency of the sampling tuning circuit 5, that is, the frequency of the reference clock and the frequency of the local oscillation signal output from the local oscillation circuit 203 in an interlocked manner. The frequency of the intermediate frequency signal output from the mixing circuit 202 can always be kept constant. Therefore, the tracking error, which has been a problem in the past, does not occur.
[0050]
In this embodiment, the sampling tuning circuit 5 is used as an intermediate frequency filter when receiving FM broadcasts, and is used as a first stage selective tuning circuit when receiving AM broadcasts. Therefore, an intermediate frequency filter and a selective tuning circuit are separately provided. There is no need. Similarly, the tuning oscillation circuit 6 is used as a voltage-controlled oscillation circuit for stereo demodulation when receiving FM broadcasts, and is used as an intermediate frequency filter when receiving AM broadcasts. Therefore, a voltage-controlled oscillation circuit and an intermediate frequency filter are provided separately. This eliminates the need to reduce the number of components and reduce the size of the receiver.
[0051]
In the embodiment described above, the configuration of the AM / FM combined radio receiver is shown. However, the present invention can also be applied to an AM dedicated radio receiver or an FM dedicated radio receiver. For example, in the case of an AM dedicated radio receiver, the FM receiver 1 shown in FIG. 1 may be omitted, and one end of the resistor 10 and the capacitor 11 connected in parallel in FIG. 1 may be directly connected to the sampling tuning circuit 5. On the other hand, in the case of an FM dedicated radio receiver, the AM receiver 2 shown in FIG. 1 may be omitted, and the output of the mixing circuit 102 of FIG. Further, since the frequency of the reference clock output from the clock generation circuit 4 is always constant during FM reception, a frequency divider having a fixed frequency division ratio may be used instead of the programmable counter 452.
[0052]
In the above-described embodiment, an example of a superheterodyne radio receiver has been described. However, the present invention can also be applied to radio receivers other than the superheterodyne radio receiver. For example, after the FM broadcast wave received by the antenna 3 is input to the sampling tuning circuit 5 without being converted into an intermediate frequency signal, selective tuning processing is performed, and after detection processing is performed based on the output of the sampling tuning circuit 5, When the stereo demodulated signal obtained by detection is separated and reproduced into an L signal and an R signal, the tuned oscillation circuit 6 shown in FIG. 1 may be used. Alternatively, the AM broadcast wave received by the antenna 3 may be selectively tuned by the sampling tuning circuit 5 and then input to the tuning oscillation circuit 6 shown in FIG. 1 without being converted into an intermediate frequency signal.
[0053]
In the sampling tuning circuit 5 shown in FIG. 3, a CMOS transistor 402 ′ may be used instead of the MOS transistor 402 as shown in FIG. When the CMOS structure transistor 402 'is used, it is less susceptible to parasitic capacitance. Further, since all the elements constituting the sampling tuning circuit 5 can be formed by a CMOS process, the process for forming a chip can be simplified.
[0054]
【The invention's effect】
As described above in detail, according to the present invention, the received signal received by the antenna is sampled by the reference clock, and only the same frequency component as the reference clock is extracted from the received signal. A tuning circuit can be configured without using a circuit. Therefore, the antenna can be directly connected to the tuning circuit and tuned to a desired frequency without being affected by the capacity of the antenna. Further, since digital tuning processing is performed, there is no influence of the temperature characteristics of the component parts. Furthermore, since the tuning frequency can be changed only by changing the frequency of the reference clock, and Q changes according to the tuning frequency, tuning can be performed with the same accuracy over a wide band.
[Brief description of the drawings]
FIG. 1 is a block diagram of one embodiment of a radio receiver.
FIG. 2 is a block diagram showing a detailed configuration of a local oscillation circuit and a channel selection circuit.
FIG. 3 is a circuit diagram showing a detailed configuration of an intermediate frequency filter.
FIG. 4 is a waveform diagram showing a change in output of a ring counter.
FIG. 5 is a block diagram showing a detailed configuration of a stereo demodulation circuit.
FIGS. 6A to 6E are signal waveform diagrams of respective parts in the stereo demodulation circuit.
FIG. 7 is a principle diagram for explaining an operation principle of a GIC included in a tuning oscillation circuit.
FIG. 8 is a circuit diagram showing a detailed configuration of a tuning oscillation circuit.
FIG. 9 is an equivalent circuit diagram of FIG.
FIG. 10 is a diagram showing an example of a transistor having a CMOS configuration used in the sampling tuning circuit.
[Explanation of symbols]
1 FM receiver
2 AM receiver
3 Antenna
4 Clock generation circuit
5 Sampling tuning circuit
6 Tuning oscillation circuit
101 High frequency amplifier circuit
102 Mixing circuit
103 Local oscillator circuit
104 Channel selection circuit
105 Intermediate frequency amplifier
106 FM detection circuit
107 Stereo demodulation circuit
108L, 108R De-emphasis circuit
109L, 109R Low frequency amplifier circuit
110L, 110R Speaker
201 Tuning circuit
202 Mixing circuit
203 Local oscillator circuit
204 Tuning circuit
205 Intermediate frequency amplifier
206 AM detection circuit
207 Low frequency amplifier circuit
208 Speaker

Claims (4)

In a radio receiver that performs detection processing by extracting only the frequency components desired to be selected from the received signal received by the rod antenna,
A pulse generation circuit that outputs a plurality of pulse signals that have a period that is an integral multiple of the period of the reference clock and that are out of phase with each other;
A sampling tuning circuit that extracts only the same frequency component as the pulse signal from the reception signal based on the result of sampling the reception signal with the pulse signal output from the pulse generation circuit;
The sampling tuning circuit extracts only a frequency component desired to be selected from the received signal input without selective tuning or frequency conversion when receiving an AM broadcast,
A radio receiver characterized in that a detection process is performed based on an output of the sampling tuning circuit. In claim 1,
An FM front end for converting the received signal into a low frequency FM intermediate frequency signal;
An FM detector for performing a detection process on the FM intermediate frequency signal;
When receiving an FM broadcast, the output of the FM front end unit is guided to the sampling tuning circuit, and only a predetermined intermediate frequency component is extracted from the output of the FM front end unit and supplied to the FM detection unit. A reception switching means for guiding the received signal to the sampling tuning circuit without selective tuning or frequency conversion at the time of receiving a broadcast;
A reference clock generating circuit for outputting the reference clock having a predetermined frequency when receiving FM broadcast, and outputting the reference clock having a frequency corresponding to a frequency desired to be selected when receiving AM broadcast;
A radio receiver further comprising: In claim 1 or 2,
A local oscillation circuit that outputs a local oscillation signal having a frequency corresponding to a frequency desired to be selected when receiving an AM broadcast;
A frequency converter for converting an output of the sampling tuning circuit into a low AM intermediate frequency based on the local oscillation signal when receiving an AM broadcast;
A radio receiver characterized in that when receiving an AM broadcast, the frequency of the reference clock and the frequency of the local oscillation signal are changed in conjunction with each other. In any one of Claims 1-3,
The sampling tuning circuit includes a plurality of capacitors for accumulating charges corresponding to the signal level of the received signal in synchronization with each pulse signal provided corresponding to each pulse signal output from the pulse generation circuit. A radio receiver featuring.

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