JPH10163407A - Lead frame for semiconductor device, and semiconductor device - Google Patents
Lead frame for semiconductor device, and semiconductor deviceInfo
- Publication number
- JPH10163407A JPH10163407A JP8330279A JP33027996A JPH10163407A JP H10163407 A JPH10163407 A JP H10163407A JP 8330279 A JP8330279 A JP 8330279A JP 33027996 A JP33027996 A JP 33027996A JP H10163407 A JPH10163407 A JP H10163407A
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- semiconductor chip
- semiconductor device
- conductive adhesive
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体製造工程にお
いて、銀ペースト等の導電性接着剤を介して半導体チッ
プをリードフレームに接着させるダイボンディング技術
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a die bonding technique for bonding a semiconductor chip to a lead frame via a conductive adhesive such as a silver paste in a semiconductor manufacturing process.
【０００２】[0002]
【従来の技術】図５により従来の技術を説明する。銀ペ
ースト等の低粘土導電性接着剤２を介在物としてリード
フレームのダイパッド３に半導体チップ１を接着させる
には、まず導電性接着剤２をダイパッド３上の１ケ所も
しくは数ケ所に塗布し、その後半導体チップ１を一定荷
重で押さえながらダイパッド３に固定させる。半導体チ
ップ１を介して一定荷重で押さえられた導電性接着剤２
はダイパッド３と半導体チップ１との間で薄く拡がる。
この時、半導体チップ１の大きさ以上に拡がる導電性接
着剤２は半導体チップ１の側面に塊状となって付着す
る。半導体チップ１とダイパッド３との接着強度は、介
在する導電性接着剤２の拡がり面積と密接な関係があ
り、所定の接合強度を得るためには一定以上の導電性接
着剤の拡がり面積が必要である。2. Description of the Related Art A conventional technique will be described with reference to FIG. In order to bond the semiconductor chip 1 to the die pad 3 of the lead frame using the low clay conductive adhesive 2 such as a silver paste as an inclusion, the conductive adhesive 2 is first applied to one or several places on the die pad 3. Thereafter, the semiconductor chip 1 is fixed to the die pad 3 while holding the semiconductor chip 1 at a constant load. Conductive adhesive 2 pressed at a constant load via semiconductor chip 1
Extends thinly between the die pad 3 and the semiconductor chip 1.
At this time, the conductive adhesive 2 spreading beyond the size of the semiconductor chip 1 adheres to the side surface of the semiconductor chip 1 in a lump. The adhesive strength between the semiconductor chip 1 and the die pad 3 has a close relationship with the spread area of the conductive adhesive 2 interposed therebetween, and a certain or more spread area of the conductive adhesive is required to obtain a predetermined bonding strength. It is.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、上述の
ような従来のダイボンディングの方法では、半導体チッ
プとダイパッドとの所定の接合強度が得られるために必
要とされる導電性接着剤の拡がり面積を確認するために
は、半導体チップによって視界が遮られ、且つ半導体チ
ップとダイパッドの間隔が狭いために視認することが不
可能であり、導電性接着剤が半導体チップの下面部の大
きさ以上に拡がった場合しか視認することはできない。
すなわち、導電性接着剤の拡がりが半導体チップの下面
部の大きさ以下であって、しかも所定の接合強度が得ら
れるような場合であっても、導電性接着剤の拡がりを視
認するためには、一定以上の導電性接着剤を塗布して半
導体チップの下面部の大きさ以上に拡がる様に、その量
を設定しなくてはならない。半導体チップの下面部の大
きさに対してダイパッドの大きさが十分でなく、導電性
接着剤の拡がりうる領域が無いか、又は非常に小さい場
合には、導電性接着剤の量が少ない時には、その拡がり
が視認出来ず、導電性接着剤の量が多い時には半導体チ
ップの側面部に拡がる導電性接着剤がダイパッドより落
ちて、後の製造工程に悪影響を与えることとなる。本発
明は上記の様な問題に対し、導電性接着剤の拡がりが半
導体チップの下面部の大きさ以下の拡がりであっても導
電性接着剤の拡がりを確認可能とし、且つ、導電性接着
剤の必要以上の拡がりを抑制することが可能なダイパッ
ド構造のリードフレームを得ることを目的とするもので
ある。However, in the above-mentioned conventional die bonding method, the spread area of the conductive adhesive required for obtaining a predetermined bonding strength between the semiconductor chip and the die pad is reduced. In order to confirm, it is impossible to see because the field of view is blocked by the semiconductor chip and the distance between the semiconductor chip and the die pad is small, and the conductive adhesive spreads over the size of the lower surface of the semiconductor chip. You can only see it if you have.
That is, even if the spread of the conductive adhesive is equal to or smaller than the size of the lower surface portion of the semiconductor chip and a predetermined bonding strength is obtained, in order to visually check the spread of the conductive adhesive, The amount must be set so that a certain amount or more of a conductive adhesive is applied and spread to the size of the lower surface portion of the semiconductor chip or more. The size of the die pad is not sufficient for the size of the lower surface of the semiconductor chip, there is no area where the conductive adhesive can spread, or if it is very small, when the amount of the conductive adhesive is small, When the spread cannot be visually recognized and the amount of the conductive adhesive is large, the conductive adhesive spreading on the side surface of the semiconductor chip falls from the die pad, which adversely affects a later manufacturing process. The present invention solves the above-mentioned problem by making it possible to confirm the spread of the conductive adhesive even if the spread of the conductive adhesive is equal to or smaller than the size of the lower surface of the semiconductor chip. It is an object of the present invention to obtain a lead frame having a die pad structure capable of suppressing unnecessarily spreading.
【０００４】[0004]
【課題を解決するための手段】上記課題を達成するため
に、リードフレームのダイパッド部を半導体チップ搭載
面である上段部と、該搭載面周辺部に段差を設けた下段
部を有する構造とし、又、ダイパッドの下段部に該ダイ
パッド部中心より略同心円状に配置した線状の凹凸を有
する構造とした。更に、ダイパッド部の上段部周辺側面
部に内側方向への食い込み部が設けられている構造とし
た。In order to achieve the above object, a die pad portion of a lead frame has a structure having an upper portion which is a mounting surface of a semiconductor chip and a lower portion having a step around the mounting surface. In addition, a structure having linear concavities and convexities arranged substantially concentrically from the center of the die pad portion in the lower portion of the die pad was adopted. Furthermore, a structure is provided in which a biting portion in the inward direction is provided on a peripheral side surface portion of the upper step portion of the die pad portion.
【０００５】[0005]
【作用】リードフレームのダイパッド部をこの様な構造
とすることにより、ダイボンディング工程において半導
体チップの下面部とダイパッドの上段部との間に隙間が
与えられ、この隙間より導電性接着剤の拡がりを視認す
ることが可能となる。又、ダイパッドの下段部に設けら
れた凹凸を有する形状により、導電性接着剤の設定量が
多い場合であっても、ダイパッドの下段部における導電
性接着剤の必要以上の拡がりを抑制することができる。With the die pad portion of the lead frame having such a structure, a gap is provided between the lower surface portion of the semiconductor chip and the upper portion of the die pad in the die bonding step, and the conductive adhesive spreads from the gap. Can be visually recognized. In addition, due to the shape having irregularities provided in the lower part of the die pad, even if the amount of the conductive adhesive set is large, it is possible to suppress unnecessary spread of the conductive adhesive in the lower part of the die pad. it can.
【０００６】更に、ダイパッド部の上段部周辺側面部の
内側方向に設けられた食い込み部によりダイパッド上段
部から拡がり出た導電性接着剤の下段部への拡がり自体
が抑制されることになる。Further, the bite portion provided inwardly of the peripheral side portion of the upper portion of the die pad portion suppresses the spread itself of the conductive adhesive which has spread from the upper portion of the die pad to the lower portion.
【０００７】[0007]
【発明の実施の形態】次に、この発明を適用した実施例
を図面を参照して説明する。図１は本発明による導電性
接着剤を介した半導体チップとダイパッドとの接着の第
１の実施例であり、１は半導体チップ、２は導電性接着
剤、３はダイパッド、４は半導体チップの下面部、５は
ダイパッドの下段部の凹凸、６はダイパッドの上段部で
ある。接着の方法は、まずダイパッド３の上段部６にお
いて半導体チップ１が接着されるべき位置の一カ所また
は数カ所に所定の接着強度が得られる量の導電性接着剤
２を塗布する。その後、半導体チップ１をダイパッド３
の上段部６に位置合わせをして、半導体チップ１に一定
の加重を加えることにより導電性接着剤２を半導体チッ
プ１とダイパッド３の上段部６との間で所要の面積が得
られるように拡がりをもたせる。しかる後に、適当な温
度と時間の組合せによるキュアリングと呼ばれる工程を
経て、導電性接着剤２は固化し、導電性接着剤２を介し
た半導体チップ１とダイパッド３との固着が完了する。
本図においては、導電性接着剤２の拡がりが半導体チッ
プの下面部４の大きさより小さいが、本発明の実施によ
り、半導体チップとダイパッドとの隙間から導電性接着
剤の拡がりが視認できる。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the bonding between a semiconductor chip and a die pad via a conductive adhesive according to the present invention, wherein 1 is a semiconductor chip, 2 is a conductive adhesive, 3 is a die pad, and 4 is a semiconductor chip. The lower surface portion, 5 is the unevenness of the lower portion of the die pad, and 6 is the upper portion of the die pad. In the bonding method, first, the conductive adhesive 2 is applied to one or several positions of the upper part 6 of the die pad 3 where the semiconductor chip 1 is to be bonded, so as to obtain a predetermined bonding strength. After that, the semiconductor chip 1 is
The conductive adhesive 2 is positioned so as to obtain a required area between the semiconductor chip 1 and the upper step 6 of the die pad 3 by applying a predetermined weight to the semiconductor chip 1 by positioning the semiconductor chip 1. Give it a spread. Thereafter, the conductive adhesive 2 is solidified through a process called curing using an appropriate combination of temperature and time, and the bonding between the semiconductor chip 1 and the die pad 3 via the conductive adhesive 2 is completed.
In this figure, the spread of the conductive adhesive 2 is smaller than the size of the lower surface portion 4 of the semiconductor chip. However, the spread of the conductive adhesive can be visually recognized from the gap between the semiconductor chip and the die pad by implementing the present invention.
【０００８】第２図は本発明実施例において導電性接着
剤の拡がりが半導体チップ側面に達した例であるが、半
導体チップとダイパッドとの間の空隙が、はみ出す導電
性接着剤に対してバッファとしての効果を持ち、且つダ
イパッドの下段部に設けられた凹凸のために導電性接着
剤の拡がりが抑制される。FIG. 2 shows an example in which the conductive adhesive spreads to the side surface of the semiconductor chip in the embodiment of the present invention, but the gap between the semiconductor chip and the die pad has a buffer against the protruding conductive adhesive. And the spread of the conductive adhesive is suppressed due to the unevenness provided at the lower part of the die pad.
【０００９】第３図はダイパッドの上段部側面部の内側
方向に設けられた食い込み部の一実施例であり、ダイパ
ッド部のみを図示したものである。本実施例においては
ダイパッド上段部の側面に設けられた食い込み部７はダ
イパッド上段部から拡がり出た導電性接着剤の下段部へ
の拡がり自体を少なくする働きをもつ。FIG. 3 shows an embodiment of the biting portion provided inward of the side surface portion of the upper portion of the die pad, and shows only the die pad portion. In the present embodiment, the biting portion 7 provided on the side surface of the upper portion of the die pad has a function of reducing the spread itself of the conductive adhesive extending from the upper portion of the die pad to the lower portion.
【００１０】第４図は半導体チップがダイパッドよりも
大きい場合の本発明の実施例であるが、半導体チップと
ダイパッド間の空隙に導電性接着剤が保持されることに
より導電性接着剤がダイパッドより落ちることが防止さ
れている。この場合ダイパッド裏面からの導電性接着剤
の拡がりの視認も可能となる。従来の技術では第４図の
様な効果は全く期待できない。FIG. 4 shows an embodiment of the present invention in which the semiconductor chip is larger than the die pad. The conductive adhesive is held in the gap between the semiconductor chip and the die pad so that the conductive adhesive is larger than the die pad. Falling is prevented. In this case, the spread of the conductive adhesive from the rear surface of the die pad can be visually recognized. With the prior art, the effect shown in FIG. 4 cannot be expected at all.
【００１１】[0011]
【発明の効果】以上説明したように本発明を実施するこ
とにより所定の接合強度を得るための適切な量の導電性
接着剤の塗布が可能となり、且つ導電性接着剤の半導体
チップ側面への拡がりを抑制することにより、ダイパッ
ドより大きな半導体チップをダイボンディングすること
が可能となる。As described above, by practicing the present invention, it is possible to apply an appropriate amount of conductive adhesive to obtain a predetermined bonding strength, and to apply the conductive adhesive to the side surface of the semiconductor chip. By suppressing the spread, a semiconductor chip larger than the die pad can be die-bonded.
【図１】本発明による半導体チップとダイパッドとの接
着の第１の実施例FIG. 1 shows a first embodiment of the bonding between a semiconductor chip and a die pad according to the present invention.
【図２】本発明による半導体チップとダイパッドとの接
着の第２の実施例FIG. 2 shows a second embodiment of the bonding between a semiconductor chip and a die pad according to the present invention.
【図３】本発明による半導体チップとダイパッドとの接
着の第３の実施例FIG. 3 shows a third embodiment of the bonding between a semiconductor chip and a die pad according to the present invention.
【図４】本発明による半導体チップとダイパッドとの接
着の第４の実施例FIG. 4 shows a fourth embodiment of the bonding between a semiconductor chip and a die pad according to the present invention.
【図５】従来の半導体チップとダイパッドとの接着例FIG. 5 shows a conventional example of bonding a semiconductor chip to a die pad.
１ 半導体チップ ２ 導電性接着剤 ３ ダイパッド ４ 半導体チップの下面部 ５ ダイパッド下段部の凹凸 ６ ダイパッドの上段部 ７ ダイパッドの上段部側面部の内側方向への食い込み
部DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Conductive adhesive 3 Die pad 4 Lower surface part of semiconductor chip 5 Unevenness of lower part of die pad 6 Upper part of die pad 7 Biting part inward of upper part side part of die pad
Claims (5)
在物として、半導体チップをダイパッド部に接着固定さ
せる半導体装置用リードフレームにおいて、上記ダイパ
ッド部に半導体チップ搭載面である上段部と、該搭載面
周辺部に段差を設けた下段部を有することを特徴とする
半導体装置用リードフレーム。1. A lead frame for a semiconductor device in which a semiconductor chip is bonded and fixed to a die pad portion using a low-viscosity conductive adhesive such as silver paste as an intervening member. A lead frame for a semiconductor device, comprising: a lower step portion having a step around the mounting surface.
イパッド部中心より略同心円状に配置した線状の凹凸を
設けたことを特徴とする請求項１記載の半導体装置用リ
ードフレーム。2. The lead frame for a semiconductor device according to claim 1, wherein linear concaves and convexes arranged substantially concentrically from the center of the die pad portion are provided on the surface of the lower portion of the die pad portion.
ッドの上段部の周辺部の外側に拡張して設けられている
ことを特徴とする請求項１記載及び請求項２記載の半導
体装置用リードフレーム。3. The lead frame for a semiconductor device according to claim 1, wherein the lower portion of the die pad portion is provided so as to extend outside the peripheral portion of the upper portion of the die pad. .
内側方向への食い込み部が設けられていることを特徴と
する請求項１乃至請求項３記載の半導体装置用リードフ
レーム。4. The lead frame for a semiconductor device according to claim 1, wherein an inward biting portion is provided in a peripheral side surface portion of the upper portion of the die pad portion.
ドフレームの上記ダイパッド部の上段部の一辺の寸法と
略等しいか寸法が大の半導体チップを上記ダイパッド部
の上段部に上記低粘度導電性接着剤を介在物として接着
固定させることを特徴とする半導体装置。5. The semiconductor device according to claim 1, wherein a semiconductor chip having a dimension substantially equal to or larger than one side of an upper portion of said die pad portion of said lead frame for a semiconductor device is provided on said upper portion of said die pad portion. A semiconductor device characterized in that a conductive adhesive is bonded and fixed as an inclusion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8330279A JPH10163407A (en) | 1996-11-26 | 1996-11-26 | Lead frame for semiconductor device, and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8330279A JPH10163407A (en) | 1996-11-26 | 1996-11-26 | Lead frame for semiconductor device, and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10163407A true JPH10163407A (en) | 1998-06-19 |
Family
ID=18230881
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8330279A Pending JPH10163407A (en) | 1996-11-26 | 1996-11-26 | Lead frame for semiconductor device, and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10163407A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7256504B2 (en) | 2004-04-06 | 2007-08-14 | Siemens Aktiengesellschaft | Circuit support for a semiconductor chip and component |
| JP2012033756A (en) * | 2010-07-30 | 2012-02-16 | On Semiconductor Trading Ltd | Semiconductor device and its manufacturing method |
| JP2013219194A (en) * | 2012-04-09 | 2013-10-24 | Sansha Electric Mfg Co Ltd | Semiconductor device |
-
1996
- 1996-11-26 JP JP8330279A patent/JPH10163407A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7256504B2 (en) | 2004-04-06 | 2007-08-14 | Siemens Aktiengesellschaft | Circuit support for a semiconductor chip and component |
| DE102004016940B4 (en) | 2004-04-06 | 2019-08-08 | Continental Automotive Gmbh | Circuit carrier for a semiconductor chip and a component with a semiconductor chip |
| JP2012033756A (en) * | 2010-07-30 | 2012-02-16 | On Semiconductor Trading Ltd | Semiconductor device and its manufacturing method |
| JP2013219194A (en) * | 2012-04-09 | 2013-10-24 | Sansha Electric Mfg Co Ltd | Semiconductor device |
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