JPH10163344A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique to reduce the area of a memory cell of an SRAM(Static Random Access Memory). SOLUTION: At a photolithography process to form a common gate electrode FG1 for a driving MISFET(Metal Insulator Semiconductor Field Effect Transistor) Qd1 and a load MISFET Qp1 , and to form a common gate electrode FG2 for a driving MISFET Qd2 and a load MISFET Qp2 , a second mask-pattern latent image is superimposed on a first mask-pattern latent image having a pattern where a pull-out electrode of the gate electrode FG1 is connected to a pull-out electrode of the gate electrode FG2 . By this arrangement, a latent image of a pattern of a pair of gate electrodes FG1 and FG2 , where the pull-out electrode of the gate electrode FG1 and the pull-out electrode of the gate electrode FG2 are separated, is formed on a photoresist film on the semiconductor wafer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, to an SRAM (Static).
The present invention relates to a technology effective when applied to a semiconductor integrated circuit device having a random access memory (Random Access Memory).

[0002]

2. Description of the Related Art An SRAM as a semiconductor memory device has a flip-flop circuit and two transfer MISFETs (Metal Insulator) at the intersection of a word line and one complementary data line.
latorSemiconductor Field Effect Transistor).

A flip-flop circuit of an SRAM memory cell is configured as an information storage unit and stores one-bit information. The flip-flop circuit of this memory cell is
As an example, a pair of CMOS (Complementary Metal Oxid
e Semiconductor) inverter. Each of the CMOS inverters is an n-channel type driving MISF.
ET and a p-channel type load MISFET. The transfer MISFET is of an n-channel type. That is, this memory cell has six MISFEs.
So-called full CMOS (Full Complemen)
Tary Metal Oxide Semiconductor) type.

A pair of Cs constituting a flip-flop circuit
The input / output terminals of the MOS inverter are cross-coupled via a pair of wires (hereinafter referred to as local wires). The input / output terminal of one CMOS inverter is connected to the source region of one transfer MISFET and the other CMOS
The input / output terminal of the S inverter has the other transfer MISF
The source area of the ET is connected. One transfer MISF
One of the complementary data lines is connected to the drain region of the ET, and the other of the complementary data lines is connected to the drain region of the other transfer MISFET. A pair of transfer MISF
A word line is connected to each gate electrode of ET,
The conduction and non-conduction of the transfer MISFET are controlled by this word line.

[0005] This type of complete CMOS SRAM is disclosed in Japanese Patent Application Laid-Open Nos. 6-302786 and 7-302.
This is described in, for example, JP-A-99255, JP-A-8-17944 and the like.

[0006]

However, with the increase in the capacity of the semiconductor memory device, the above-mentioned complete CMOS type SRA is required.
In considering reduction of the occupied area of M memory cells,
The inventor has found the following problems.

FIG. 1 shows a pattern layout of a memory cell of a conventional complete CMOS type SRAM. As shown, a driving MIS constituting one CMOS inverter is shown.
The common gate electrode FG ₁ of the FET Qd ₁ and the load MISFET Qp ₁ has the gate electrode FG ₁ and the local wiring L
₂ is formed, and similarly, a driving MIS constituting the other CMOS inverter is formed.
The common gate electrode FG ₂ of the FET Qd ₂ and the load MISFET Qp ₂ has the gate electrode FG ₂ and the local wiring L
An extraction electrode for connecting to _{No. 1} is formed.

However, in order to ensure high resolution in the photolithography process, the width (W ₁ ) of the extraction electrode of the gate electrode FG ₁ and the width (W ₂ ) of the extraction electrode of the gate electrode FG ₂ must be set to 0. 0.4 μm or more, the gate electrode F
Distance between the extraction electrode and the extraction electrode of the gate electrode FG ₂ in G ₁ (S) is not have to set more than 0.4 .mu.m, and factors which alienating reduction in memory cell size of the full CMOS type SRAM Has become.

An object of the present invention is to provide a technique capable of reducing the area of an SRAM memory cell.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) The semiconductor integrated circuit device of the present invention has a driving MISF
A pair of CMOSs comprising an ET and a load MISFET
A memory cell is configured by a flip-flop circuit configured by an inverter, and a pair of transfer MISFETs connected to a pair of input / output terminals of the flip-flop circuit,
The driving MISFET and the load MI are formed of a first conductive film.
A common pair of gate electrodes of the SFET and the transfer M
An SRAM in which a gate electrode of an ISFET is formed, and a pair of local wirings connecting a pair of input / output terminals of the pair of CMOS inverters is formed by a second conductive film formed on the first conductive film. MISFE for driving
An extraction electrode for connecting T and a common gate electrode of the load MISFET and the local wiring is provided on the common gate electrode of the pair of the driving MISFET and the load MISFET, and the width of the extraction electrode is Are formed to be narrower than the width of the lead electrode of the gate electrode of the MISFET formed in the peripheral circuit.

(2) A method of manufacturing a semiconductor integrated circuit device according to the present invention, wherein the pair of the driving MISFET and the load MISF is one of the manufacturing steps of the SRAM of (1).
In a lithography process for forming a common gate electrode of ET, a latent image of a mask pattern formed on a first mask and a latent image of a mask pattern formed on a second mask are formed on a resist film on a semiconductor wafer. A pair of the driving MISs having a predetermined shape are formed by overlapping.
A resist pattern for a common gate electrode of the FET and the load MISFET is formed on the semiconductor wafer.

According to the above-mentioned means, the latent image of the mask pattern of the first mask and the latent image of the mask pattern of the second mask are superimposed on the resist film on the semiconductor wafer, whereby the mask pattern of the first mask is formed. Is corrected, and a resist pattern finer than the mask pattern of the first mask can be formed on the semiconductor wafer.

That is, first, using the first mask,
An extraction electrode of a common gate electrode of one driving MISFET and a load MISFET and the other driving MISFE
A latent image having a pattern in which T and a lead electrode of a common gate electrode of the load MISFET are connected is formed on a resist film on a semiconductor wafer. Next, by using the second mask, an extraction electrode of a common gate electrode of one driving MISFET and a load MISFET and the other driving MISFET are used.
A latent image having a pattern for separating the FET and a common gate electrode lead electrode of the load MISFET is formed on a resist film on a semiconductor wafer. Thereby, the lead electrode of the common gate electrode of one driving MISFET and the load MISFET, and the other driving MISFET and the load M
A latent image of a pattern in which a common gate electrode of the ISFET is separated from a lead electrode is formed on a resist film on a semiconductor wafer, and a pair of a driving MISFET and a load MISFET are formed.
A resist pattern for a common gate electrode of the FET is formed on a semiconductor wafer.

At this time, the width of the resist pattern of the lead electrode of the common gate electrode of the pair of the driving MISFET and the load MISFET can be arbitrarily set.
It is possible to make the width of the resist pattern of the lead electrode of the common gate electrode of T smaller than the width of the resist pattern of the lead electrode according to the layout rule of the gate electrode of the MISFET formed in the peripheral circuit.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description will be omitted.

FIG. 2 is an equivalent circuit diagram of a memory cell of the SRAM of the present embodiment. As illustrated, the memory cell of the SRAM according to the present embodiment includes a pair of driving MISFETs Qd ₁ arranged at intersections of a pair of complementary data lines (data line DL, data line bar DL) and a word line WL. , Q
d ₂ , a pair of load MISFETs Qp ₁ and Qp ₂ and a pair of transfer MISFETs Qt ₁ and Qt ₂ . Driving MISFETs Qd ₁ , Qd ₂ and transfer Qt
₁ and Qt ₂ are of the n-channel type, and the load MISFE
TQp ₁ and Qp ₂ are of a p-channel type. That is, this memory cell has four n-channel type MISFs.
It is composed of a complete CMOS type using ET and two p-channel MISFETs.

Six MISFs constituting the memory cell
Among the ETs, the driving MISFET Qd ₁ and the load MISFET Qd ₁
The FET Qp ₁ forms a CMOS inverter (INV ₁ ), and the driving MISFET Qd ₂ and the load MISFET Q
p ₂ constitutes a CMOS inverter (INV ₂ ). This pair of CMOS inverters (INV ₁ , INV ₂ )
Between the input / output terminals (accumulation nodes A and B) of the first pair via a pair of local interconnects L ₁ and L ₂ to form a flip-flop circuit as an information storage unit for storing 1-bit information. ing.

[0020] One of the input and output terminals of the flip-flop circuit (storage node A) is connected to the source region of the transfer MISFET Qt _1, the other input-output terminal (the storage node B) is connected to the source region of the transfer MISFET Qt ₂ Have been. Drain region of the transfer MISFET Qt ₁ is connected to the data line DL, the drain region of the transfer MISFET Qt ₂ is connected to the data line bar DL.

One end of the flip-flop circuit (the respective source regions of the load MISFETs Qp ₁ and Qp ₂ )
Is connected to the power supply voltage (Vcc), and the other end (MISF for driving)
The source regions of ETQd ₁ and Qd ₂ are connected to a reference voltage (Vss). The power supply voltage (Vcc) is, for example, 5 V, and the reference voltage (Vss) is, for example, 0 V (GN
D voltage).

The operation of the above circuit will be described.
The storage node A of the OS inverter (INV ₁ ) has a high potential (“
H ″), the drive MISFET Qd ₂ is ON
, The storage node B of the other CMOS inverter (INV ₂ ) becomes low potential (“L”). Therefore, the driving MISFET Qd ₁ is turned off, and the high potential (“H”) of the storage node A is held. That is, a pair of CMOs
A latch circuit in which S inverters (INV ₁ , INV ₂ ) are cross-coupled holds the state of the mutual storage nodes A and B, and holds information while the power supply voltage is applied.

The word line WL is connected to the gate electrode of the transfer MISFETQt _1, Qt _2, conduction of the transfer MISFET Qt _1, Qt ₂ This word line WL, the non-conduction is controlled. That is, when the word line WL is at a high potential ("H"), the transfer MISFET Qt
₁ and Qt ₂ are turned on, and the latch circuit and the complementary data lines (data lines DL and / DL) are electrically connected. Therefore, the potential state (“H” or “H”) of the storage nodes A and B is set.
L ") appear on the data lines DL and / DL, and are read as information of the memory cells.

To write information in the memory cell, the word line WL is set to the "H" potential level and the transfer MISFET Qt
₁ and Qt ₂ are turned on to transmit information on the data lines DL and DL to the storage nodes A and B. In order to read the information of the memory cell, the information of the storage nodes A and B in which the word line WL is at the “H” potential level and the transfer MISFETs Qt ₁ and Qt ₂ are in the ON state are also written to the data lines DL and / DL.
To communicate.

Next, FIG. 3 (a plan view of a semiconductor substrate showing approximately one memory cell) showing the specific configuration of the memory cell, and FIG. 4 (a cross section of the semiconductor substrate taken along line AA 'in FIG. 3). FIG. 5 and FIG. 5 (cross-sectional view of the semiconductor substrate taken along line BB ′ in FIG. 3). 6 and 7 are plan views of a semiconductor substrate showing approximately one memory cell in a manufacturing process.

As shown in FIGS. 3 to 5, six MISFETs constituting a memory cell are formed in an active region surrounded by a field insulating film 2 of a p ⁻ type semiconductor substrate 1. Driving MISFET composed of n-channel type
Each of Qd ₁ , Qd ₂ and the transfer MISFETs Qt ₁ , Qt ₂ are formed in the active region of the p-type well 3, and the load MISFETs Qp ₁ , Qp ₂ formed of the p-channel type are formed in the active region of the n-type well 4. Is formed. Each of the p-type well 3 and the n-type well 4 is formed on a main surface of a p-type epitaxial silicon layer 5 formed on the semiconductor substrate 1.

The transfer MISFETs Qt ₁ and Qt ₂ have a gate electrode FG ₃ formed integrally with the word line WL. The gate electrode FG ₃ (word line WL) is composed of a polycide film 6 in which a polycrystalline silicon film and a refractory metal silicide film are laminated, and is formed on a gate insulating film 7 composed of a silicon oxide film. I have.

The source and drain regions of the transfer MISFETs Qt ₁ and Qt ₂ are formed of a low impurity concentration n ⁻ -type semiconductor region 8 and a high impurity concentration n ⁺ -type impurity region formed in the active region of the p-type well 3. It is composed of a semiconductor region 9. That is, the source region and the drain region of each of the transfer MISFETs Qt ₁ and Qt ₂ have an LDD structure.

The driving MISFET Qd ₁ and the load MISFET Qp ₁ forming one CMOS inverter of the flip-flop circuit have a common gate electrode FG ₁ , and the driving MISFET Qd ₁ forming the other CMOS inverter.
The ISFET Qd ₂ and the load MISFET Qp ₂ have a common gate electrode FG ₂ (FIG. 6).

The gate electrodes FG ₁ and FG ₂ are composed of the same polycide film 6 as the gate electrode FG ₃ (word line WL) of the transfer MISFETs Qt ₁ and Qt ₂ , and are formed on the gate insulating film 7. I have. Note that the gate electrodes FG ₁ ,
An n-type impurity (for example, phosphorus) is introduced into the polycrystalline silicon film below the polycide film 6 constituting the FG ₂ and the gate electrode FG ₃ (word line WL).

The source and drain regions of the driving MISFETs Qd ₁ and Qd ₂ are formed of a low impurity concentration n ⁻ -type semiconductor region 8 and a high impurity concentration n ⁺ -type semiconductor formed in the active region of the p-type well 3. The region 9 is configured. That is, the source region and the drain region of each of the driving MISFETs Qd ₁ and Qd ₂ have an LDD structure.

Each of the source and drain regions of the load MISFETs Qp ₁ and Qp ₂ is an n-type well 4.
Are formed of a low impurity concentration p ⁻ type semiconductor region (not shown) and a high impurity concentration p ⁺ type semiconductor region (not shown) formed in the active region. That is, the load MI
The source region and the drain region of each of the SFETs Qp ₁ and Qp ₂ have an LDD structure.

The driving MISFETs Qd ₁ , Qd ₂ ,
Load MISFETs Qp ₁ and Qp ₂ and Transfer MISFET
A metal silicide film 1 for lowering the resistance is provided above the source and drain regions of ETQt ₁ and Qt _2.
0 is formed. The metal silicide film 10 is composed of, for example, a titanium silicide (TiSi ₂ ) film.

Driving MISFET Qd ₁ and Load MIS
Common gate electrode FG ₁ of FETQp ₁ has a lead-out electrode for connecting the constructed local wiring L ₂ by the gate electrodes FG ₁ and metal wires M ₁ of the first layer, for driving MISFET Qd ₂ and load MISF
ETQp common gate electrode FG ₂ of ₂ has a lead-out electrode for connecting the local wiring L ₁ constituted with the gate electrode FG ₂ by a first layer of metal wiring M _1.

The MISFE constituting the peripheral circuit
Gate electrode FG ₄ of T also this gate electrode FG ₄ first
And a lead-out electrode for connecting the metal wires M ₁ layer eyes (Fig. 8). However, the driving MISF
The width (W ₁ ) of the extraction electrode of the common gate electrode FG ₁ of the ETQd ₁ and the load MISFET Qp ₁ depends on the gate electrode FG of the MISFET of the peripheral circuit according to the layout rule.
₄ is smaller than the width (W ₃ ) of the extraction electrode, and similarly, the driving MISFET Qd ₂ and the load MISFET
The width (W ₂ ) of the extraction electrode of the common gate electrode FG ₂ of the FET Qp ₂ is M
Width of the extraction electrode of the gate electrode FG ₄ of ISFET (W
It is formed thinner than ₃ ).

Driving MISFET Qd ₁ and Load MIS
Common gate electrode FG ₁ of FET Qp ₁ , driving MIS
The silicon nitride film 11 and the first interlayer insulating film 12 are formed on the common gate electrode FG ₂ of the FET Qd ₂ and the load MISFET Qp ₂ and the gate electrode FG ₃ (word line WL) of the transfer MISFETs Qt ₁ and Qt _2. Are formed. This first interlayer insulating film 12 on is metal wiring M ₁ of the first layer is formed, the local wiring L _1, L ₂ by metal wires M ₁ of the first layer is configured (FIG. 7). First interlayer insulating film 12 is, for example, a silicon oxide film and the BPSG is composed of a laminated film of a (Boron Phospo Silicate Glass) film, the metal wiring M ₁ of the first layer is a tungsten (W) film It is configured.

The local wiring L ₁ is the first interlayer insulating film 12
Through the contact hole 13a, the drain region of the driving MISFET Qd ₁ and the load MISFET Qp ₁ , and the driving MISFET Qd ₁
It is connected to the common gate electrode FG ₂ of Qd ₂ and the load MISFET Qp ₂ . Similarly, the local wiring L ₂ first
Contact hole 1 opened in interlayer insulating film 12 of the layer
3b, the respective drain regions of the driving MISFET Qd ₂ and the load MISFET Qp ₂ , and the driving MISFET Qd ₁ and the load MISFET Qp 2
It is connected to a common gate electrode FG _{1 1.}

Therefore, the drain region of the driving MISFET Qd ₁ and the load MISFET are formed by the first-layer metal wiring M ₁ formed on the first-layer interlayer insulating film 12.
ETQp ₁ drain region, drive MISFET Qd ₂
A common gate electrode FG ₂ for load MISFET Qp ₂
The source region of the transfer MISFET Qt ₁ is electrically connected.

Similarly, the drain region of the driving MISFET Qd ₂ , the drain region of the load MISFET Qp ₂ , and the driving MISFE are formed by the first-layer metal wiring M ₁ .
TQD ₁ and common source region of the gate electrode FG ₁ and transfer MISFET Qt ₂ of the load MISFET Qp ₁ is electrically connected.

[0040] Note that the driving MISFET Qd ₁ and the load for MISFET Qp ₁ common with the extraction electrode of the gate electrode FG ₁ load MISFET Qp ₂ of the drain region, and the same contact hole 13b is formed, for driving MISFET Qd ₂ and load MISFET Q
The common gate electrode FG ₂ lead electrodes on the driving MISFET Qd ₁ of the drain region of the p _2, the same contact hole 13a is formed.

[0041] Further, through the contact hole 13c which is opened in the interlayer insulating film 12 of the first layer, the metal wiring M ₁ of the first layer, each of the source region of the driving MISFET Qd _1, Qd _2, load MISFETQp ₁ , Qp ₂ and the transfer MISFETs Qt ₁ ,
Qt ₂ are connected to respective drain regions.

A second-layer metal wiring M ₂ is formed above the first-layer metal wiring M ₁ via a second-layer interlayer insulating film 14. Second interlayer insulating film 1
4, for example, a stacked film of a silicon oxide film and a BPSG film, metal wiring M ₂ of the second layer is composed, for example, W film.

The second-layer metal wiring M ₂ is formed in the first through hole 1 formed in the second-layer interlayer insulating film 14.
Is connected to the transfer MISFET Qt _1, metal wires M ₁ of the first layer disposed on each of the drain regions Qt ₂ through 5a.

Further, the second-layer metal wiring M ₂ constitutes a reference voltage (V _SS ), and is driven through a first through hole 15 b opened in the second-layer interlayer insulating film 14. The MISFETs Qd ₁ and Qd ₂ are connected to the first-layer metal wiring M ₁ disposed on the respective source regions. Further, the second-layer metal wiring M ₂ constitutes the power supply voltage (Vcc), and the load M through the first through hole 15 c opened in the second-layer interlayer insulating film 14.
ISFETQp _1, Qp ₂ of which is connected to the first-layer metal wiring M ₁ arranged in each of the source regions.

A third-layer metal wiring M ₃ is formed above the second-layer metal wiring M ₂ via a third-layer interlayer insulating film 16. Third interlayer insulating film 1
6 is, for example, a silicon oxide film, SOG (Spin On Glass)
And consists of a laminated film of a silicon oxide film, the third layer metal wiring M ₃ of is constituted, for example, an aluminum alloy film.

The third-layer metal wiring M ₃ constitutes a data line DL and a bar DL.
The bar DL is connected to the transfer MISFET Qt through the second through hole 17 formed in the third interlayer insulating film 16.
₁ and Qt ₂ are arranged on the respective drain regions.
It is connected to the metal wiring M ₂ of the layer first.

Next, a description will be given of a method of manufacturing the memory cell of the present embodiment configured as described above.

First, after a p-type epitaxial silicon layer 5 is grown on a semiconductor substrate 1 made of p ⁻ -type single crystal silicon, a field insulating film 2 is formed on the main surface of the semiconductor substrate 1.
To form Subsequently, p is added to the semiconductor substrate 1 by a well-known method.
Form a well 3 and an n-well 4. Next, a gate insulating film 7 made of a thin silicon oxide film is formed on each of the main surfaces of the p-type well 3 and the n-type well 4 surrounded by the field insulating film 2.

Next, the driving MISFET Qd ₁ and the common gate electrode FG ₁ of the load MISFET Qp _1, the common gate electrode FG ₂ and the transfer MISFET Qt ₁ of the drive MISFET Qd ₂ and load MISFET Qp _2, Q
gate electrode FG ₃ of t ₂ to form a (word line WL).

The gate electrodes FG ₁ and FG ₂ and the gate electrode FG ₃ (word line WL) are
Polycrystalline silicon film, tungsten silicide (WSi ₂ ) film and silicon oxide film 18 into which phosphorus has been introduced by the VD method
Are sequentially deposited, and the silicon oxide film 18, the polycrystalline silicon film, and the WSi ₂ film are sequentially processed by dry etching using a photoresist pattern (resist pattern) as a mask.

Next, the driving MISFET Qd ₁ and the common gate electrode FG ₁ of the load MISFET Qp _1, the common gate electrode FG ₂ and the transfer MISFET Qt ₁ of the drive MISFET Qd ₂ and load MISFET Qp _2, Q
The method of forming the resist pattern used when forming the gate electrode FG ₃ (word line WL) at t ₂ will be described below.

First, a photoresist film having a thickness of 1 to 2 μm is uniformly applied to the surface of a semiconductor wafer by a spin coating method, and then the semiconductor wafer is baked. The photoresist materials used for manufacturing the semiconductor integrated circuit device are a negative ultraviolet resist and a positive ultraviolet resist. However, since a high resolution can be obtained, a positive ultraviolet resist is used in this embodiment. .

[0053] Then, set the first mask MG ₁ and the semiconductor wafer shown in FIG. 9 in an exposure apparatus, after the accurate alignment, for example, ultraviolet ray having a wavelength of 0.365 .mu.m (i-line) for a predetermined time irradiation (exposure) to form a latent image of the first mask pattern of the mask MG ₁ in the photoresist film on the semiconductor wafer. The first mask MG _1, the gate electrode FG _1, FG ₂ and the gate electrode FG ₃ (word line WL) has a mask pattern which led all formed, the gate electrode FG _1, FG ₂ and the gate electrode FG ₃ A shifter for forming a thin resist pattern (word line WL) on a semiconductor wafer is formed. In the drawing, reference numeral 20 denotes a light shielding film, 21 denotes a shifter, and 22 denotes an exposed portion of the mask substrate.

Subsequently, the second mask MG ₂ shown in FIG.
Set in the exposure apparatus, similarly to the first mask MG _1,
For example certain time irradiation with ultraviolet rays (i-rays) with a wavelength of 0.365 .mu.m (exposure) to form a latent image of the second mask pattern of the mask MG ₂ to the photoresist film on the semiconductor wafer.

Next, after performing the developing process for a predetermined time, rinsing with pure water and spin drying are continuously performed. As a result, the gate electrodes FG ₁ ,
Resist pattern of FG ₂ and the gate electrode FG ₃ (word line WL) is formed on a semiconductor wafer.

[0056] Figure 11 first cross sectional view of the mask MG ₁ (a), the cross sectional view of a second mask MG ₂ (b), the
(C) the light intensity at the first light intensity at the mask MG ₁ on the semiconductor wafer at the time of exposure using the (solid line) and the semiconductor wafer when the light exposure using the second mask MG ₂ (dotted line ) And (d) show the _first mask MG1 and the second mask MG.
₂ shows a resist pattern formed on a semiconductor wafer by using No. ₂ . In the drawing, reference numeral 23 denotes a mask substrate, and reference numeral 24 denotes a photoresist film.

FIG. 11 shows the structure of the first mask MG ₁ .
Latent image in accordance with the light intensity indicated by the solid line in (c) is formed in the photoresist film, the second mask MG _2, FIG. 11
A latent image according to the light intensity indicated by the dotted line in (c) is formed on the photoresist film. Therefore, the development of the photoresist film after exposure, the photoresist film of strong light intensity is obtained region by the first mask MG ₁ and second mask MG ₂ is removed, FIG. 11 (d) A resist pattern is formed on a semiconductor wafer.

That is, with only the first mask MG ₁ ,
A latent image of a mask pattern in which the gate electrodes FG ₁ and FG ₂ and the gate electrode FG ₃ (word line WL) shown in FIG. 9 are connected is formed on the photoresist film on the semiconductor wafer.
However, the second latent image of the mask pattern of the mask MG ₂ (alpha region) by forming superimposed on the photoresist film shown in FIG. 10, gate electrodes FG _1, FG ₂ and the gate electrode FG ₃ (word A latent image from which each of the lines WL) is separated can be formed on the photoresist film.

[0059] At this time, since the width of the resist pattern width and the extraction electrode of the gate electrode FG ₂ of the resist pattern of the extraction electrodes of the gate electrode FG ₁ may be respectively arbitrarily set, the gate electrode FG ₁ of the width of the resist pattern width and the extraction electrode of the gate electrode FG ₂ of the resist pattern extraction electrode, is narrower than the width of the resist pattern of the extraction electrodes of the gate electrode FG ₄ of the MISFET of the peripheral circuit in accordance with the layout rule be able to.

Next, an n-type impurity (P, As) is added to the p-type well 3 by ion implantation using the resist pattern as a mask.
Is introduced into the n-type well 4 with a p-type impurity (BF ₂ ). Then, CVD (Chemical Vapor D)
silicon oxide film deposited by RIE (Reac
tive Ion Etching) and patterned by, for driving MISFET Qd ₁ and the common gate electrode FG ₁ of the load MISFET Qp _1, the common gate electrode FG ₂ and the transfer MISFET Qt ₁ of the drive MISFET Qd ₂ and load MISFET Qp _2, Qt ₂ A side wall spacer 19 is formed on each side wall of the gate electrode FG ₃ (word line WL). Next, an n-type impurity (P, As) is introduced into the p-type well 3 and a p-type impurity (BF ₂ ) is introduced into the n-type well 4 by ion implantation using the resist pattern as a mask.

Next, the n-type impurity and the p-type impurity are thermally diffused to form a driving MISFET on the main surface of the p-type well 3.
Source regions and drain regions (n ⁻ -type semiconductor region 8 and n ⁺ -type semiconductor region 9) of Qd ₁ , Qd ₂ and transfer MISFETs Qt ₁ , Qt ₂ are formed, and a main surface of the n-type well 4 is used for load. Source regions and drain regions (not shown) of the MISFETs Qp ₁ and Qp ₂ are formed.

Next, the driving MISFETs Qd ₁ , Qd
d ₂ , load MISFETs Qp ₁ , Qp ₂ and transfer M
A metal silicide film, for example, a titanium silicide (TiSi ₂ ) film is formed on the surface of each of the source and drain regions of the ISFETs Qt ₁ and Qt ₂ by a self-alignment method.

Next, a silicon nitride film 11 and a first interlayer insulating film 12 are deposited on the entire surface of the semiconductor substrate 1. The first interlayer insulating film 12 is composed of, for example, a laminated film of a silicon oxide film and a BPSG film. Using the resist pattern formed on the first interlayer insulating film 12 as a mask, the first interlayer insulating film 12 and the silicon nitride film 11 are sequentially etched. Thereby, the driving M
_On the drain region of ISFET Qd ₁ and MIS for driving
FETQd ₂ and to form the same contact hole 13a on the common gate electrode FG ₂ of the load MISFET Qp _2, further, a contact hole 13a in the load MISFET Qp ₁ of the drain region.

Similarly, on the drain region of the load MISFET Qp ₂ and on the drive MISFET Qd ₁ and the load M
To form the same contact hole 13b on the common gate electrode FG ₁ of ISFETQp _1, further driving MI
Contact hole 1 on the drain region of SFET Qd ₂
3b is formed.

Further, the driving MISFETs Qd ₁ and Qd ₂
, The load MISFETs Qp ₁ ,
Qp ₂ on each source region and transfer MISF
Forming a contact hole 13c to ETQt _1, each of the drain regions of Qt _2.

Next, a first-layer wiring material (not shown) is deposited on the entire surface of the semiconductor substrate 1. This wiring member is formed of a metal film, for example, a W film. Next, a resist pattern by patterning the wiring material by dry etching using a mask, to form the metal wiring M ₁ of the first layer. Thus, the drain region of the driving MISFET Qd _1, the drain region of the load MISFET Qp _1, MISFET Q for the load and the driving MISFET Qd ₂
local wiring L ₁ connecting the common gate electrode FG ₂ of p ₂
Is formed.

Similarly, the drain region of the driving MISFET Qd ₂ , the drain region of the load MISFET Qp ₂ ,
MISFET Qd ₁ for driving and MISFET Qp ₁ for load
Local interconnection L ₂ connecting the common gate electrode FG ₁ is formed.

Further, the driving MISFETs Qd ₁ , Qd ₂
, The load MISFETs Qp ₁ ,
Qp ₂ on each source region and transfer MIS
FETQt _1, Qt to respective drain contact hole 13c formed on a region of ₂ to form a metal wiring M ₁ of the first layer.

Next, a second layer composed of a laminated film in which a silicon oxide film and a BPSG film are sequentially deposited on the entire surface of the semiconductor substrate 1
A first interlayer insulating film 14 is deposited.

Thereafter, first through holes 15a to 15c are formed in the second interlayer insulating film 14 by dry etching using the resist pattern as a mask. The first through hole 15a is formed above each drain region of the transfer MISFETs Qt ₁ and Qt ₂ , and the first through hole 15b is formed above each source region of the drive MISFETs Qd ₁ and Qd _2. The first through hole 15c is formed above each source region of the load MISFETs Qp ₁ and Qp ₂ .

Next, a second-layer wiring material (not shown) is deposited on the entire surface of the semiconductor substrate 1. This wiring member is formed of a metal film, for example, a W film. Next, a resist pattern by patterning the wiring material by dry etching using a mask, the power supply voltage (Vcc), the second layer is of forming a metal wiring M ₂ constituting a reference voltage (Vss). Further, a transfer MISFET Qt _1, Qt ₂ of each of the first even second-layer metal wiring in the through holes 15a formed above the drain region M _2.

Next, a third interlayer insulating film 16 composed of a laminated film in which a silicon oxide film, an SOG film, and a silicon oxide film are sequentially deposited on the entire surface of the semiconductor substrate 1 is deposited.

Thereafter, a second through hole 17 is formed in the third interlayer insulating film 16 by dry etching using the resist pattern as a mask. The second through hole 17 is formed above each drain region of the transfer MISFETs Qt ₁ and Qt ₂ .

Next, a third-layer wiring material (not shown) is deposited on the entire surface of the semiconductor substrate 1. This wiring member is formed of a metal film, for example, an aluminum alloy film. Next, the wiring material is patterned by dry etching using a resist pattern as a mask, and the data line D is formed.
L, to form the third layer metal wiring M ₃ of which constitutes a bar DL.

Finally, a final passivation film is deposited on the third-layer metal wiring M ₃ to complete the memory cell of the present embodiment.

In the present embodiment, as shown in FIG. 9, the driving MISF formed on the first mask MG ₁
ETQd ₁ and the common gate electrode FG ₁ of the load MISFET Qp _1, MIS for the load and the driving MISFET Qd ₂
Common gate electrode FG ₂ and transfer M of FET Qp ₂
ISFETQt _1, the mask pattern of the gate electrode FG ₃ of Qt ₂ is has led all, as shown in FIG. 12, the extraction electrode and the gate electrode of the gate electrode FG ₁ FG
_The gate electrode FG ₁ remains connected with the extraction electrode ₂
And gate electrode FG ₃ , gate electrode FG ₂ and gate electrode F
A mask pattern is disconnected and G ₃ first mask MG
_It may be formed in _one .

At this time, the second mask MG ₂ includes FIG.
As shown in a pattern (alpha region) for separating the extraction electrode of the extraction electrode and the gate electrode FG ₂ gate electrode FG _1, excessive resist pattern on a semiconductor wafer according to a first shifter on the mask MG ₁ A pattern (β region) is formed to prevent the formation of a pattern.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0079]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, a pair of driving MISFs constituting a flip-flop circuit of an SRAM memory cell are provided.
Since the width of the extraction electrode of the common gate electrode of the ET and the load MISFET can be reduced, the SRA
The area of M memory cells can be reduced.

[Brief description of the drawings]

FIG. 1 is a main part plan view showing a pattern layout of a memory cell of a conventional SRAM.

FIG. 2 is an equivalent circuit diagram of an SRAM memory cell.

FIG. 3 is a plan view of a principal part showing a pattern layout of a memory cell of the SRAM according to the embodiment of the present invention;

FIG. 4 is a cross-sectional view of a principal part of the semiconductor substrate taken along line AA ′ of FIG. 3 showing a memory cell of the SRAM according to the embodiment of the present invention;

FIG. 5 is a cross-sectional view of a principal part of the semiconductor substrate taken along line BB ′ of FIG. 3 showing a memory cell of the SRAM according to the embodiment of the present invention; Area view).

FIG. 6 is a plan view of a principal part showing a pattern layout of a memory cell of the SRAM according to the embodiment of the present invention;

FIG. 7 is a main part plan view showing a pattern layout of a memory cell of the SRAM according to the embodiment of the present invention;

FIG. 8 is a plan view of a principal part showing a pattern layout of a peripheral circuit of the SRAM according to the embodiment of the present invention;

FIG. 9 is a plan view of a principal part of a mask pattern of a first mask according to an embodiment of the present invention.

FIG. 10 is a plan view of a principal part of a mask pattern of a second mask according to an embodiment of the present invention.

FIG. 11 is an explanatory diagram illustrating a method of forming a latent image on a photoresist film on a semiconductor wafer using a first mask and a second mask.

FIG. 12 is a plan view of a principal part of a mask pattern of a first mask according to another embodiment of the present invention.

FIG. 13 is a plan view of a principal part of a mask pattern of a second mask according to another embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 field insulating film 3 p-type well 4 n-type well 5 p-type epitaxial silicon layer 6 polycide film 7 gate insulating film 8 n ^- type semiconductor region 9 n ⁺ type semiconductor region 10 metal silicide film 11 silicon nitride film 12th First interlayer insulating film 13a Contact hole 13b Contact hole 13c Contact hole 13d Contact hole 14 Second interlayer insulating film 15a First through hole 15b First through hole 15c First through hole 16 Third layer Eye interlayer insulating film 17 Second through hole 18 Silicon oxide film 19 Sidewall spacer 20 Light shielding film 21 Shifter 22 Mask substrate exposed portion 23 Mask substrate 24 Photoresist film FG _{1 to} FG ₄ Gate electrode L ₁ , L ₂ Local wiring DL, bar DL Data line Qd ₁ , Qd ₂ driving MISFET Qp _1, Qp ₂ for load MISFET Qt _1, Qt ₂ for transfer MISFET WL word lines A, B accumulation node Vcc power supply voltage Vss reference voltage INV _1, INV ₂ CMOS inverters M ₁ of the first layer metal wiring M ₂ second layer of metal wiring M ₃ metal wiring MG ₁ of the third layer first mask MG ₂ second mask

Claims (7)

[Claims] A driving MISFET and a load MIS
A flip-flop circuit composed of a pair of CMOS inverters composed of FETs; and a pair of transfer MISFEs connected to a pair of input / output terminals of the flip-flop circuit.
A memory cell is constituted by T, a pair of common gate electrodes of the driving MISFET and the load MISFET and a gate electrode of the transfer MISFET are formed of the first conductive film, and the first conductive film is formed on the first conductive film. A semiconductor integrated circuit device having an SRAM in which a pair of local wirings connecting a pair of input / output terminals of the pair of CMOS inverters is formed by a formed second conductive film, wherein the driving MISFE is used.
An extraction electrode for connecting T and a common gate electrode of the load MISFET and the local wiring is provided on the common gate electrode of the pair of the driving MISFET and the load MISFET, and the width of the extraction electrode is A semiconductor integrated circuit device having a width smaller than a width of a lead electrode of a gate electrode of a MISFET formed in a peripheral circuit. 2. The semiconductor integrated circuit device according to claim 1, wherein one driving MISFET and one load MISFET.
The contact hole for connecting the extraction electrode of the common gate electrode of the FET and one local wiring is the same as the contact hole for connecting the drain region of the other load MISFET and the one local wiring. , The other drive MISFET and the other load MISFE
A contact hole for connecting a common gate electrode of T to the other local wiring, and the one driving MISFE
A semiconductor integrated circuit device, wherein a contact hole for connecting the drain region of T and the other local wiring is the same. 3. The semiconductor integrated circuit device according to claim 1, wherein a pair of said driving MISFET and a load MISFET are provided.
A semiconductor integrated circuit device, wherein an extraction electrode of a common gate electrode of ET is formed of the first conductive film. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein in the lithography step of forming a common gate electrode of the pair of the driving MISFET and the load MISFET, the MISFET is formed on the first mask. The latent image of the mask pattern formed on the semiconductor wafer and the latent image of the mask pattern formed on the second mask are formed on the resist film on the semiconductor wafer so as to form a pair of the driving MISFET having a predetermined shape and the load. Forming a resist pattern of a common gate electrode of the MISFET for use on the semiconductor wafer. 5. The method for manufacturing a semiconductor integrated circuit device according to claim 4, wherein one of the driving MISFET and the load M
A mask pattern in which a common gate electrode extraction electrode of an ISFET and a common gate electrode extraction electrode of a driving MISFET and a load MISFET are connected to each other is formed on the first mask. The one driving MISFET and the load M
A latent image of a mask pattern in which an extraction electrode of a common gate electrode of an ISFET is connected to an extraction electrode of a common gate electrode of the other driving MISFET and a load MISFET, and a mask pattern formed on the second mask; Is formed on the resist film on the semiconductor wafer, thereby forming the one driving MIS.
An extraction electrode of a common gate electrode of the FET and the load MISFET, and the other drive MISFET and the load MI
A method of manufacturing a semiconductor integrated circuit device, comprising: forming a resist pattern on a semiconductor wafer in which a common gate electrode of an SFET is separated from an extraction electrode. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein said first mask is a phase shift mask. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 6, wherein one of the driving MISFET and the load M
A mask pattern in which a common gate electrode extraction electrode of an ISFET and a common gate electrode extraction electrode of a driving MISFET and a load MISFET are connected to each other is formed on the first mask. The one driving MISFET and the load M
A latent image of a mask pattern in which an extraction electrode of a common gate electrode of an ISFET is connected to an extraction electrode of a common gate electrode of the other driving MISFET and a load MISFET, and a mask pattern formed on the second mask; Is formed on the resist film on the semiconductor wafer, thereby forming the one driving MIS.
An extraction electrode of a common gate electrode of the FET and the load MISFET, and the other drive MISFET and the load MI
A resist pattern in which a common gate electrode of an SFET is separated from a lead electrode is formed on the semiconductor wafer, and an unnecessary pattern by a shifter provided on the first mask is not transferred onto the semiconductor wafer. A method for manufacturing a semiconductor integrated circuit device.