JPH10154811A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable lessening of deterioration in step coverage, decrease in dielectric withstand voltage, disconnection of wire of a metal wiring layer by a method wherein a conductive layer is thermally oxidized, and an interlayer insulating film, with which the conductive layer filled in a groove and the conductive layer left in a pad region are electrically separated, is formed. SOLUTION: A photoresist PR is selectively formed on the region where a lead-out electrode pad is formed, and a polysilicon layer 16 is etched back to the degree that its thickness becomes one half or less. Then, after the photoresist PR has been exfoliated, the polysilicon layer 16 is thermally oxidized at about 1100 deg.C for 20 minutes under a steam oxidization state. Thus, polysilicon is left in a trench 14 and on a pad region, and the polysilicon is electrically separated by the interlayer insulating film 17 consisting of an oxide film formed by the oxidization of the polysilicon layer 16. Accordingly, the deterioration of the stepcoverage on stepping, the lowering of dielectric withstand voltage and the disconnection of a metal wiring layer can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improvement in a method for manufacturing a trench type power semiconductor device.

[0002]

2. Description of the Related Art A method of manufacturing a conventional semiconductor device will be described below with reference to FIGS. FIG.
FIG. 12 shows a conventional power MO having a so-called trench structure.
It is sectional drawing explaining the manufacturing method of SFET. First, as shown in FIG. 7, an n − -type drain layer 1B is formed on the surface of a semiconductor substrate 1A made of n + -type silicon, and a p + -type channel layer 1C is formed on the surface. Further, an oxide film 3 is formed on the channel layer 1C, and an n + -type impurity is selectively implanted and diffused to form a source region 2. afterwards,
The oxide film 3 near the source region 2 and the semiconductor substrate 1 are selectively etched to form a trench 4.

Next, as shown in FIG. 8, an oxide film 5 is formed on the inner wall of the trench 4 by thermally oxidizing the entire surface. Next, as shown in FIG. 9, a polysilicon layer 6 is formed on the entire surface to fill the inside of the trench 4, and then the entire surface is etched back to remove the polysilicon layer 6 on the substrate surface. As shown, the gate electrode 7 filled in the trench 4 and the extraction electrode pad 8 are simultaneously formed.

Next, as shown in FIG. 11, an interlayer insulating film 9 made of an oxide film or the like is formed on the entire surface by a CVD method to cover the gate electrode 7 and the lead electrode pad 8, and then a part of the source region 2 is formed. The interlayer insulating film 9 in the region is removed, and FIG.
As shown in FIG. 2, a metal wiring layer 10 in contact with the source region 2 is formed.

[0005]

According to the above-mentioned manufacturing method, in order to eliminate the depression on the trench 4 of the polysilicon layer 6, the polysilicon layer 6 must be 1.5 .mu.m under normal conditions.
At this time, the step d shown in FIG. 10 also increases to 1.5 μm, so that the step coverage deteriorates due to the step, and the dielectric breakdown voltage at the step is reduced, or the step coverage is reduced. Metal wiring layer 1
This causes troubles such as disconnection of 0.

Furthermore, it is necessary to deposit an interlayer insulating film by the CVD method, and the number of steps has been increased.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional disadvantages. As shown in FIG. 1, a step of forming a groove in a semiconductor substrate, a step of filling the groove, and a step of A step of forming a conductor layer covering the entire surface of the substrate and a step of selectively forming a mask in a region where a pad is to be formed, and etching back the conductor layer to a thickness of about half the thickness of the conductor layer And thermally forming the conductive layer to form an interlayer insulating film that electrically separates the conductive layer filled in the trench from the conductive layer remaining in the pad region. According to the method of manufacturing a semiconductor device,
This is to solve the above-mentioned problem.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A power MOSFET having a trench structure according to an embodiment of the present invention will be described below with reference to the drawings. 1 to 6 are cross-sectional views illustrating a method for manufacturing a power MOSFET according to the present embodiment.
First, as shown in FIG. 1, an n − -type drain layer 11B is formed on the surface of a semiconductor substrate 11A made of n + -type silicon by an epitaxial growth method, and a p + -type channel layer 11C is formed on the surface. Further, a silicon oxide film 13 is formed on the channel layer 11C, and arsenic (As +), which is an N + -type impurity, is selectively implanted and diffused into the surface layer of the channel layer at a dose of 6 × 10 13 cm -1. , Source region 1
Form 2 Thereafter, the silicon oxide film 13 and the semiconductor substrate 11 near the source region 12 are selectively dry-etched to form a trench 14 having a width of 1 μm and a depth of 1.5 to 3 μm, preferably about 2 μm.

Next, as shown in FIG. 2, the entire surface is thermally oxidized to form a silicon oxide film 15 having a thickness of about 500 ° on the inner wall of trench 14. This silicon oxide film becomes a gate insulating film in the power MOSFET of the present embodiment. Next, as shown in FIG. 3, the trench 14 is filled,
A polysilicon layer 16 having a thickness of about 1.5 μm is formed on the entire surface of the semiconductor substrate 11 so as to cover the entire surface.

Next, a photoresist P is formed in a region where an extraction electrode pad is to be formed later (hereinafter referred to as a pad region).
R is selectively formed, and as shown in FIG.
The polysilicon layer 16 is etched back until the thickness of the polysilicon layer 16 becomes about 0.5 μm, which is less than half. Therefore, the level difference d 'between the polysilicon remaining in the pad region at this point and the surface of the etched back polysilicon layer 16 is 0.5.
It becomes about μm.

Next, after removing the photoresist PR, the polysilicon layer 16 is formed under the condition that a thermal oxide film of about 6000 ° is formed, specifically, for example, about 1100 ° C.
Thermal oxidation is performed under the condition of steam oxidation for 20 minutes. Then
Although the surface of the polysilicon layer 16 is oxidized to become a silicon oxide film, the polysilicon layer inside the trench 14 is not oxidized and maintains the state of polysilicon.

Further, since the extraction electrode pad formation region is not etched back, the film thickness is about 1.5 μm, and although the surface is oxidized, the inside is not oxidized, and the thickness is about half from the bottom. Only the state of polysilicon is maintained. Thus, as shown in FIG. 5, polysilicon remains in trench 14 and the pad region, and these polysilicons are electrically connected by interlayer insulating film 17 made of an oxide film formed by oxidizing the polysilicon layer. Will be separated. Among them, the polysilicon remaining in the trench functions as the gate electrode 18 of the power MOSFET of the present embodiment, and the polysilicon in the region where the extraction electrode pad is formed functions as the extraction electrode pad 19.

After that, the interlayer insulating film 17 in a part of the source region 12 is selectively removed by etching or the like to expose the source region 12, and then a wiring layer 20 made of metal such as aluminum is formed on the entire surface. By patterning this, a trench type power MO as shown in FIG.
The SFET is completed. As described above, according to the method of manufacturing the semiconductor device according to the present embodiment, when simultaneously forming the gate electrode and the extraction electrode pad, after removing all the polysilicon layers by etch back and separating them, C
Without taking the step of forming an interlayer insulating film by the VD method,
As shown in FIG. 4, the polysilicon layer 16 is reduced to about half the thickness.
After etching back, the entire surface is thermally oxidized as shown in FIG.
9 are formed at the same time and the interlayer insulating film 17 is also formed at the same time, so that the step d 'in the pad region can be reduced to almost 1/3 as compared with the conventional case, and the step coverage at this step, which has been a conventional problem, is reduced. It is possible to reduce the deterioration of the device, the decrease in the withstand voltage, the disconnection of the metal wiring layer formed thereon, and the like.

Further, since the interlayer insulating film is formed simultaneously in the step of forming the gate electrode and the like, the number of steps can be reduced as compared with the conventional method in which the interlayer insulating film is separately formed by the CVD method or the like. It is possible to improve the yield and reduce the manufacturing cost. In the present embodiment, the thickness of the polysilicon layer 16 is set to 1.5 μm, and the thickness after the etch back is set to 0.5 μm. However, the present invention is not limited to these values. Even if the film thickness after the etch-back is approximately half the original film thickness, the same effect can be obtained.

In this embodiment, a method of manufacturing a power MOSFET having a trench structure is described. However, the present invention is not limited to this, and an electrode such as polysilicon is buried in a trench and formed at the same time. It is explained that the same effect can be obtained in almost any case where the electrode pad is formed on the substrate surface, and that it can be applied to an IGBT (insulated gate bipolar transistor) having a trench structure. Needless to do.

[0016]

As described above, according to the method of manufacturing a semiconductor device according to the present invention, after the polysilicon layer is etched back to about half the film thickness, the entire surface is thermally oxidized to form the gate electrode and the gate electrode. Since the extraction electrode pads are formed at the same time and the interlayer insulating film is also formed at the same time, the steps in the electrode pads can be reduced as compared with the prior art, and the step coverage at these steps, which has been a conventional problem, is deteriorated, the withstand voltage is reduced. Alternatively, it is possible to reduce disconnection of a metal wiring layer formed thereon.

Further, by simultaneously forming the interlayer insulating film, the number of steps can be reduced as compared with the conventional method in which the interlayer insulating film is separately formed by a CVD method or the like.
It is possible to improve the yield and reduce the manufacturing cost.

[Brief description of the drawings]

FIG. 1 is a first sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a second sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 3 is a third sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 4 is a fourth sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 5 is a fifth sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 6 is a sixth sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 7 is a first cross-sectional view illustrating a method for manufacturing a semiconductor device according to a conventional example.

FIG. 8 is a second sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 9 is a third cross-sectional view illustrating a method for manufacturing a semiconductor device according to a conventional example.

FIG. 10 is a fourth sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 11 is a fifth sectional view illustrating the method for manufacturing the semiconductor device according to the conventional example.

FIG. 12 is a sixth sectional view illustrating the method of manufacturing the semiconductor device according to the conventional example.

Claims (4)

[Claims] 1. A step of forming a groove in a semiconductor substrate, a step of forming a conductor layer that fills the groove and covers the entire surface of the semiconductor substrate, and selectively forms a mask in a pad region where an electrode pad is formed. Etching back the conductive layer to a thickness of about half the thickness of the conductive layer; and thermally oxidizing the conductive layer to fill the groove with the conductive layer and the pad. Forming an interlayer insulating film for electrically separating a conductive layer remaining in the region from the conductive layer. 2. The method according to claim 1, wherein a polysilicon layer is formed in the step of forming the conductor layer, and an interlayer insulating film made of a silicon oxide film is formed in the step of forming the interlayer insulating film. The manufacturing method of the semiconductor device described in the above. 3. a step of forming the one conductivity type drain region layer on a surface layer of the one conductivity type semiconductor substrate, and forming an opposite conductivity type channel region layer on the surface layer of the drain region layer; Forming a source region by diffusing an impurity of one conductivity type into the channel region layer; and forming the first insulating film and the semiconductor substrate in a region near the source region. Selectively etching to form a groove and forming a second insulating film on the inner wall of the groove; forming a conductive layer filling the groove and covering the entire surface of the semiconductor substrate; Selectively forming a mask in a pad region where an electrode pad is to be formed, and etching back the conductive layer to a thickness of about half the thickness of the conductive layer; and thermally oxidizing the conductive layer. And said groove is filled Forming an interlayer insulating film for electrically separating an electric conductor layer and an electric conductor layer remaining in the pad region, using the electric conductor layer filled in the groove as a gate electrode, and extracting the electric conductor layer in the pad region. Forming a wiring layer that selectively removes the interlayer insulating film in a part of the source region to expose the source region and that makes contact with the source region. A method for manufacturing a semiconductor device. 4. The method according to claim 2, wherein a polysilicon layer is formed in the step of forming the conductor layer, and an interlayer insulating film made of a silicon oxide film is formed in the step of forming the interlayer insulating film. The manufacturing method of the semiconductor device described in the above.