JPH10154043A - Memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a memory controller which does not have so large total capacity of buffer memory and also has excellence in data transfer efficiency. SOLUTION: A virtual storage device group 81 consists of storage devices 100 and 200 which store data, a virtual storage device group 82 consists of storage devices 101 and 201, a virtual buffer memory group 71 comprises buffer memory 11a and 21a, and a virtual buffer memory group 72 comprises buffer memory 12a and 22a. In a certain cycle, data is read from the group 81 and stored in the group 71, and also, data which is already stored in the group 72 is outputted to a data receiver. In the next cycle, data is read from the group 82 and stored in the group 72, also, data which is stored from the group 71 in the preceding cycle is outputted to the data receiver, and in every cycle, the groups 71 and 72 are alternately switched from/to the groups for data storage and data output.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device, and more particularly to an improvement in data transfer efficiency of a buffer memory control device having a plurality of buffer memories.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a configuration of a conventional buffer memory control device. In FIG. 5, 10,
Reference numeral 20 denotes a data output device, and 11a to 11d and 12a to 12
d is a buffer memory built in the data output device 10, 2
Reference numerals 1a to 21d and 22a to 22d denote buffer memories built in the data output device 20, and 100 denotes a data output device 10
, 200 is a storage device connected to the data output device 20, 110 is an interface circuit for controlling the storage device 100, 210 is an interface circuit for controlling the storage device 200, and 4a to 4d issue a data transfer request. The data receiving device (client terminal) 50 outputs data from the data output devices 10 and 20 to the data receiving device 4a.
To 4d are switch devices (hubs).

The data of files A, B, C and D (not shown) are stored in a buffer memory
Block data A1, A2,..., B1, B in units of 6 KB
2, ..., C1, C2, ..., D1, D2, ...
These block data are stored in the storage devices 100 and 200. For example, the configuration of file A is shown in FIG. In FIG. 6, 1 is a file A divided into small blocks of 1 KB size, and 2 is a small block 1 to 256 of the file A.
A consisting of 256 KB
1 and 3 are small blocks 257 to 512 following block A1.
Block A2 composed of 256 KB
Thus, the file A is divided into a plurality of blocks in units of 256 KB. Then, as shown in FIG. 5, blocks A1 and A1 whose block numbers are odd-numbered.
Are stored in the storage device 100, while the blocks A2, A4,.
Are respectively stored. Hereinafter, although not shown, the file B is also divided into block data B1 to B6 similarly to the file A, and the storage device 100,
The file C is also divided into block data C1 to C6 and stored in the storage devices 100 and 200, respectively.
Is stored in the block data D1.
From the storage devices 100 and 20 respectively.
0 is stored.

In the above configuration, the data of the file A is received by the data receiving device 4a, the data of the file B is received by the data receiving device 4b, the data of the file C is received by the data receiving device 4c, and the data of the file D is received by the data receiving device 4c. Device 4
A transmission method in the case of transmitting data simultaneously to d is disclosed in, for example, JP-A-5-35407. The method will be described below with reference to FIG. FIG. 7 is a diagram showing a relationship between data reading from a storage device and data output to a data receiving device in each cycle in a conventional buffer memory control device.

In the first cycle, the data output device 10
Reads the block data A1 from the storage device 100 and temporarily stores it in the buffer memory 11a. Next, the block data B1 is read from the storage device 100 and temporarily stored in the buffer memory 11b. The data output device 20 reads the block data C2 from the storage device 200 and temporarily stores the read block data C2 in the buffer memory 21c. next,
Reading the block data D2 from the storage device 200,
The data is temporarily stored in the buffer memory 21d.

In the second cycle, the data output device 10
Reads the block data C3 from the storage device 100 and temporarily stores it in the buffer memory 11c. Next, the block data D3 is read from the storage device 100 and temporarily stored in the buffer memory 11d. The data output device 20 reads the block data A2 from the storage device 200 and temporarily stores the read block data A2 in the buffer memory 21a. Next, the block data B2 is read from the storage device 200 and temporarily stored in the buffer memory 21b. On the other hand, the data output device 10 outputs the block data A1 temporarily stored in the buffer memory 11a to the data receiving device 4a via the switch device 50, and outputs the block data B1 temporarily stored in the buffer memory 11b to the data receiving device. 4b. Also, the data output device 20
Via the switch device 50, the block data C2 temporarily stored in the buffer memory 21c is transferred to the data receiving device 4c.
And outputs the block data D2 temporarily stored in the buffer memory 21d to the data receiving device 4d.

In the third cycle, the data output device 10
Reads the block data A3 from the storage device 100 and temporarily stores it in the buffer memory 12a. Next, the block data B3 is read from the storage device 100 and temporarily stored in the buffer memory 12b. Further, the data output device 20 reads the block data C4 from the storage device 200 and temporarily stores the block data C4 in the buffer memory 22c. Next, the block data D4 is read from the storage device 200 and temporarily stored in the buffer memory 22d. On the other hand, the data output device 10 outputs the block data C3 temporarily stored in the buffer memory 11c to the data receiving device 4c via the switch device 50, and outputs the block data D3 temporarily stored in the buffer memory 11d to the data receiving device. Output to 4d. Also, the data output device 20
Via the switch device 50, the block data A2 temporarily stored in the buffer memory 21a is transferred to the data receiving device 4a.
And outputs the block data B2 temporarily stored in the buffer memory 21b to the data receiving device 4b.

However, when the data transfer from the data output device 10 to the data receiving device 4a or the data transfer to the data receiving device 4b in the second cycle is not completed, the data output device 10 in the third cycle is not completed. The start of data transfer will be delayed. That is, depending on the file,
Since the data transfer rate required by the data receiving device is low, it is not possible to specify when the switching from the data output device 10 to the data output device 20 is performed. The switching of these output devices is the same for the files B, C, and D. When the transfer is performed smoothly, as shown in FIG. 8, a video file 1 (video) is transmitted from both data output devices 10 and 20 at a maximum transfer efficiency of 1.5 Mbps.
-file-1) and video file 2 (video-file-2) are switched at predetermined time intervals and sequentially read out, but the reading of video file 1 is not completed before the start of reading the next video file 2 As shown in FIG. 9, the reading of the video file 1 overlaps with the reading period of the video file 2 and the data cannot be read normally for the portion exceeding the maximum transfer efficiency of 1.5 Mbps. Alternatively, processing such as suspending the screen until the reading of the video file 1 ends and restarting the display after the reading of the video file 1 is completed is performed.

In the fourth cycle, the data output device 10
Reads the block data C5 from the storage device 100 and temporarily stores it in the buffer memory 12c. Next, the block data D5 is read from the storage device 100 and temporarily stored in the buffer memory 12d. Data output device 20
Reads the block data A4 from the storage device 200 and temporarily stores it in the buffer memory 22a. Next, the block data B4 is read from the storage device 200 and temporarily stored in the buffer memory 22b. On the other hand, the data output device 10 outputs the block data A3 temporarily stored in the buffer memory 12a to the data receiving device 4a via the switch device 50, and outputs the data to the buffer memory 12b.
The block data B3 temporarily stored in the
b. The data output device 20 outputs the block data C4 temporarily stored in the buffer memory 22c to the data receiving device 4c via the switch device 50, and outputs the block data D4 temporarily stored in the buffer memory 22d to the data receiving device. Output to 4d.

In the subsequent cycles, the first to fourth data shown above are used.
In the same manner as in the cycle, each of the data output devices 10 and 20 reads the block to be read in that cycle, temporarily stores the read block in the assigned buffer memory, and then outputs it to each of the data receiving devices 4a to 4d in the next cycle. . This process is repeated until the end of the file. Thus, a buffer memory for reading from the storage devices 100 and 200,
By alternately switching the buffer memory for outputting data to the data receiving device, data can be output continuously even for files having various transfer rates. In order to output data to four data receiving devices, a buffer memory of 256 KB × 8 is required for each of the data output devices 10 and 20, and the total memory capacity of the entire system is 4M.
B.

[0011]

The conventional memory control device is configured as described above. By alternately switching between a buffer memory for reading and a buffer memory for outputting data to a data receiving device, various memory control devices are provided. Although the system was configured so that data could be output continuously even at the transfer rate file, the above configuration has the problem that the total capacity of the buffer memory increases and the cost of the entire system increases. was there. However, if you simply reduce the size of the buffer memory,
Although the cost as a system can be reduced, the storage device 10
The amount of data that can be read in one read process from 0 or 200 is reduced, the data read time is shortened, and the number of accesses to data performed to read data of the same capacity is increased. Storage devices 100, 2
00, a seek time, which is a moving time of a head for reading data from a disk, such as a generally used hard disk drive (HDD), and a waiting time until the storage area rotates near the head. There is a loss time such as time. Therefore, if the number of accesses is simply increased by reducing the size of the buffer memory as described above, the seek time and the loss time of the storage devices 100 and 200 occupy most of the period. The amount of data that can be read from the storage devices 100 and 200 decreases, and the data output device 1
Since the data output from 0 and 20 also decreases, a problem arises that the number of data receiving devices capable of outputting data decreases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has a memory control device capable of reducing the total capacity of a necessary buffer memory and reducing the number of data receiving devices capable of outputting data. The purpose is to provide.

[0013]

According to a first aspect of the present invention, there is provided a memory control device comprising: a storage device group including a plurality of storage devices for storing data; and a data transferred from the storage device group. And a plurality of data transfer paths each having a buffer memory group composed of a plurality of buffer memories for storing a file. One file is divided into a plurality of blocks of a predetermined size, and the blocks are respectively provided on different data transfer paths. A memory control device that performs control so that data is dispersed and stored in a plurality of storage devices, and data is read out from the storage device and output as needed in response to a request from a terminal connected to the buffer memory end. A plurality of virtual storage device groups are formed by selecting storage devices existing between them, and a buffer memory existing between the different data transfer paths is selected. A plurality of virtual buffer memory groups are formed, and in a first cycle, the data divided and stored in a predetermined virtual storage device group of the plurality of virtual storage device groups is read, and the plurality of virtual buffer memory groups are read out. While temporarily storing in a predetermined virtual buffer memory group of the memory group, and outputting data stored in a virtual buffer memory group different from the predetermined virtual buffer memory,
In the second cycle, data that is divided and stored in a virtual storage device group different from the predetermined virtual storage device group is read and temporarily stored in a virtual buffer memory group different from the predetermined virtual buffer memory group. At the same time, the data stored in the predetermined virtual buffer memory group is output, and the switching of the data read from the plurality of virtual buffer memory groups is controlled by alternately repeating the first cycle and the second cycle. It is provided with data output control means.

Further, the memory control device according to claim 2 is
2. The memory control device according to claim 1, wherein the data output control means collectively manages the plurality of buffer memories as free buffer memories, and one or more of the plurality of free buffer memories controls one of the plurality of free buffer memories. A virtual buffer memory group, and one or more free buffer memories that do not form the one virtual buffer memory group of the plurality of free buffer memories form another virtual buffer memory group; Of the buffer memories constituting the memory group, the buffer memories for which the output of the temporarily stored data has been finished are excluded from the buffer memories constituting the plurality of virtual buffer memory groups, and these are re-used as empty buffer memories. This is managed as a memory.

According to a third aspect of the present invention, there is provided the memory control device according to the first or second aspect, wherein a network interface circuit is connected to the buffer memory and the data is output from the data transfer path. The data is output to a network via the network interface circuit.

According to a fourth aspect of the present invention, there is provided the memory control device according to the first or second aspect, wherein a bus interface circuit is connected to the buffer memory and the data is output from the data transfer path. The data is output to a bus via the bus interface circuit.

According to a fifth aspect of the present invention, in the memory control device according to any one of the first to fourth aspects, a network is provided between the data output control means and the data transfer path. Connected.

A memory control device according to a sixth aspect of the present invention is the memory control device according to any one of the first to third aspects, wherein a bus is provided between the data output control means and the data transfer path. Connected.

According to a seventh aspect of the present invention, in the memory control device according to any one of the first to fourth aspects, a serial line is provided between the data output control means and the data transfer path. It is connected by.

According to an eighth aspect of the present invention, in the memory control apparatus according to any one of the fifth to seventh aspects, the data output control means includes a plurality of the plurality of data output control means for controlling the plurality of data output means within a specific error range. The synchronous control of the data output device is performed.

According to a ninth aspect of the present invention, in the memory control device according to any one of the fifth to seventh aspects, the data output control means includes a control command for the data output device. This is performed at regular intervals.

According to a tenth aspect of the present invention, in the memory control device according to the sixth aspect, the data output control means performs a control command for the data transfer path by DMA transfer. It was done.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 FIG. Hereinafter, a memory control device according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 1A is a conceptual diagram showing a configuration of a file A according to the first embodiment. In FIG. 1A, a file A is divided from its head into blocks a1, a2, a3,... Having a size of 1 KB. FIG. 1B is a block diagram showing the configuration of the memory control device according to the first embodiment. In FIG. 1, reference numerals 10 and 20 denote data output devices and 11a to 1a.
1d, 12a to 12d are buffer memories built in the data output device 10, 21a to 21d, 22a to 22d are buffer memories built in the data output device 20, 100,
101 is a storage device connected to the data output device 10, 20
0 and 201 are storage devices connected to the data output device 20,
110 is an interface circuit for controlling the storage devices 100 and 101; 210 is an interface circuit for controlling the storage devices 200 and 201; 4a to 4d are data reception devices for issuing data transfer requests; and 50 is data output devices 10 and 20
A switch device for connecting the data output from the data receiving devices 4a to 4d to the data receiving devices 4a to 4d;
, A virtual buffer memory group composed of buffer memories 11a and 21a, a virtual buffer memory group 72 composed of buffer memories 12a and 22a, and 81 a storage device 100, 20
0, a virtual storage device group 82,
This is a virtual storage device group composed of 1,201.

In the first embodiment, when the file A shown in FIG. 1A is stored in the storage devices 100, 101, 200, and 201, the first block a having a size of 256 KB is used.
1 to a256 are stored in the storage devices 100 and 200 constituting the virtual storage device group 81. At this time, 128 blocks a1, a3,..., A255 having odd-numbered numbers are grouped together into a block unit of 128 KB size.
00 and the even-numbered blocks a2, a4,
, A256 are collectively stored in the storage device 200 as a block unit having a size of 128 KB.

Then, the next 256K constituting the file A
The B-sized blocks a257 to a512 are stored in the storage devices 101 and 201 that constitute another virtual storage device group 82. At this time, the block a25 having an odd number is also used.
7, a259,..., A511 are 128
The blocks a 258, a 260,..., Which are stored in the storage device 101 as KB-size block units and have even-numbered blocks.
128 pieces of a512 are stored in the storage device 201 as a block unit having a size of 128 KB.

Block a5 constituting file A
In the same manner as above, the 13th and subsequent blocks are alternately stored in the virtual storage device groups 81 and 82 as 256 KB size block units. As described above, the storage devices 100 and 10
The operation of transmitting the data of the file A stored in 1, 200, 201 to the data receiving device 4a will be described below as an example.

In the first cycle, the data output devices 10,
Reference numeral 20 denotes the first 256 KB sized blocks a1 to a of the file A according to the control of the data output device control circuit 60.
256 is read from the virtual storage device group 81 and stored in the virtual buffer memory group 71. That is, the interface circuit 110 reads the blocks a1, a3,..., A255 from the storage device 100 and temporarily stores them in the buffer memory 11a.
, A256 are read from the storage device 200 and temporarily stored in the buffer memory 21a.

In the second cycle, the data output devices 10,
20, according to the control of the data output device control circuit 60,
Blocks a1 to a stored in virtual buffer memory group 71
256 is output. That is, the data output device 10 outputs the block a1 stored in the buffer memory 11a, and the data output device 20 outputs the block a2 stored in the buffer memory 21a.
Is a block a3 stored in the buffer memory 11a.
And the data output device 20 outputs the buffer memory 21a
And outputs the block a4 stored in. Thereafter, similarly, the data output devices 10 and 20 alternately store the blocks a5 and b5 stored in the buffer memories 11a and 21a.
.., A256 are output in the order of block numbers. As described above, the data of the blocks a1 to a256 output from the virtual buffer memory group 71 is transmitted to the data receiving device 4a via the switch device 50.

At the same time, in the second period, under the control of the data output device control circuit 60, the output devices 10 and 20 transfer the next 256 KB blocks a257 to a512 constituting the file A to another virtual storage device. The data is read out from the group 82 and is temporarily stored in another virtual buffer memory group 72 similarly to the above. That is, the interface circuit 110 includes the blocks a257, a259,.
Is read from the storage device 101 and the buffer memory 12a
And the interface circuit 210
, A512 are read from the storage device 201 and temporarily stored in the buffer memory 22a.

Then, in the third cycle, the data output devices 10 and 20 control the block a stored in the virtual buffer memory group 72 under the control of the data output device control circuit 60.
257 to a512 are output. Virtual buffer memory group 7
The data of blocks a257 to a512 output from 2 is transmitted to the data receiving device 4a via the switch device 50.

At the same time, in the third cycle, the data output devices 10 and 20 transmit the next 256 KB sized blocks a513 to a768 (not shown) constituting the file A under the control of the data output device control circuit 60 in the first cycle. Is read out from the virtual storage device group 81 and temporarily stored in the virtual buffer memory group 71.

Then, in the fourth period, the data output devices 10 and 20 operate under the control of the data output device control circuit 60 to store the blocks a stored in the virtual buffer memory group 71.
513 to a768 (not shown) are output. Blocks a513 to a7 output from virtual buffer memory group 71
The data 68 (not shown) is transmitted to the data receiving device 4a via the switch device 50.

At the same time, in the fourth period, the data output devices 10 and 20 store the next 256 KB size blocks a769 to a1024 (not shown) constituting the file A under the control of the data output device control circuit 60 in the virtual storage device. Read from the group 82 and the virtual buffer memory group 72
To be stored temporarily.

Similarly, in the fifth and subsequent cycles, the virtual storage device groups 81 and 82 for reading data in each period are sequentially switched between the virtual storage device group 81 and the virtual storage device group 82 and the data is stored. Alternatively, the virtual buffer memory groups 71 and 72 to be output are sequentially switched between the virtual buffer memory group 71 and the virtual buffer memory group 72.

As described above, in the memory control device according to the first embodiment, the data read from the virtual storage device group 81 is temporarily stored in the virtual buffer memory group 71 in the N-th cycle.
At the same time, the data already stored in the virtual buffer memory group 72 is output to the data receiving device 4a in the (N-1) th cycle, and is stored in the virtual buffer memory group 71 in the (N) th cycle in the next (N + 1) th cycle. The new data read from the virtual storage device group 82 is temporarily stored in the virtual buffer memory group 72 at the same time as outputting the data thus obtained to the data receiving device 4a. The virtual storage device groups 81 and 82 for reading data in this way, and the virtual buffer memory groups 71 and 7 for storing or outputting data.
2 is switched in each cycle, so that when transmitting any file data to the data receiving devices 4a to 4d, each of the data output devices 10 and 20 requires 120 KB ×
Since eight buffer memories are required, that is, the total memory capacity of the entire system is 2 MB, it is possible to reduce the total buffer memory capacity required.

Further, in the above configuration, when the maximum transfer efficiency is 75 Mbps and the number of connected clients is 100, when time t is 0, 50 client terminals send 1.5 Mbps (cycle time 1.3).
A request to read a video stream occurs at the rate of 3), and 1.3 Mbps is transmitted from the other 50 client terminals.
When a video stream read request occurs at a rate of (cycle time 1.54), the total bit rate G
In the first cycle (0 ≦ t <1.33), G1 (t) = 1.5 × 50 = 75 (Mbps) G2 (t) = 1.3 × 50 = 65 (Mbps) In the second cycle (1.33 ≦ t <1.54), G1 (t) = 0 (Mbps) G2 (t) = (1.3 + 1.5) × 50 = 140 (Mb)
ps) In the third cycle (1.54 ≦ t <2.66), G1 (t) = 1.3 × 50 = 65 (Mbps) G2 (t) = 1.5 × 50 = 75 (Mbps) Fourth In the period (2.66 ≦ t <3.08), G1 (t) = (1.3 + 1.5) × 50 = 140 (Mb
ps) G2 (t) = 0 (Mbps), and the total bit rate required in the second and fourth cycles exceeded the maximum transfer efficiency, making it impossible to perform continuous transfer. However, in the present embodiment, by performing transfer using the virtual storage device group and the virtual buffer memory group, G1 (t) = (1.5 / 2 + 1.3 / 2) × 50 = 70 in each cycle.
(Mbps) G2 (t) = (1.5 / 2 + 1.3 / 2) × 50 = 70
(Mbps), and is always constant and less than the maximum transfer efficiency (75 Mbps). Therefore, the transfer processing does not become difficult.
The video does not stop or drop off halfway.

Embodiment 2 Next, a memory control device according to the second embodiment will be described. As shown in FIG. 2, the memory control device according to the second embodiment has a virtual storage device group 81, 82 having an arbitrary number of three or more, and a virtual storage device group 81, 82,. The switching is performed sequentially in each cycle. If the number of virtual storage device groups is limited to two as in the first embodiment described above, the total storage capacity of the entire system cannot be easily increased. The reason will be described below.

For example, the storage devices 100, 101, 20
When a 3.5-inch hard disk drive (HDD) is used as 0,201, the capacity of the HDD has doubled in recent years, but still has a maximum capacity of 9 GB.
There is only DD. Four storage devices 1 as in the first embodiment
The system composed of 00, 101, 200, and 201 is a system having only a total storage capacity of 36 GB when an HDD having a capacity of 9 GB is used. 36G storage capacity
Consider the case where the system B stores, for example, a two-hour movie. Compressing a 2-hour movie with the moving picture compression format MPEG1 requires about 1.3 GB of storage capacity, and compressing with a moving picture compression format for high quality images such as S-VHS MPEG2 requires about 5.2 GB of storage capacity. , 36 GB storage capacity MPEG
1 can store only 27 movies, and MPEG2 can store only 6 movies. Therefore, it is necessary to increase the total storage capacity of the entire system. However, if the number of the virtual storage device groups 81 and 82 is limited to two as in the first embodiment, the storage devices 100, 101, 200, and Since there is an upper limit on the capacity of the single unit 201, it is not easy to increase the total storage capacity of the entire system.

Therefore, in order to increase the total storage capacity of the entire system, a method using a method of increasing the number of storage devices 100, 101, 200, 201 in the virtual storage device groups 81, 82 will be examined. Storage devices 100, 10
When the number of 1,200,201 is increased, one RAID (Redundant Arrayso
f Independent Disks). Here, RAID refers to writing (reading) data of a certain size to an HDD, instead of writing (reading) to a single HDD, dividing the data and writing (reading) to a plurality of HDDs in parallel. By itself, H
This is one type of storage device that can reduce the processing time compared to DD. However, according to this method, 1
There are a plurality of virtual storage device groups 81 and 82 that constitute one RAID, and the entire virtual storage device groups 81 and 82 are RA.
As a result, it is extremely complicated and impractical to integrally control a plurality of RAIDs.

Therefore, in the second embodiment, as shown in FIG. 2, the number of virtual storage device groups 81 and 82 is set to an arbitrary number of 3 or more, and a plurality of virtual storage device groups 81, 82,.
Since 8n is sequentially switched for each cycle to read data, an effect is obtained that the total storage capacity of the entire system can be easily increased.

Embodiment 3 Next, a memory control device according to the third embodiment will be described. As shown in FIG. 3, the memory control device according to the third embodiment sets the number of virtual buffer memory groups to an arbitrary number equal to or more than three, and temporarily stores data and a virtual buffer memory group 7n-1 (7n) for outputting data. And a virtual buffer memory group 7n (7n-1)
The switching is sequentially performed in each cycle.

If the number of virtual buffer memory groups is limited to two as in the first embodiment, flexible handling is possible when there is a variation in the data transmission rate to the data receiving devices 4a to 4d. Can not. The reason will be described below.

The data transmission rate when outputting data from the virtual buffer memory groups 71 and 72 is equal to the upper limit (MPEG) of the average data transmission rate of various moving image compression formats.
1.5 Mbps for 1 and 6 Mbps for MPEG2
ps), at the end of the Nth cycle,
Since data that has not yet been output remains in the virtual buffer memory group 71 (72), the next data to be stored in the virtual buffer memory group 71 (72) cannot be read. In this case, the next data is read after the (N + 1) th cycle. The data remaining in the virtual buffer memory group 71 (72) and another virtual buffer memory group 72 (7
If the output of the data stored in 1) cannot be continued, the video will be interrupted. If the data transmission rate at the time of output from the virtual buffer memory group is higher than the upper limit of the average data transmission rate of the various moving image compression formats, the data of the virtual buffer memory groups 71 and 72 must be set before the end of the Nth cycle. Output is completed, and the video is interrupted.

Therefore, in the third embodiment, the number of virtual buffer memory groups 71, 72 is set to an arbitrary number of 3 or more, and a plurality of virtual buffer memory groups 71, 72,.
−1 and 7n are sequentially switched in each cycle to store and output data, so that it is possible to flexibly cope with a fluctuation in the data transmission rate to the data receiving apparatus. can get.

Embodiment 4 Next, a memory control device according to the fourth embodiment will be described. The memory control device according to the fourth embodiment manages the buffer memories 11a to 12d and 21a to 22d as empty buffer memories in the configuration of FIG. 1 and temporarily stores data when temporarily storing data. , 21a-22
d, the required buffer memory is taken out and managed as a virtual buffer memory group 71 (72). When data output is completed, even in the middle of the N-th cycle, the buffer memory 11a is output from the virtual buffer memory group 71 (72). , 21a
(12a, 22a) is taken out and managed again as a free buffer memory. The data output device control circuit 60 manages such a buffer memory.

For example, an operation for transmitting the data of the file A to the data receiving device 4a will be described. First
In the cycle, the data output device control circuit 60 takes out the buffer memories 11a and 21a from the empty buffer memories 11a to 12d and 21a to 22d to form a virtual buffer memory group 71. And data output devices 10 and 20
.., A255 are read from the virtual storage device group 81 and temporarily stored in the buffer 11a under the control of the data output device control circuit 60, and a2,.
Is read and temporarily stored in the buffer 21a.
A buffer memory management table corresponding to each of the data output devices 10 and 20 exists inside the data output device control circuit 60, and the data output device control circuit 60 manages the buffer memory according to the management table. .

In the second cycle, the data output devices 10, 2
0 indicates a virtual buffer memory group 71 (buffer memories 11a and 21a) according to the control of the data output device control circuit 60.
The data temporarily stored in a) is output to the data receiving device 4a. When the output of the data from the virtual buffer memory group 71 is completed, the data output device control circuit 60 returns from the virtual buffer memory group 71 to the empty buffer memory 11.
a and 21a are released, and the free buffer memory 11
a and 21a.

At the same time, in the second cycle, the data output device control circuit 60 sets the empty buffer memories 11a to 11a to 1
2d, 21a to 22d to buffer memories 12a, 22
The virtual buffer memory group 72 is constructed by extracting “a”.
Then, the data output devices 10 and 20 transmit a2 from the virtual storage device group 82 under the control of the data output device control circuit 60.
57,..., And a511,
, a512, and the data of a258,..., a512 is read out and temporarily stored in the buffer 22a.

In the third and subsequent cycles, the data read from the virtual storage device group 81 (82) is extracted from the free buffer memory and stored in the virtual buffer memory in the same manner as the operations in the first and second cycles. Memory group 71 (7
2) and managed by another virtual buffer memory group 72 (7
When outputting the data stored in 1) to the data receiving device 4a, the virtual buffer memory group 72 (71) is released when the data is output, and is managed as a free buffer memory group.

In the above operation, when the data of the file A is transmitted to the data receiving device 4a and the files B, C, and D are also transmitted to the data receiving devices 4b to 4d, the files other than the virtual buffer memory groups 71 and 72 are used. Since the buffer memories are managed as free buffer memories, free buffer memories other than the virtual buffer memory groups 71 and 72 can be used as virtual buffer memory groups for files B, C and D.

As described above, according to the memory control device according to the fourth embodiment, the data output device control circuit manages the buffer memory as a free buffer memory or a virtual buffer memory group, so that a plurality of data can be simultaneously stored in a plurality of data. When transmitting data to the data receiving device, the free buffer memory other than the virtual buffer memory group for a certain file can be used as a virtual buffer memory group for another file. Even in a different case, the effect that the total capacity of the buffer memory can be reduced can be obtained.

Embodiment 5 FIG. Next, a memory control device according to the fifth embodiment will be described. The configuration of the memory control device according to the fifth embodiment is such that, as shown in FIG. 4, a network interface circuit 500 is connected to a DRAM 700 as a buffer memory, and the buffer memory 700 is connected to the DRAM 700 via the network interface circuit 500. The temporarily stored data is transmitted to a local area network (LAN) or a wide area network (WAN). Here, the network means a general term for computer networks, and the network standards include Ethernet.
t (10Base-2 / 5/5), FastEther
net (100Base-TX / T4), Token-
Ring, 100VG-AnyLAN, FDDI, AT
M etc.

As described above, according to the memory control device of the fifth embodiment, the network interface circuit 500 is connected to the buffer memory 700, so that an existing computer network line can be used for data transmission. This makes it possible to easily transmit data to data receiving devices all over the world.

Embodiment 6 FIG. Next, Embodiment 6 of the present invention
Will be described. As shown in FIG. 4, the memory control device according to the sixth embodiment stores a bus interface circuit (I / O bus br) in the buffer memory 700.
idge ASIC) 501 is connected. That is, via the bus interface circuit 501, data temporarily stored in the buffer memories 11a to 12d and 21a to 22d is transferred to a general-purpose SBus, PCI
The data is transmitted to a bus, an EISA bus, or the like.

Here, the bus means three or more ICs and LSIs.
Are a plurality of data lines that can be connected to the data line, and input and output data having the same bit width as the number of data lines. It is usually called a data bus or an address bus depending on the type of data to be transferred, or a system bus (CPU bus) or I / O (Input / Output) depending on the internal configuration of the computer.
Output Bus) Also called a bus. There are a number of standards for buses, and the well-known I / O bus alone
NUbus of Macintosh of the United States and Sun Bus of Sun Microsystems of the United States.
Such as VME bus, DOS / VPC which is used for control system as a general-purpose bus
(8 bits), AT (= ISA, 16
bit), EISA (32 bit), PCI (32 bi
There are buses such as t). These buses are connected to a disk control circuit, a network control circuit, and the like, and are often used to transfer data from the outside to the inside of the computer.

As described above, according to the memory control device of the sixth embodiment, the bus interface circuit 501 is connected to the buffer memory 700, so that data transfer to the data receiving device having the same type of bus interface circuit is performed. Transfer speed is higher than modem (28Kbit / sec) and network (100-150Mbit / sec)
The speed becomes extremely high (250 to 320 Mbit / sec), and the effect that high-quality images can be transmitted is obtained.

Embodiment 7 FIG. Next, a memory control device according to the seventh embodiment will be described. As shown in FIG. 4, the memory control device according to the seventh embodiment includes a data output device control circuit (here, UNIX Workstati).
on 502) and the data output devices 10 and 20
The network is connected by a network 503 such as N or WAN. That is, the network interface circuit 504 and the network protocol creating / analyzing device (here, the UNIX workstation 502 is provided) are provided in the UNIX work station 502, which is a data output device control circuit, and the data output devices 10 and 20, respectively.
3 to enable communication between the data output device control circuit and the data output device by data transfer using a network protocol.

As described above, according to the memory control device of the seventh embodiment, since the data output device control circuit and the data output device are connected by the network 503, the data output device control circuit and the data output device are connected. The effect that it becomes possible to install an apparatus in a distant place, such as a different room or a different building, is acquired.

Embodiment 8 FIG. Next, a memory control device according to the eighth embodiment will be described. As shown in FIG. 4, the memory control device according to the eighth embodiment is a UNIX workstation 5 which is a data output device control circuit.
02 and the data output devices 10 and 20 are connected by SBus, P
The connection is made by a bus 505 such as a CI bus or an EISA bus. That is, a UNIX interface 502 serving as a data output device control circuit and a bus interface circuit 501 are provided for the data output devices 10 and 20, respectively, and the bus interface circuit 501 is connected between the bus interface circuits 501 by a bus cable 505.
The communication between the kstation 502 and the data output devices 10 and 20 is enabled by the bus 505.

As described above, according to the memory control device of the eighth embodiment, the data output device control circuit UN
Since the IX Workstation 502 and the data output devices 10 and 20 are connected by the bus 505, the data transfer rate of the bus 505 is more than twice as fast as that of the serial connection or the network connection. The data can be sent from the data output device control circuit to the data output device, and the effect of increasing the number of data receiving devices can be obtained.

Embodiment 9 FIG. Next, Embodiment 9 of the present invention
Will be described. The memory control device according to the ninth embodiment includes, as shown in FIG.
On 502 and the data output devices 10 and 20 are connected by a serial cable 506. That is, UNIX Wor which is a data output device control circuit
kstation 502 and the data output devices 10 and 20 respectively have a serial interface circuit (I / O bridge ASI).
C), and a serial cable 50
6 and a data output device control circuit UN
The IX Workstation 502 and the data output devices 10 and 20 can communicate with each other via a serial cable 506.

As described in the seventh embodiment, the UNIX work-state, which is a data output device control circuit, is used.
When n502 and the data output devices 10 and 20 are connected via the network 500, a protocol header must be added to each data to be transferred, so that protocol processing is required later. The protocol header includes an ID number (a number is sequentially added to each data to be transferred), a transfer destination address (information indicating a data transfer destination),
Various information such as a transfer source address (information indicating the transfer source of the data) and a checksum (information for checking whether the transferred data is correct) are included. A protocol header of about 100 bytes is added. Therefore, if data of 53 Mbps (53 Mbps per second) is transferred by a general workstation (equivalent to SPARC Station 5 manufactured by Sun), about 40% of the CPU usage rate is required for protocol processing. Therefore, in the ninth embodiment, by using the transfer by the serial cable 506 for the data transfer, the protocol processing becomes unnecessary and the CPU is not used.
Usage rate can be reduced.

As described above, according to the memory control device of the ninth embodiment, the data output device control circuit UN
Since the IX Workstation 502 and the data output devices 10 and 20 are connected by the serial cable 506, the data output device control circuit UNIX
Workstation 502 and data output device 1
0 and 20 can be arranged at a distance of about 10 meters. In addition, since protocol processing as in the case of connection via a network is not required, the usage rate of the data output device control circuit decreases, and as a result, the usage rate of the data output device can be reduced. Furthermore, by using the serial cable 506, system construction can be performed at a lower cost than when a network is constructed.

Embodiment 10 FIG. Next, a memory control device according to the tenth embodiment will be described. Embodiment 1
The data output device control circuit constituting the memory control device with 0 controls the synchronization of the plurality of data output devices 10 and 20 within a specific error range. The reason will be described below.

For example, in the memory control device having the configuration as shown in FIG. 1, when the data output devices 10 and 20 and the data receiving devices 4a to 4d are connected by a network, Ethernet is a standard network. It is used. When transferring data, the Ethernet divides the data into packets of a specific size (1.5 KB or less). Data output device 10, 20
Ethernet between the data receiving devices 4a to 4d
When transmitting MPEG1 video to the data receiving device 4a by connecting the data, it is necessary to transmit 1.5 Mbits of data per second. Therefore, in the case of a 1 KB packet, a total of 192 packets are output from the plurality of data output devices 10 and 20. Is output to the data receiving devices 4a to 4d. When data is alternately output from the two data output devices 10 and 20, each data output device 10 and 20 outputs 96 packets per second, in other words, outputs packets to the data receiving device 4a every 10.4 ms. In order for the data receiving device 4a to continuously reproduce video, one data output device 10 (20)
It is necessary to receive the packet output by another data output device 20 (10) 5.2 ms after receiving the packet output by the other data output device 20 (10). That is, if the arrival of the packet at the data receiving device 4a exceeds 5.2 ms, continuous video reproduction cannot be guaranteed.

For the above reason, by controlling the synchronization of the plurality of data output devices 10 and 20 within the range of 5.2 ms or less, the arrival interval of packets to the data receiving device 4a can be controlled. It is possible to guarantee continuous reproduction of data in the data receiving device 4a.

In the memory control device according to the tenth embodiment, when the system settings such as the moving image compression format, the type of network, and the number of data output devices change, the error range of the synchronous control of the data output devices 10 and 20 also increases. It will be different. This example will be described next.

First, it is assumed that the setting of the moving image compression format has changed. Since the compression ratio of the video file differs depending on the moving image compression format, the data transfer rate required for reproduction differs even if the same video is compressed. For example, the data transfer rate of MPEG1 is 1.2 to 1.5 Mbps, and that of MPEG2 is 4.0.
６6.0 Mbps. If the data transfer rate is different, the required data transfer amount per second changes, so that the error range of the synchronization control of the data output devices 10 and 20 also changes.

Next, it is assumed that the network settings have changed. In the computer network according to the tenth embodiment, a combination of NFS, Ethernet, and the like is assumed. If the terminal is NFS (Ver 2.0), it makes a request at 8 KB, but Ethernet only recognizes packets of 1.5 KB or less, so at least 6 (1.5 KB × 5, 0.5 KB × 1) Respond by dividing into packets. However, since the number of data output devices is assumed to be 2, 4 or 8 in the tenth embodiment, a response is made of 1 KB × 8 in order to equalize the packet size. When this becomes NFS (Ver 3.0), a request of 32 KB or more becomes possible, so that it is necessary to respond with 1 KB × 64 requests. So, if we replace Ethernet with FDDI, which is a faster network,
In DDI, the maximum packet size is recognized up to 4.5 KB, so that a response is made of 2 KB × 32 packets and 4 KB × 16 packets. As described above, since the number of packets to be transmitted per second changes depending on the packet size, the error range of the synchronization control of the data output devices 10 and 20 also changes.

It is further assumed that the number of data output devices 10 and 20 has changed. For example, the request from the terminal is 8KB
Then, when replying with eight data output devices, it is sufficient to reply with one 1 KB packet from each data output device. However, when replying with four data output devices, it is necessary to reply with two 1 KB packets. As described above, since the number of packets to be transmitted changes due to the change in the number of data output devices 10 and 20, the data output device 1
The error range of the synchronous control of 0, 20 also changes.

As described above, when the system settings such as the moving image compression format, the type of network, and the number of data output devices change, the error range of the synchronization control of the data output devices 10 and 20 also changes. In this case, the error range may be set.

As described above, according to the memory control device of the tenth embodiment, the synchronization control of a plurality of data output devices is performed within a specific error range. Since the control can be performed, an effect is obtained that the data can be reproduced continuously without interruption in the data receiving device.

Embodiment 11 FIG. Next, a memory control device according to an eleventh embodiment of the present invention will be described. The data output device control circuit constituting the memory control device according to the eleventh embodiment is configured to send control commands to the data output devices 10 and 20 collectively. However, the time for collecting the control commands must be shorter than the interval at which each of the data output devices 10 and 20 outputs a packet to the data receiving devices 4a to 4b. For example, if the tenth embodiment is taken as an example, it is necessary to reduce the time for grouping control commands to 5.2 ms or less.

As described above, according to the memory control device of the eleventh embodiment, since the control commands to the data output device are sent together, the load on the data output device control circuit can be reduced. Become.

Embodiment 12 FIG. Next, a memory control device according to a twelfth embodiment of the present invention will be described. The data output device control circuit constituting the memory control device according to the twelfth embodiment is configured to send a control command to the data output devices 10 and 20 by DMA (Direct Memory Access). As in the above-described seventh embodiment, a data output device control circuit (UNIX Workstation 502)
When the data output devices 10 and 20 are connected using, for example, an SBus, the data output device control circuit (UNI
Since the X Workstation 502 has a built-in arithmetic circuit such as a CPU, the data output device control circuit (UNIX Workstation 502) uses this arithmetic device to provide the data output devices 10 and 20 with three data output devices.
It is necessary to send a transfer instruction by 2 bits (the data width of the SBus), and the data output device control circuit (UNIX Wor)
kstation 502). Therefore, in the twelfth embodiment, the DMA transfer control device 502a is connected to the data output device control circuit (UNIX).
Workstation 502), and a memory area for storing the transfer instruction by the arithmetic unit is set to DMA.
The transfer control device is notified and a transfer command is sent to the data output device through the DMA transfer control device 502a.

As described above, according to the memory control device of the twelfth embodiment, the control command to the data output device is
Since the transmission is performed by MA, the load of the arithmetic processing of the data output device control circuit can be reduced.

[0077]

As described above, according to the memory control device of the present invention, the virtual buffer memory group is switched to the data storage virtual buffer memory group and the data output virtual buffer memory group at each cycle. Since it is used, the total capacity of the buffer memory of the data output device can be reduced.

Further, even if the number of virtual storage devices is three or more, or the number of virtual buffer memories is managed as a free buffer memory, the total capacity of the buffer memory can be reduced. .

Further, by setting the number of virtual buffer memory groups to an arbitrary number of three or more, it is possible to cope with a case where the data transmission rate to the data receiving apparatus fluctuates.

Further, by connecting the network interface circuit to the buffer memory, there is an effect that data can be easily transmitted to remote data receiving devices all over the world.

Further, by connecting a bus interface circuit to the buffer memory, there is an effect that high-speed and high-quality video can be transmitted.

Further, by connecting the data output control means and the data transfer path via a network, it is possible to install the data output control means and the data transfer path in different places such as different buildings.

Further, by connecting the data output control means and the data transfer path with a bus, more control commands can be sent from the data output control means to the data transfer path within a certain period of time. There is an effect that the number can be increased.

Further, by serially connecting the data output control means and the data transfer path, the data output control means and the data transfer path can be arranged at a distance of about 10 meters from each other. And the use rate of the data transfer path can be reduced.

Further, by performing synchronous control of a plurality of data transfer paths within a specific error range, there is an effect that data in the data receiving apparatus can be continuously reproduced without interruption.

Further, by transmitting the control commands to the data output device collectively to the data transfer path, the load on the data output control means can be reduced.

Further, by transmitting a control command from the data output control means to the data transfer path by DMA, there is an effect that it is possible to reduce the processing load of the data output control means.

As described above, the memory control device of the present invention
The effect is that the total capacity of the buffer memory can be reduced without reducing the number of data receiving devices, and the system design and control method can be adaptively changed as necessary, so that its practical effects Has the effect that it becomes enormous.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a file A in a memory control device according to a first embodiment of the present invention (FIG. 1A), and memory control according to the first embodiment and the fourth, tenth, and eleventh embodiments; FIG. 2 is a block diagram showing the configuration of the device (FIG. 1)
(b)).

FIG. 2 is a block diagram showing a configuration of a memory control device according to a second embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a memory control device according to a third embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a memory control device according to Embodiments 5 to 9 and 12 of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional memory control device.

FIG. 6 is a diagram showing a configuration of a file in a conventional memory control device.

FIG. 7 is a diagram showing a relationship between data reading from a storage device and data output to a data receiving device in each cycle in a conventional memory control device.

FIG. 8 is a diagram for explaining a state of normal data transfer by the conventional memory control device.

FIG. 9 is a diagram for explaining a state of data transfer by the conventional memory control device when the data transfer is not normal.

[Explanation of symbols]

1 file A 2 block A1 obtained by dividing file A 3 block A2 obtained by dividing file A 4a, 4b, 4c, 4d Data receiving device 10, 20 Data output device 11a, 11b, 11c, 11d, 12a, 12b, 1
2c, 12d, 21a, 21b, 21c, 21d, 22
a, 22b, 22c, 22d Buffer memory 50 Switch device 60 Data output device control circuit 71, 72 Virtual buffer memory group 81, 82 Virtual storage device group 100, 101, 200, 201 Storage device 110, 210 Interface circuit

Claims (10)

[Claims] 1. A data transfer system comprising: a storage device group including a plurality of storage devices for storing data; and a buffer memory group including a plurality of buffer memories for storing data transferred from the storage device group. One file is divided into a plurality of blocks of a predetermined size having a plurality of paths, which are divided and stored in a plurality of storage devices existing in different data transfer paths, and connected to the end of the buffer memory. A memory control device that performs control to read and output data from the storage device as appropriate in response to a request from the terminal, wherein a plurality of virtual storage device groups are selected by selecting storage devices existing between the different data transfer paths. Forming a plurality of virtual buffer memory groups by selecting a buffer memory existing between the different data transfer paths; Reading the data divided and stored in a predetermined virtual storage device group of the plurality of virtual storage device groups and temporarily storing the data in a predetermined virtual buffer memory group of the plurality of virtual buffer memory groups Output the data stored in a virtual buffer memory group different from the predetermined virtual buffer memory, and in a second cycle, divide and store the data in a virtual storage device group different from the predetermined virtual storage device group Read out the stored data, temporarily store the data in a virtual buffer memory group different from the predetermined virtual buffer memory group, and output the data stored in the predetermined virtual buffer memory group. Data for controlling switching of data read from the plurality of virtual buffer memory groups by alternately repeating the second cycle. Memory control apparatus characterized by comprising a force control means. 2. The memory control device according to claim 1, wherein the data output control means collectively manages the plurality of buffer memories as a free buffer memory, and one or more of the plurality of free buffer memories. One virtual buffer memory group is configured by the buffer memory, and another virtual buffer memory group is configured by one or more free buffer memories that do not configure the one virtual buffer memory group of the plurality of free buffer memories; Among the buffer memories constituting the plurality of virtual buffer memory groups, the buffer memories for which temporarily stored data has been output are excluded from the buffer memories constituting the plurality of virtual buffer memory groups, A memory control device for managing these as an empty buffer memory again. 3. The memory control device according to claim 1, wherein a network interface circuit is connected to the buffer memory, and the data output from the data transfer path is transmitted through the network interface circuit.
A memory controller configured to output to a network. 4. The memory control device according to claim 1, wherein a bus interface circuit is connected to said buffer memory, and said data output from said data transfer path is transmitted to said buffer memory.
A memory control device, wherein the data is output to a bus via the bus interface circuit. 5. The memory control device according to claim 1, wherein said data output control means and said data transfer path are connected by a network. 6. The memory control device according to claim 1, wherein said data output control means and said data transfer path are connected by a bus. 7. The memory control device according to claim 1, wherein said data output control means and said data transfer path are connected by a serial line. 8. The memory control device according to claim 5, wherein said data output control means performs synchronous control of said plurality of data output devices within a specific error range. Memory control device. 9. The memory control device according to claim 5, wherein said data output control means executes a control command for said data transfer path at regular time intervals. Control device. 10. The memory control device according to claim 6, wherein said data output control means executes a control command for said data transfer path by DMA transfer.