JPH10153985A - Sample-and-hold method for liquid crystal display device and system therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To dissolve degradation of picture quality caused by stripes every plural pixels. SOLUTION: Clocks SH1, SH2, SH3 are clocks to be a high level for a fixed time in order, a video signal DAT is successively subjected to sample-and-hold synchronizing with the clocks SH1, SH2, SH3 with different timing in sample- and-hold circuits 42, 44, 46. Second sample-and-hold circuits 48, 50, 52 sample and hold output signals of the first sample-and-hold circuits, but the second sample-and-hold circuits 48, 50 synchronizes with the clock SH3, and the second sample-and-hold circuit 52 synchronizes with the clock SH1 and they performs sample-and-hold, and a video signal is simultaneously outputted to a liquid crystal display device 12 in the prescribed period. Thereby, each video signals are surely subjected to sample-and-hold two times, and errors between video signals are uniformalized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold method and system for a liquid crystal display device, and more particularly, to a sample and hold method for a liquid crystal display device of a multi-dot simultaneous sampling type, in which a video signal corresponding to each of a plurality of continuous pixels is sampled and held. The present invention relates to a method and system for sample and hold of a liquid crystal display device which is supplied simultaneously.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing an example of a conventional liquid crystal display device of a multi-dot simultaneous sampling system. First, a conventional liquid crystal display device will be described with reference to FIG. The liquid crystal display device 12 shown in FIG. 3 includes, on a substrate 14, a large number of pixel elements 16 corresponding to each pixel of a display image,
An H shift register 18, a V shift register 20, an H switch element 22, a V switch element 24 and the like are arranged. The pixel elements 16 are arranged in a matrix (only a part is shown in the figure) and each includes a capacitor 26. By storing a video signal in the capacitor 26, the optical transmittance of the liquid crystal cell of each pixel element 16 is reduced. It changes to form an image. One terminal of each capacitor 26 is connected to the common electrode 28.

A V-switch element 24 is provided for each pixel element 16. When the V-switch element 24 is turned on, a video signal is supplied to a capacitor 26 of each pixel element 16. Further, the control terminals of the V switch elements 24 are commonly connected to each row, so that the ON / OFF control of the V switch elements 24 of each row is performed collectively.

The V shift register 20 supplies switch pulses PV1 to PVp (p is a positive integer) for sequentially turning on the V switch elements 24 for each row to each V switch element 24. The V shift register 20 has a configuration in which a V start pulse 30 is externally input through a V input terminal 32. When the V start pulse 30 is input, the V shift register 20 is also supplied from the outside. In synchronization with the V clock VCK, switch pulses PV1 to PVp for turning on the V switch elements 24 in each row are sequentially turned on at regular time intervals from the V switch elements 24 in the first row (the top row in the drawing). It is supplied to the V switch element 24.

In this liquid crystal display device 12, a video signal is simultaneously supplied to adjacent pixel elements 16 in n columns (n is a positive integer). Therefore, the H switch elements 22 are provided for every n columns,
2 turns on, the video signal V supplied simultaneously from the outside
1 to Vn are supplied to the corresponding n columns of pixel elements 16 through the H switch element 22.

The ON / OFF of each H switch element 22 is controlled by an H shift register 18. The H shift register 18 outputs switch pulses PH1 to PHm (m is a positive integer) for sequentially turning on the H switch elements 22 for each H.
It is supplied to the switch element 22. The H shift register 18 has a configuration in which an H start pulse 34 is externally input through an H input terminal 36. When the H start pulse 34 is input, the H shift register 18 is similarly supplied from the outside. In synchronization with the H clock HCK, the pixel element 1
H corresponding to the first n columns (the leftmost n columns in the figure)
A switch pulse PH for sequentially turning on the H switch element 22 at a constant time interval from the switch element 22
1 to PHm are supplied to the H switch element 22.

FIG. 4 is a block diagram showing a pre-processing unit for a video signal. This part includes an RGB driver 38 and a sample and hold system 40 (S / H system). After the video signal is processed by the RGB driver 38 and further sampled and held by the sample and hold system 40,
It is supplied to the liquid crystal display (LCD) 12.

The RGB driver 38 has a luminance adjustment signal BR
T, the gain adjustment signal GAIN, and the gamma correction signal GAMMA are input, and the RGB driver 38 performs processing for brightness and gain adjustment on the video signal V0 based on these signals, and further performs gamma correction. .

Further, the video signal is transmitted to the RGB driver 3
At 8, an AC signal is generated for driving the liquid crystal by the AC driving pulse Pac. FIGS. 5A and 5B show a video signal input to the RGB driver 38 and a video signal output from the RGB driver 38, respectively. The video signal input to the RGB driver 38 as a DC signal as shown in FIG. 5A is output as an up-down symmetric AC signal as shown in FIG. 5B.

FIG. 6 is a block diagram showing the sample and hold system 40 in detail. The sample and hold system 40 is a liquid crystal display device 12 configured to simultaneously supply video signals to three pixel elements 16 (in the case of n = 3 in FIG. 3).
And comprises three first sample and hold circuits 42, 44 and 46 and three second sample and hold circuits 48, 50 and 52. And
The video signal from the RGB driver 38 is commonly input to the three first sample and hold circuits 42, 44 and 46, and the output signals of the first sample and hold circuits 42, 44 and 46 are three second sample and hold circuits, respectively. Circuits 48, 5
0 and 52 are input.

FIG. 7 shows this sample and hold system 40.
7 is a timing chart showing the operation of the first sample hold circuit 42, 44. The clocks SH1, SH2 shown in FIG.
, A high level signal HIGH is always input instead of the sample and hold clock. The second sample-and-hold circuits 48, 50 and 52 all receive the clock S
H3 is input as a sample and hold clock. The video signal DATA input to the sample-and-hold system 40 includes signals a, b, c,... (The time width is T) corresponding to the pixels arranged continuously in the horizontal direction in the order of elapse of time. It has an arrayed form.

The clocks SH1, SH2, SH3 are shown in FIG.
As shown in the figure, the level sequentially becomes high in this order, and the period is time T. In addition, the repetition period of the high level is 3T corresponding to three consecutive pixels. The H clock HCK is a clock that switches between a high level and a low level every 3T, and this clock is supplied to the H shift register 18 shown in FIG.

First, the first sample and hold circuit 42 starts sampling the signal a of the video signal DATA at the rising edge of the clock SH1, and holds the signal a at the falling edge. Similarly, the first sample and hold circuit 44
Starts sampling the signal b of the video signal DATA at the rising edge of the clock SH2, and holds the signal b at the falling edge. On the other hand, the first sample and hold circuit 46
Is always supplied with the high level signal HIGH, the first sample and hold circuit 46 outputs the video signal DAT.
A is always output.

As a result of the first sample and hold circuits 42 and 44 operating as described above based on the clocks SH1 and SH2, the first sample and hold circuit 42 converts the signals a, d, and g as the video signal A1 in FIG. And the first sample and hold circuit 44 sequentially outputs the signals b, e, and h as the video signal B1 at the timing as shown in FIG. Then the second
Sample-and-hold circuits 48, 50, and 52 start sampling the output signals of the first sample-and-hold circuits 42, 44, and 46 at the rising edge of the clock SH3, respectively.
Each signal is held at the falling edge. As a result, during the period from the fall of the clock SH3 to the next rise, the second sample and hold circuits 48, 5
Signals a, b, c, d, e, f, g, h, and i are simultaneously output from 0 and 52 as video signals V1, V2, and V3, respectively, as shown in the figure, and supplied to the liquid crystal display device 12. Then, it is input to each H switch element 22.

Although the case where the video signal is supplied to the three pixel elements 16 at the same time has been described above, the configuration and operation of the sample-and-hold system can be performed even when the number of the pixel elements 16 that simultaneously supply the video signal is large. Is basically the same. FIG. 8 is a block diagram showing a sample and hold system 54 for simultaneously supplying a video signal to n pixel elements 16, and FIG. 9 is a timing chart showing the operation of the sample and hold system 54. This system is configured by adding n-3 sample and hold circuits as first and second sample and hold circuits to the sample and hold system 40, respectively. , Except for the last first sample and hold circuit 56, a clock whose high-level timing is shifted by time T is supplied as a sample and hold clock.
The sample-and-hold circuit 56 is always supplied with a high-level signal HIGH. Further, the clock SHn which is at the highest level last is supplied to all the added second sample and hold circuits.

[0016]

However, when such a conventional sample and hold system 40 is used, FIG.
As shown in (1), a high-level signal is always supplied to the first sample and hold circuit 46, and the video signal passes through the first sample and hold circuit 46 and is supplied to the second sample and hold circuit 52. Therefore, while the video signal supplied to the liquid crystal display device 12 through the first sample and hold circuits 42 and 44 and the second sample and hold circuits 48 and 50 is sampled and held twice, the first sample and hold circuit The video signal supplied to the liquid crystal display device 12 through the circuit 46 and the second sample and hold circuit 52 is sampled and held only once.

The sample and hold circuit cannot normally sample and hold the original signal at all, and the level of the sampled and held signal contains some error. Therefore, assuming that an error generated by one sample-and-hold is ΔV, the video signal supplied through the first and second sample-and-hold circuits 42, 44, 48, and 50 includes an error of 2ΔV.
And the video signal supplied through the second sample and hold circuits 46 and 52 contains only an error of ΔV. The difference between the error components is determined by the liquid crystal display device 12.
In the displayed image, for example, vertical stripes appear due to a luminance difference for every three pixels, for example, which causes deterioration in image quality.

Of course, such a problem also occurs when the number of pixel elements 16 that simultaneously supply video signals is large. In the example of FIG. 8, the first to n-1st video signals V1 to V1 are output.
While Vn-1 is sampled and held twice,
The n-th video signal Vn is sampled and held only once, and its effect appears in a display image as, for example, vertical streaks every n pixels. SUMMARY OF THE INVENTION It is an object of the present invention to provide a sample and hold method and system for a liquid crystal display device that can eliminate such image quality deterioration due to streaks of a plurality of pixels.

[0019]

According to the present invention, in order to achieve the above object, the present invention provides:
The video signals are sampled and held in sequence at different timings corresponding to the plurality of pixels, respectively, by the same number of first sample hold units as the plurality of pixels, and the same number of second sample hold units as the plurality of pixels are used. ,
When the output signal of the first sample-and-hold means is sampled and held in the cycle and supplied to the liquid crystal display device, and sampled and held by the second sample-and-hold means, the video signal is firstly output in the cycle. The output signal of the first sample and hold means for sampling and holding is sampled and held at the same timing as the first sample and hold means for sampling and holding the video signal last in the cycle, and The output signal of the first sample and hold means that samples and holds last is sampled and held at the same timing as the first sample and hold means that samples and holds the video signal first within the period. .

According to the present invention, the same number of the first pixels as the plurality of pixels are sampled and held in sequence at a different timing corresponding to each of the plurality of pixels in each cycle corresponding to the plurality of continuous pixels. Sample-and-hold means, and the same number of second sample-and-hold means as the plurality of pixels, each of which samples and holds the output signal of the first sample-and-hold means in the period and supplies the output signals to a liquid crystal display device. The second sample-and-hold means samples and holds the video signal first in the cycle. The output signal of the first sample-and-hold means samples and holds the video signal last in the cycle. Sample and hold at the same timing as the sample and hold means of The output signal of sul said first sample and hold means, characterized by sample-and-hold at the same timing as the first sample and hold means first sampling and holding said video signal in said period.

According to the present invention, a plurality of video signals simultaneously supplied to the liquid crystal display device are always sampled and held twice before being supplied to the liquid crystal display device. Is the same for any video signal. Therefore, when the video signal generated according to the present invention is used, a streak of a plurality of pixels does not appear in a display image as in the related art, and good image quality can be realized.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described based on embodiments with reference to the drawings. FIG. 1 is a block diagram showing an example of a sample and hold system of a liquid crystal display device according to the present invention, and FIG. 2 is a timing chart for explaining the operation of the sample and hold system of the liquid crystal display device of FIG. Hereinafter, the sample and hold system of the liquid crystal display device according to the embodiment will be described with reference to these drawings, and at the same time, one embodiment of the sample and hold method of the liquid crystal display device according to the present invention will be described. 1 and 2, the same components and signals as those in FIGS. 6 and 7 are denoted by the same reference numerals.

This sample and hold system 2 is for a liquid crystal display device 12 (in the case of n = 3 in FIG. 3) configured to supply video signals to three pixel elements 16 at the same time. Sample hold circuits 42, 44, 4
6 and 3 second sample and hold circuits 48, 50, 5
2 is constituted. Then, the RG shown in FIG.
The video signal DATA from the B driver 38 is commonly input to the three first sample-hold circuits 42, 44, 46, and the output signals of the first sample-hold circuits 42, 44, 46 are three second sample-hold circuits 42, 44, 46, respectively. Hold circuit 4
8, 50, and 52 are input.

In the sample and hold system 2, the clocks SH1, SH2 and SH3 shown in FIG. 2 are input to the first sample and hold circuits 42, 44 and 46 as sample and hold clocks, respectively. And
The clock SH3 is input to both the second sample and hold circuits 48 and 50, while the clock SH1 is input to the second sample and hold circuit 52 as a sample and hold clock. The video signal DATA input to the sample-and-hold system 2 is composed of signals a, b, c,... (Time width T) corresponding to pixels arranged continuously in the horizontal direction in the order of elapse of time. It has an arrayed form.

The clocks SH1, SH2, SH3 are shown in FIG.
As shown in the figure, the level sequentially becomes high in this order, and the period is time T. In addition, the repetition period of the high level is 3T corresponding to three consecutive pixels. The H clock HCK is a clock that switches between a high level and a low level every 3T, and this clock is supplied to the H shift register 18 shown in FIG.

Next, the operation of the sample and hold system 2 will be described. First, the first sample and hold circuit 42
Starts sampling the signal a of the video signal DATA at the rising edge of the clock SH1, and holds the signal a at the falling edge. Similarly, the first sample and hold circuit 4
4 starts sampling the signal b of the video signal DATA at the rising edge of the clock SH2, and starts sampling the signal b at the falling edge.
Hold. Also, the first sample and hold circuit 4
6 starts sampling the signal c of the video signal DATA at the rising edge of the clock SH3, and at the falling edge of the signal c
Hold.

The first sample and hold circuits 42, 44,
46 operates as described above based on the clocks SH1, SH2, and SH3, so that the first sample and hold circuit 42 outputs the signals a, d, g,.
Are sequentially output at the timings shown in FIG. 5, and the first sample-and-hold circuit 44 outputs the signals b, e, h,.
Output the signals c, f, i,... Sequentially as the video signal C1 at the timing shown in FIG.

Thereafter, the second sample and hold circuit 4
8, 50 are first sample and hold circuits 42, respectively.
The sampling of the video signals A1 and B1 from 44 starts at the rising edge of the clock SH3, and each signal is held at the falling edge. As a result, the second sample-and-hold circuit 48 and the second sample-and-hold circuit 48
50, the signals a, d,
g,... and signals b, e, h,. On the other hand, the second sample and hold circuit 5
2 is the video signal C from the first sample and hold circuit 46
1 starts sampling at the rising edge of the clock SH1, and holds at the falling edge. As a result, after a short time has elapsed after the clock SH1 has risen, during the period until the next rise, the second sample and hold circuit 52 outputs the signals c, f, i,
.. Are output as shown in FIG.

Therefore, in the period Tc shown in FIG. 2, signals a, b, c,..., Signals d, e, f,. ,
are the second sample and hold circuits 48, 5
0 and 52 are output simultaneously. Therefore, if the H switch element 22 shown in FIG. 3 is turned on in synchronization with this period Tc, the above three signals can be supplied to each pixel element 16 at the same time.

In this embodiment, as described above, the first
Clock SH3 for the sample and hold circuit 46 of FIG.
Is supplied as a sample and hold clock, and the first
The video signal is also sampled and held by the sample and hold circuit 46. Therefore, any video signal supplied to each pixel element 16 at the same time is sampled and held at least twice, and the error component included in each video signal accompanying the sample and hold is the same for any video signal. Become. Therefore, when the video signal generated according to the present embodiment is used, a streak of every plural pixels does not appear in a display image as in the related art, and good image quality can be realized.

In this embodiment, the clock SH3 is input to the second sample and hold circuit 50.
As is clear from the timing chart of FIG.
It is also possible to input H2 as a sample and hold clock. Although the case where the video signal is supplied to the three pixel elements 16 at the same time has been described here, the present invention is of course effective even when the number of the pixel elements 16 that supply the video signal at the same time is large. That is, in the case of the sample and hold system 54 as shown in FIG. 8, first, the clock SHn which becomes the last high level is input to the n-th first sample and hold circuit 56 as the sample and hold clock. Then, the clock SHn is input as a sample / hold clock from the second sample / hold circuit 48 to the (n−1) -th second sample / hold circuit 53, and the n-th second sample / hold circuit 5 is input.
5, the clock SH1 is input as a sample and hold clock.

[0032]

As described above, according to the present invention, a plurality of video signals simultaneously supplied to the liquid crystal display device are always sampled and held twice before being supplied to the liquid crystal display device. The error component included in each video signal due to the hold is the same for all video signals. Therefore, when the video signal generated according to the present invention is used, a streak of a plurality of pixels does not appear in a display image as in the related art, and good image quality can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a sample and hold system of a liquid crystal display device according to the present invention.

FIG. 2 is a flowchart illustrating the operation of the sample and hold system of the liquid crystal display device of FIG. 1;

FIG. 3 is a circuit diagram showing an example of a conventional liquid crystal display device of a multiple dot simultaneous sampling system.

FIG. 4 is a block diagram illustrating a pre-processing unit for a video signal.

FIG. 5 is a waveform diagram showing an input signal and an output signal of a preprocessing unit.

FIG. 6 is a block diagram showing the sample and hold system 40 in detail.

FIG. 7 is a timing chart showing the operation of the sample hold system 40.

FIG. 8 is a block diagram showing a sample and hold system 54 for simultaneously supplying a video signal to n pixel elements 16;

FIG. 9 is a timing chart showing the operation of the sample hold system 54.

[Explanation of symbols]

2 ... Sample hold system, 12 ... Liquid crystal display device, 14 ... Substrate, 16 ... Pixel element, 18 ... H shift register, 20 ... V shift register, 22 ... H switch element, 24 ... V Switch element, 26, capacitor, 28, common electrode, 30, V start pulse, 32
... V input terminal, 34 ... H start pulse, 36 ... H input terminal, 38 ... RGB driver, 40 ... sample hold system, 42 ... first sample hold circuit, 44 ... first sample Hold circuit, 46 first sample hold circuit, 48 second sample hold circuit, 50 second sample hold circuit, 5
2. Second sample-hold circuit, 53 Second sample-hold circuit, 54 Sample-hold system, 55 Second sample-hold circuit, 56 First sample-hold circuit.

Claims (6)

[Claims] 1. A video signal is sampled sequentially at different timings corresponding to each of the plurality of pixels by a same number of first sample-and-hold means as the plurality of pixels for each cycle corresponding to a plurality of continuous pixels. Holding the output signals of the first sample-and-hold means by the same number of second sample-and-hold means as the plurality of pixels, respectively, in the cycle, and supplying the output signals to the liquid crystal display device; When the sample and hold is performed by the hold unit, the output signal of the first sample and hold unit that samples and holds the video signal first in the cycle is the first signal that samples and holds the video signal last in the cycle. Sample and hold at the same timing as the sample and hold means, and The output signal of the first sample-and-hold unit that samples and holds the video signal is sampled and held at the same timing as the first sample-and-hold unit that samples and holds the video signal first within the period. Display device sample and hold method. 2. The liquid crystal display device according to claim 1, wherein the plurality of pixels are arranged in a horizontal direction on a screen of a liquid crystal display device.
A sample and hold method for a liquid crystal display device as described in the above. 3. The first sample and hold means for sampling and holding the video signal second in the cycle when sampling and holding by the second sample and hold means, wherein the number of the plurality of pixels is three. 2. The sample of the liquid crystal display device according to claim 1, wherein the output signal is sampled and held at the same timing as the first sample and hold means for sampling and holding the video signal last or second in the cycle. Hold method. 4. The same number of first sample-holds as the plurality of pixels, wherein the video signals are sampled and held sequentially at different timings corresponding to each of the plurality of pixels for each cycle corresponding to the plurality of continuous pixels. Means for sampling and holding each output signal of the first sample and hold means in the cycle and supplying the output signals to a liquid crystal display device, the same number of second sample and hold means as the plurality of pixels; 2 sample and hold means, wherein the output signal of the first sample and hold means which samples and holds the video signal first in the cycle is the first sample which samples and holds the video signal last in the cycle. Sampling and holding at the same timing as the holding means, and sampling and holding the video signal last in the cycle The output signal of the first sample and hold means samples and holds the video signal at the same timing as the first sample and hold means which samples and holds the video signal first in the period. Hold system. 5. The liquid crystal display device according to claim 4, wherein the plurality of pixels are arranged in a horizontal direction on a screen of a liquid crystal display device.
A sample and hold system for a liquid crystal display device as described in the above. 6. The number of the plurality of pixels is three, and the second sample-and-hold unit samples and holds the video signal second in the period. The output signal of the first sample-and-hold unit is 5. A sample and hold system for a liquid crystal display device according to claim 4, wherein said sample and hold is performed at the same timing as said first sample and hold means for sampling and holding said video signal last or second in said cycle.