JPH10150472A - Data transmission equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data transmission equipment capable of simply and easily removing indefiniteness of frequency divider phase due to serial-parallel transformation when plural encoders and error correction decoders are installed in parallel. SOLUTION: A data transformation means 12 at a transmitting side converts output of an encoding means 11a into (X, Y), the output of encoding means 11b to 11n into (Y<-> , X) and outputs the converted outputs by parallel-serial conversion in parallel serial converting means 13a, 13b and orthogonal modulation by an orthogonal modulating means 14. The outputs are orthogonally demodulated by an orthogonal demodulating means 15 at a receiving side and the output of a serial-parallel converting means 16a, 16b are decoded by decoding means 17a to 17n. Each decoding means removes the indefiniteness of quadraple phase due to orthogonal modulation and demodulation so as to be synchronized. A removed pattern signal is monitored by a frequency divider phase judging means 18, an order of columns of parallel data corresponding to the transmission side is judged and the order of the data columns of output of each decoding means in a switching means 19 is replaced so that the indefiniteness of the frequency divider phase due to the serial-parallel converter is removed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission apparatus, and more particularly to a data transmission apparatus that uses an orthogonal modulation system as a modulation system and performs error correction using a convolutional encoder and an error correction decoder.

[0002]

2. Description of the Related Art As a prior art of this type of data transmission apparatus, for example, Japanese Patent Application Laid-Open No.
(2) The description in JP-A-60-38957 is referred to.

The size of a Viterbi decoder used for error correction decoding of a convolutional code that has received a transmission error increases with the size of the constraint length K. For example, the current maximum speed at which a Viterbi decoder with a constraint length K = 7 and a coding rate R = 1/2 can decode is about 30 Mbps, and the information transmission speed is limited by the maximum speed.

In order to overcome this problem, there is a demand for a data transmission apparatus in which a plurality of convolutional encoders and a plurality of Viterbi decoders are installed, and an information bit sequence to be transmitted is processed in parallel.

FIG. 6 is a diagram for explaining a configuration of a conventional data transmission apparatus. FIG. 6J (a) is a block diagram showing a configuration of a modulation unit, and FIG. 6 (b) is a configuration of a demodulation unit. It is a block diagram.

The data transmission device includes encoders 61a to 61
d, a modulator configured by parallel / serial converters (P / S) 63a, 63b and a quadrature modulator 64;
5, a demodulation unit including serial / parallel converters (S / P) 66a and 66b, Viterbi decoders 67a to 67d, a sync word detector 68, and a switch 69. Less than,
Each component will be described in detail.

[0007] The encoder 61a receives an information bit sequence T01 to be transmitted as an input, performs convolutional coding on the information bit sequence at a coding rate of 1/2, and outputs a coded bit sequence consisting of two columns, a bit sequence T11 and a bit sequence T12.

Similarly, the encoder 61b receives the bit sequence T02, outputs a coded bit sequence consisting of two columns, a bit sequence T13 and a bit sequence T14, and outputs the coded bit sequence.
Receives a bit sequence T03, outputs a coded bit sequence composed of two columns of a bit sequence T15 and a bit sequence T16, and an encoder 61d receives a bit sequence T04 as an input, and outputs a coded bit sequence composed of two columns of a bit sequence T17 and a bit sequence T13 Is output.

The parallel / serial converter 63a includes an encoder 61
a to 61d output bit strings T11 and T11, respectively.
13, T15 and T17 are input, and these are converted into parallel / serial to output a bit string T21.

Similarly, the parallel / serial converter 63b outputs the bit string T output from each of the encoders 61a to 61d.
12, T14, T16, and T18 are input, and these are converted into parallel / serial to output a bit string T22.

The quadrature modulator 64 includes a parallel / serial converter 63
a and 63b output bit strings T21 and T
22 is input, these are subjected to 4-phase phase modulation corresponding to each of the orthogonal axes, and a modulation signal T31 is transmitted to the transmission path.

The quadrature demodulator 65 receives the received signal R01 transmitted via the transmission path as input, performs four-phase demodulation, and outputs bit strings R11 and R12.

The serial / parallel converter 66a includes a quadrature demodulator 6
5 is input, and this is converted to serial / parallel to perform bit string R21, R23, R25, R
27 is output. Similarly, the serial / parallel converter 66b
The bit string R12 output from the quadrature demodulator 65 is used as an input, and this is serially / parallel converted to perform bit strings R22 and R2.
4, R26 and R28 are output.

The Viterbi decoder 67a outputs the bit strings R21 and R22 output from the serial / parallel converters 66a and 66b.
Are input, and these are subjected to error correction decoding and bit sequence R31
Is output.

Similarly, the Viterbi decoder 67b outputs the bit string R2 output from the serial / parallel converters 66a and 66b.
3, R24 are input, error-corrected and decoded to output a bit string R32. The Viterbi decoder 67c outputs the bit string R2 output from the serial / parallel converters 66a and 66b.
5, R26 are input, error-corrected and decoded, and a bit string R33 is output. The Viterbi decoder 67d outputs the bit string R2 output from the serial / parallel converters 66a and 66b.
7, R28 are input, and these are subjected to error correction decoding to output a bit string R34.

The synchronization word detector 68 includes a Viterbi decoder 6
The bit strings R31 to R34 output from 7a to 67d are input and, for example, by detecting the frame synchronization word inserted on the transmission side, the serial / parallel converters 66a and 66
The order of the bit string exchanged due to the division phase uncertainty of 6b is determined, and a division phase determination signal C11 is output.

The switch 69 includes Viterbi decoders 67a-67.
The bit strings R31 to R34 output from d.
According to the frequency-divided phase determination signal C11 output from the synchronous word detector 68, the arrangement of the bit strings is changed by the encoders 61a to 61-6.
Switching is performed so as to correspond to the information bits T01 to T04 of the 1d input, and bit strings R41 to R44 are output.

Next, the operation of the conventional data transmission apparatus will be described.

First, the operation of the modulation section will be described with reference to FIG. Four information bit strings T01 to T to be transmitted
If T04 is T01: D11, D12, D13, ... T02: D21, D22, D23, ... T03: D31, D32, D33, ... T04: D41, D42, D43, ... The obtained information bit strings T01 to T04 are convolutionally coded, and coded bit strings T11 to T18 are output.

T11: X11, X12, X13, ... T12: Y11, Y12, Y13, ... T13: X21, X22, X23, ... T14: Y21, Y22, Y23, ... T15: X31, X32 , X33, ... T16: Y31, Y32, Y33, ... T17: X41, X42, X43, ... T18: Y41, Y42, Y43, ...

The encoded bit strings T11 to T18 output from the encoders 61a to 61d are converted into parallel / serial converters 63.
a and 63b.

The parallel / serial converters 63a and 63b perform parallel / serial conversion on the input coded bit strings T11 to T18, and output the following bit strings T21 and T22.

T21: X11, X21, X31, X41,... T22: Y11, Y21, Y31, Y41,.

The bit strings T21 and T22 output from the parallel / serial converters 63a and 63b are modulated by the quadrature modulator 64, and a modulated signal T31 is sent to the transmission line.

Next, the operation of the demodulation unit will be described with reference to FIG.

The modulated signal T31 transmitted from the modulation section to the transmission line as described above receives the received signal R0 via the transmission line.
1 is input to the quadrature demodulator 65.

In the quadrature demodulator 65, the input received signal R01 is four-phase-demodulated, and the demodulated bits R11 and R12 are demodulated.
Is output.

The demodulated bits R11 and R12 output from the quadrature demodulator 65 are converted into serial / parallel converters 6 respectively.
6a and 66b, are converted into parallel / serial, and output as bit strings R21 to R28.

The bit strings R21 to R28 output from the serial / parallel converters 66a and 66b are input to Viterbi decoders 67a to 67d, respectively.

In each of the Viterbi decoders 67a to 67d, error correction decoding is performed on the bit strings R21 to R28, respectively, and the above-described four information bit strings T01 to T to be transmitted are transmitted.
The bit strings R31 to R34 corresponding to the data 04 are output.

The four-phase demodulation method performed in the quadrature demodulator 65 shown in FIG. 6B is a kind of quadrature modulation method.
Since the demodulation in the quadrature modulation method has four-phase uncertainty, the bit strings R11, R11 output from the quadrature demodulator 65 are output.
Numeral 12 does not always match the bit strings T21 and T22 input to the quadrature modulator 64 even if the transmission error is ignored.

For example, the bits of the bit strings R11 and R12 with respect to the bits X11 and Y11 of the bit strings T21 and T22 are (X11, Y11), ignoring the transmission error.
(Y11￣, X11), (X11￣, Y11￣), (Y
11, X11￣). Here, the symbol ￣ indicates a complementary (inverted) signal.

Various methods have been proposed as a method for removing the four-phase uncertainty. For example, as applied to the TDMA system, Japanese Patent Application Laid-Open No. 61-137449 discloses a calculation of a transition path length in a Viterbi decoder,
A polyphase PSK in which the unique word detection in the unique word detection circuit is executed in parallel in time, thereby reducing the overall processing time and omitting the shift register of the phase uncertainty removal circuit A signal decoding device has been proposed. In the decoding device disclosed in the publication, phase information in a preamble portion of a burst signal is used.

Japanese Patent Application Laid-Open No. 60-38957 discloses that
The phase uncertainty elimination circuit is configured so as to minimize the combination of control signals for elimination of phase uncertainty, thereby shortening the time until the elimination of uncertainty. A PSK wave phase uncertainty removing circuit has been proposed.

[0035]

In the conventional data transmission apparatus described above, the output bit strings R21, R23, R25, and R27 of the serial / parallel converter (S / P) 66a are arranged as follows.
Due to the division phase uncertainty in the serial / parallel conversion, the bit strings T11, T13, T15, T17 on the transmitting side are not necessarily required.
Does not match, and there are four patterns in all. This means
The same applies to the serial / parallel converter (S / P) 66b.

FIG. 8 shows that the phase of the reference carrier of the quadrature demodulator 65 and the phase of the carrier of the quadrature modulator 64 match, and the frequency-divided phases of the serial / parallel converters 66a and 66b correspond to the transmitting side and the receiving side. An example of each output when there is a shift of one bit from the side is shown. However, in consideration of a transmission error, a bit “R” is added to the bit on the receiving side.

As shown in FIG. 8, the serial / parallel converter 66
If the dividing phases of a and 66b are shifted between the transmitting side and the receiving side, the arrangement of the bit strings R21 to R28 is different from the arrangement of the bit strings T11 to T18 on the transmitting side shown in FIG. Become.

Also in this case, each of the Viterbi decoders 67a to 67a-6
In 7d, error correction is normally performed.

Therefore, the serial / parallel converters 66a, 66b
The bit strings R21 to R28 output from the decoders are error-correction decoded by the respective Viterbi decoders 67a to 67d as they are, and as a result, the bit strings T01 to T01 on the transmission side shown in FIG.
Bit strings R31 to T34 different from the arrangement of T04 are output.

In order to detect the arrangement of columns on the receiving side, there is a method using a frame synchronization word inserted on the transmitting side, for example. This focuses on the sequence of synchronization words,
If they are arranged from the decoded bit string R31, the arrangement on the transmitting side and the receiving side match.

If the decoding bit string R32 starts and continues to the decoding bit string R34 and then continues one or two bits apart to the decoding bit R31, the first bit on the transmitting side
It can be seen that the information bits in the column correspond to the second column on the receiving side.

Here, the one or two-bit separation is determined by the coding rate of the Viterbi decoders 67a to 67d and the hardware configuration. When the coding rate is R = 1/2, the bit separation is one bit. When the conversion ratio R approaches 1, there may be a case where two bits are separated.

As described above, the pattern of the synchronization word on the receiving side increases as the parallel number increases.

As described above, when a plurality of encoders and error correction decoders are respectively installed in parallel, due to the uncertainty of the frequency division phase in the serial / parallel converter, the output of the error correction decoder is The order of data may be different from that of the sender.

If the frame synchronization word is used to detect this order, a plurality of synchronization word patterns appear on the receiving side depending on the number of parallel circuits and the coding rate of the convolutional encoder. The size of the detection circuit increases,
In addition, there is a problem that it takes time to match a plurality of patterns with the synchronization word, and the detection processing time becomes long.

Accordingly, the present invention has been made in view of the above problems, and has as its object to provide a simple configuration and a short structure when a plurality of encoders and error correction decoders are respectively installed in parallel. In processing time, the serial / parallel converter (S
/ P) to provide a data transmission apparatus for removing the frequency division phase uncertainty.

[0047]

In order to achieve the above object, the present invention provides an encoding means for convolutionally encoding a plurality of information bit strings to be transmitted for each column and outputting an encoded bit string; Parallel / serial conversion means for parallel / serial conversion of each coded bit string from the coding means, orthogonal modulation means for orthogonally modulating the output of the parallel / serial conversion means and transmitting a modulated signal to a transmission path; Orthogonal demodulation means for orthogonally demodulating each of the modulated signals and outputting a demodulated signal, serial / parallel conversion means for serial / parallel conversion of the outputs of the orthogonal demodulation means, and conversion by the serial / parallel conversion means. Decoding means for performing error correction decoding of each demodulated bit string and outputting a decoded bit string corresponding to the plurality of information bit strings, wherein each encoding bit inputted to the parallel / serial conversion means is provided. A data conversion means for converting the data of the data train, and a frequency division phase in the serial / parallel conversion means which is determined based on a four-phase uncertainty removal pattern signal output from the decoding means, and a determination signal is output. It is characterized by having a peripheral phase determining means and a switching means for switching the arrangement of decoded bit strings based on a determination signal output from the frequency dividing phase determining means.

Further, in the present invention, the encoding means convolutionally encodes n (n ≧ 3) columns of information bit strings to be transmitted for each column, and generates a code comprising first and second bit strings. The data conversion means determines the sign of a first bit string of a first column and a second bit string of a bit string other than the first column out of the n columns. And outputting a first bit string group consisting of the bit strings obtained by the first and second bit strings of the first column in the n columns.
A data converter that outputs a second bit string group including a first bit string of a bit string other than a column, and wherein the parallel / serial conversion means converts the first bit string group into a parallel / serial data. A parallel / serial converter and a second parallel / serial converter for parallel / serial conversion of the second bit string group, wherein the serial / parallel conversion means outputs the output of the quadrature demodulation means to each of n columns And a second serial / parallel converter for serial / parallel conversion into two bit strings output from the first and second serial / parallel converters. , And Viterbi decoding is performed for each pair of columns corresponding to each other, and n Viterbi decoders that output a decoded bit sequence and a four-phase uncertainty removal pattern signal are provided. Output from Viterbi decoder A frequency-divided phase determiner configured to detect a decoded bit sequence of a first column based on the four-phase uncertainty removal pattern signal and to output a frequency-divided phase determination signal to the switching means; May be configured by a switch that switches the arrangement of each decoded bit string in accordance with the information bit string according to the divided phase judgment signal output from the divided phase discriminator.

According to the present invention configured as described above,
As a detection means when an erroneous bit string is output due to frequency division phase uncertainty by the serial / parallel conversion means, a four-phase phase uncertainty removal pattern signal output by a quadrature modulation / demodulation means output from a Viterbi decoder is used. By using this, detection can be easily performed with a simple configuration.

[0050]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.
FIG. 1A is a block diagram illustrating a configuration of a modulation unit, and FIG.
(B) is a block diagram showing a configuration of a demodulation unit.

Referring to FIG. 1, in the data transmission apparatus according to the embodiment of the present invention, the modulation section performs convolutional encoding of a plurality of information bit strings to be transmitted for each column and outputs an encoded bit string. Encoding means 11a to 11d, and parallel / serial conversion means 13a and 13b for performing parallel / serial conversion of each encoded bit string from the encoding means 11a to 11d.
A data conversion unit 12 for converting data of each encoded bit string input to the parallel / serial conversion units 13a and 13b;
And a quadrature modulator 14 for orthogonally modulating the outputs of the parallel / serial converters 13a and 13b and sending out a modulated signal to a transmission path. Quadrature demodulation means 1 for demodulating and outputting a demodulated signal
5, serial / parallel conversion means 16a and 16b for serial / parallel conversion of the output of the quadrature demodulation means 15, and error-decoding of each demodulated bit string converted by the serial / parallel conversion means 16a and 16b. Decoding means 17a to 17d for outputting a decoded bit string corresponding to the bit string, and serial / parallel conversion means 16a, 16 using the four-phase uncertainty removal pattern signal output from the decoding means 17a to 17d.
(b) frequency dividing phase determining means for determining a frequency dividing phase and outputting a determination signal; and switching means 19 for switching the arrangement of decoded bit strings based on the determination signal output from the frequency dividing phase determining means 18. Have been.

On the transmitting side (modulator side), encoding means 11
Assuming that each output of a to 11n is (X, Y), the data conversion unit 12 replaces the output of the other encoding units 11b to 11n with the output of the encoding unit 11a as it is (X, Y). (Y￣, X), and converted into parallel / serial conversion means 13 respectively.
The parallel-to-serial conversion is performed at a and 13b, and the signal is orthogonally modulated by the orthogonal modulation means 14 and output.

On the receiving side, orthogonal demodulation is performed by orthogonal demodulation means 15, and the outputs of serial / parallel conversion means 16a and 16b are decoded by decoding means 17a to 17n, respectively. At this time, each decoding means removes the four-phase uncertainty by quadrature modulation and demodulation so that synchronization can be achieved. This removal pattern signal is monitored by the divided phase determination means 28, and the parallel data sequence corresponding to the transmitting side is removed. The order is determined, and the data sequence of the output of each decoding means is exchanged by the switching means 19 so as to remove the uncertainty of the frequency division phase by the serial / parallel conversion means and output. In the embodiment of the present invention, the frequency-divided phase uncertainty by the serial / parallel conversion means can be removed using the 4-phase phase uncertainty removal pattern information of the decoder. The dividing phase can be determined, and a complicated frame synchronization circuit is not required.

[0054]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 2 is a diagram for explaining a circuit configuration of an embodiment of the present invention. FIG. 2A is a diagram showing a circuit configuration of a modulation unit, and FIG. 2B is a circuit of a demodulation unit. FIG. 3 is a diagram illustrating a configuration.

Referring to FIG. 2, the data transmission apparatus of the present embodiment comprises convolutional encoders 21a to 21d, data inverters 22b to 22d, parallel / serial converters 23a and 23b, and quadrature modulator 24. Modulator and quadrature demodulator 2
5, serial / parallel converters 26a and 26b, Viterbi decoder 2
7a to 27d, a frequency-divided phase determiner 28, and a demodulator including a switch 29. Each component will be described in detail below.

The convolutional coder 21a receives an information bit sequence T01 to be transmitted as an input, performs convolutional coding on the information bit sequence at a coding rate of 1/2, and outputs a coded bit sequence consisting of two sequences of a bit sequence T11 and a bit sequence T12. I do.

Similarly, the encoder 21b outputs the bit string T
02 as an input, 2 of bit strings T13 and T14
A coded bit sequence composed of a sequence is output, an encoder 21c receives a bit sequence T03 as an input, outputs a coded bit sequence composed of two columns of a bit sequence T15 and a bit sequence T16, and an encoder 21d receives a bit sequence T04 as an input, T17
And a coded bit string consisting of two strings of a bit string T18.

The data inverter 22b is a convolutional encoder 2
2b, and outputs a bit sequence T14 # with the sign of the input bit sequence inverted.

Similarly, the data inverter 22c receives the bit string T16 output from the convolutional encoder 22c as an input, and converts the bit string T16 # obtained by inverting the sign of the input bit string.
And the data inverter 22d outputs the convolutional coder 22d.
The bit sequence T18 output from d is input and a bit sequence T18 # in which the sign of the input bit sequence is inverted is output.

The parallel / serial converter (P / S) 23a outputs bit strings T11, T14 #, T1 output from the convolutional encoder 21a and the data inverters 22b to 22d, respectively.
6} and T18}, and converts these into parallel / serial to output a bit string T21.

Similarly, a parallel / serial converter (P / S) 23
b receives as input the bit strings T12, T13, T15, and T17 output from the convolutional encoders 21a to 21d, converts these into parallel / serial, and outputs a bit string T22.

The quadrature modulator 24 includes a parallel / serial converter 23
a and 23b output bit strings T21 and T21, respectively.
22 is input, these are subjected to 4-phase phase modulation corresponding to each of the orthogonal axes, and a modulation signal T31 is transmitted to the transmission path.

The quadrature demodulator 25 receives the received signal R01 transmitted via the transmission path, performs four-phase demodulation, and outputs bit strings R11 and R12.

The serial / parallel converter (S / P) 26a receives the bit string R11 output from the quadrature demodulator 25 as an input, performs serial / parallel conversion of the bit string R11, and converts the bit strings R21, R2.
3, R25 and R27 are output.

Similarly, a serial / parallel converter (S / P) 26
b receives the bit string R12 output from the quadrature demodulator 25, converts the bit string into a bit string R22,
R24, R26 and R28 are output.

The Viterbi decoder 27a outputs the bit strings R21, R22 output from the serial / parallel converters 26a, 26b.
Are input, and these are subjected to error correction decoding and bit sequence R31
Is output. In order to achieve Viterbi synchronization, at least 90% of the four-phase uncertainties caused by quadrature modulation / demodulation are used.
Although it is necessary to remove the degree of uncertainty, the removal pattern is output as a divided phase uncertainty removal signal C01.

Similarly, the Viterbi decoder 27b outputs the bit string R2 output from the serial / parallel converters 26a and 26b.
3 and R24, and outputs a bit string R32 and a frequency-divided phase uncertainty elimination signal C02 obtained by error-correcting and decoding these. Also, the Viterbi decoder 27c has a serial / parallel converter 2
The bit strings R25 and R26 output from 6a and 26b are input, and a bit string R33 obtained by error-correcting and decoding these and a frequency-divided phase uncertainty elimination signal C03 are output. Further, the Viterbi decoder 27d includes a serial / parallel converter 26a,
The bit strings R27 and R28 output from 26b are input, and the bit strings R34 and the frequency-divided phase uncertainty elimination signal C04 obtained by error-correcting and decoding these are output.

The frequency dividing phase determiner 28 includes a Viterbi decoder 27
divided phase uncertainty elimination signal C output from a to 27d
When 01 to C04 are input and only one of the input signals C01 to C04 has a pattern different from the others,
This is detected, and a frequency-divided phase determination signal C11 that controls to rearrange the column that has transmitted the signal to the first column on the receiving side,
Output to the switch 29.

The switching unit 29 includes Viterbi decoders 27a to 27
The bit strings R31 to R34 output from d.
Divided phase determination signal C output from divided phase determiner 28
11, the arrangement of the bit strings is determined by the encoders 21a to 21a.
The bit strings are switched so as to correspond to the d input information bits T01 to T04, and bit strings R41 to R44 are output.

Next, the operation of the data transmission apparatus of this embodiment will be described in detail. FIG. 3 is a time chart for explaining the operation of the modulation unit in one embodiment of the present invention.

First, the operation of the modulation section will be described with reference to FIG. Four information bit strings T01 to T to be transmitted
If T04 is T01: D11, D12, D13,... T02: D21, D22, D23,... T03: D31, D32, D33,. The bit string T01 is convolutionally coded at a coding rate of 、, and the bit strings T11, T11
A coded bit sequence consisting of 12 columns is output. Note that D
Reference numeral 12 denotes the second bit data in the first column of the bit string.

Similarly, the encoder 1b outputs T13, T14
, The encoder 1c outputs T15 and T16, and the encoder 1d outputs T17 and T18.

At this time, the bit strings are represented by T11: X11, X12, X13,... T12: Y11, Y12, Y13,... T13: X21, X22, X23, ... T14: Y21, Y22, Y23,. X32, X33, ... T16: Y31, Y32, Y33, ... T17: X41, X42, X43, ... T18: Y41, Y42, Y43, ...

The data inverters 22b to 22d convert the encoded bit strings T14, T16, T18 into T14￣,
It is converted to T16 # and T18 # and output. However, the symbol ￣ indicates the complement (inversion).

The parallel / serial converter 2a outputs the bit string T1
1, T14}, T16}, and T18} into a bit string T21, and the parallel / serial converter 2b converts the bit strings T12, T
13, T15 and T17 are converted into a bit string T22.

At this time, each bit string T21, T22 is represented by T21: X11, Y21￣, Y31￣, Y41￣, X1
2, ... T22: Y11, X21, X31, X41, Y12, ...
Becomes

The quadrature modulator 24 converts the bit strings T21, T2
2 corresponding to each of the orthogonal axes.
31 to the transmission path.

Next, the four-phase phase modulation signal T3 from the modulation section
The operation of the demodulation unit for demodulating 1 will be described with reference to FIG. FIG. 4 is a time chart for explaining the operation of the demodulation unit in one embodiment of the present invention.

The quadrature demodulator 25 performs four-phase demodulation on the received signal R01 transmitted on the transmission line, and performs demodulation bit strings R11 and R11.
12 is output.

Although this output has a four-phase uncertainty,
When the phase of the reference carrier matches the phase of the carrier of the quadrature modulator 24, as shown in FIG. 4, R11: RX11, RY21Ｙ, RY31￣, RY41
Ｒ,... R12: RY11, RX21, RX31, RX41,. However, "R" is added to the bit on the receiving side in consideration of the transmission error.

When R11 and R12 are output from the quadrature demodulator 25, the serial / parallel converter 26a outputs the bit string R11
Is converted to R21, R23, R25, and R27. Similarly, the serial / parallel converter 26b converts the bit string R12 into R22, R
24, R26 and R28. In this conversion, R2
In the present embodiment, the following operations are performed since 1 to R28 have a frequency division uncertainty in the serial / parallel conversion.

(1) The case where the divided phases of the parallel / serial converters 23a and 23b and the serial / parallel converters 26a and 26b match will be described below.

The parallel / serial converters 23a and 23b
When the divided phases of the parallel converters 26a and 26b match, as shown in FIG. 4, R21: RX11, RX12, RX31,... R22: RY11, RY12, RY31,. ￣, ... R24: RX21, RX22, RX23, ... R25: RY31￣, RY32￣, RY33￣, ... R26: RX31, RX32, RX33, ... R27: RY41￣, RY42￣, RY43…, ... R28: RX41, RX42 , RX43,...

Of the above-mentioned pair of demodulated bit strings, R21, R
With respect to 22, the Viterbi decoder 27a can directly perform Viterbi decoding, and a decoded bit string R31 is obtained. The other bit string pairs correspond to the case where the phase of the reference carrier of the quadrature demodulator 25 is shifted by 90 degrees with respect to the carrier of the quadrature modulator 24.

In general, a Viterbi decoder has a configuration in which the phase uncertainty is removed and Viterbi synchronization is achieved. For each column pair, the set of (RY￣, RX) is changed to (RX, RY). After that, the bit strings R32 to R34 are output.

The presence / absence of the bit string exchange operation is output as frequency-divided phase uncertainty removal signals C01 to C04.

In this embodiment, the divided phase uncertainty removal signals C01 to C04 are (0 degree, 90 degree, 90 degree, 90 degree
Degree).

These are monitored by the frequency dividing phase determiner 28,
It can be seen that the bit string pair R21, R22 in the first column, in which only one Viterbi decoder performs processing different from the others, corresponds to the convolutional encoder 21a in the first column of the modulation unit.

Accordingly, in this case, the order of the bit strings of the modulating unit and the demodulating unit is the same, so that the frequency dividing phase decision unit 28
, The input bit strings R31 to R34 are switched by the switch 29 in the same order as R41.
Are output as .about.R44.

(2) Next, the parallel / serial converters 23a and 23
A case will be described in which the frequency-divided phases of b and the serial / parallel converters 26a and 26b are shifted by one bit.

The parallel / serial converters 23a and 23b
When the frequency division phases of the parallel converters 26a and 26b are shifted by one bit, as shown in FIG. 5, R21: RY21￣, RY22￣, RY23￣, ... R22: RX21, RX22, RX23, ..., R23: RY31 ２４, RY32￣, RY33￣, ... R24: RX31, RX32, RX33, ... R25: RY41￣, RY42￣, RY43￣, ... R26: RX41, RX42, RX43, ... R27: RX12, RX13, RX14, ... R28: RY12, RY13, RY14,...

Of the pair of the demodulated bit strings, R27, R
With respect to 28, Viterbi decoding can be performed by the Viterbi decoder 27d as it is, and a decoded bit string R34 is obtained.

For the other bit string pairs, each of the Viterbi decoders 27a to 27c outputs (RY￣,
The set (RX) is replaced with (RX, RY), and decoded bit strings R31 to R33 are output. At this time, the divided phase uncertainty removal signals C01 to C04 are (90 degrees, 90 degrees, respectively).
Degrees, 90 degrees, 0 degrees).

These are monitored by the frequency dividing phase determiner 28,
It can be seen that the bit string pair R27, R28 in the fourth column, in which only one Viterbi decoder performs processing different from the others, corresponds to the convolutional encoder 21a in the first column of the modulation unit.

Therefore, in this case, it is determined that the order of the bit strings of the modulation unit and the demodulation unit is out of order,
8, the input bit strings R31 to R34 are changed to R42, R43, R
44 and R41.

At the same time, since only R41 is ahead of the others by one bit, it is output after being delayed by one bit.

The case where the phase of the reference carrier of the quadrature demodulator 25 coincides with the carrier of the quadrature modulator 24 has been described above. However, the same operation is performed even when the phase is shifted due to four-phase uncertainty. .

For example, when the phases are shifted by 90 degrees, assuming that the output of the convolutional encoder 21a is (RX, RY) and the outputs of the convolutional encoders 21b to 21d are (RYＲ, RX),
As for the inputs of the Viterbi decoders 27a to 27d, if the divided phases of the serial / parallel converters 26a and 26b coincide with the modulation unit, only the first column (RY￣, RX) and the other three columns (RX
{, RY}). At this time, the divided phase uncertainty removal signals C01 to C04 are (90 degrees, 180 degrees, 180 degrees, respectively).
Degrees, 180 degrees), which indicates that the first column corresponds to the first column of the modulation section.

In the embodiment described above, the Viterbi decoder 27
Since a to 27d are operated in parallel, data can be transmitted at a transmission speed four times the limit of the decoding speed of the Viterbi decoders 27a to 27d. If the number of encoders and Viterbi decoders is increased, higher-speed data transmission becomes possible.

Although the data transmission apparatus of the above embodiment uses a convolutional code with a coding rate of 1/2, the data transmission apparatus according to the present embodiment can also use a convolutional code with a coding rate other than 1/2. A similar effect can be obtained by applying the present invention.

Further, in the data transmission apparatus of the above embodiment, the case where a Viterbi decoder is used as a decoder for performing error correction has been described, but the case where another decoder for performing error correction on a convolutional code is used is also used. By applying the present invention, the same function and effect can be obtained.

[0103]

As described above, according to the present invention,
When a plurality of encoders and error correction decoders are respectively installed in parallel, a change in the order of parallel data due to frequency division uncertainty in the serial / parallel converter can be easily detected with a simple circuit configuration and transmitted. This has the effect of being able to match the order on the side.

Further, according to the present invention, since the frame synchronization can be performed after the bit string order is determined, the frame synchronization circuit can be easily configured, and the size and cost of the device can be reduced, that is, the cost can be reduced. To play.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment of the present invention, where (a) is a block diagram illustrating a configuration of a modulation unit, and (b).
FIG. 3 is a block diagram illustrating a configuration of a demodulation unit.

FIG. 2 is a diagram showing a circuit configuration of an embodiment of the present invention.
FIG. 3A is a diagram illustrating a configuration of a modulation unit, and FIG. 3B is a diagram illustrating a configuration of a demodulation unit.

FIG. 3 is a time chart for explaining an operation of a modulation unit in one embodiment of the present invention.

FIG. 4 is a time chart for explaining an operation in a case where the phase of a reference carrier wave in the modulation / demodulation unit matches the phase of the carrier wave in the modulation unit and the frequency division phase in one embodiment of the present invention. .

FIG. 5 is a time chart for explaining an operation in a case where the phase of the reference carrier in the demodulation section matches the phase of the carrier in the modulation section and the dividing phase is shifted by 1 bit in one embodiment of the present invention. is there.

FIG. 6 is a diagram showing a configuration of a conventional data transmission device;
FIG. 3A is a diagram illustrating a configuration of a modulation unit, and FIG. 3B is a diagram illustrating a configuration of a demodulation unit.

FIG. 7 is a time chart for explaining an operation in a modulation section of a conventional data transmission device.

FIG. 8 is a time chart for explaining an operation in a case where the phase of a reference carrier in a demodulation unit of a conventional data transmission device matches the phase of a carrier of a modulation unit and the frequency division phase is shifted by one bit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Encoding means 12 Data conversion means 13 Parallel / serial conversion means 14 Quadrature modulation means 15 Quadrature demodulation means 16 Serial / parallel conversion means 17 Decoding means 18 Frequency division phase judgment means 19 Switching means 21, 61 Encoder 22 Data inverter 23, 63 Parallel / serial converter 24, 64 Quadrature modulator 25, 65 Quadrature demodulator 26, 66 Serial / parallel converter 27, 67 Viterbi decoder 28 Divided phase detector 29, 69 Switch 68 Synchronous word detector

Claims (3)

[Claims] An encoding means for convolutionally encoding a plurality of information bit strings to be transmitted for each of the strings and outputting an encoded bit string, and performing parallel / serial conversion on each of the encoded bit strings from the encoding means. Parallel / serial conversion means, quadrature modulation means for orthogonally modulating the output of the parallel / serial conversion means and transmitting a modulated signal to a transmission path, quadrature demodulating each of the transmitted modulated signals and outputting a demodulated signal. Demodulating means; serial / parallel converting means for serially / parallel converting the outputs of the quadrature demodulating means; and error correction decoding of each demodulated bit string converted by the serial / parallel converting means to correspond to the plurality of information bit strings. A decoding unit that outputs a decoded bit string to be converted, and a data conversion unit that converts data of each encoded bit string input to the parallel / serial conversion unit; A divided phase determining unit that determines a divided phase in the serial / parallel converting unit based on a four-phase uncertainty removal pattern signal output from the dividing unit, and outputs a determination signal; Switching means for switching the arrangement of the decoded bit strings according to the output determination signal. 2. The data transmission apparatus according to claim 1, wherein said encoding means convolutionally encodes n (n ≧ 3) information bit strings to be transmitted for each of the first and second information bit strings. 2
And n encoders for outputting encoded bits consisting of the following bit strings, wherein the data converting means includes a first bit string of a first column among the n columns and a second bit string of a bit string other than the first column. A first bit string group consisting of a bit string with the sign of the bit string inverted, and a second bit string consisting of a second bit string of a first column of the n columns and a first bit string of a bit string other than the first column A first parallel / serial converter for parallel / serial conversion of the first bit string group, and a second parallel / serial converter for parallel / serial conversion of the second bit string group. And a second serial / parallel converter, wherein the serial / parallel converter converts the output of the quadrature demodulator into a bit string of n columns, respectively. Wherein the decoding means comprises: the first and second serial It is provided with n Viterbi decoders that perform Viterbi decoding for each column pair corresponding to each other in two bit string groups output from the parallel converter, and output a decoded bit string and a four-phase uncertainty removal pattern signal, The divided phase determination means detects a first decoded bit string from the four-phase uncertainty removal pattern signals output from the n Viterbi decoders, and outputs the divided phase to the switching means. Outputting a determination signal, wherein the switching means switches the arrangement of the decoded bit strings so as to correspond to the sequence of the information bit strings according to the frequency division phase determination signal output from the frequency division phase determiner. apparatus. 3. A transmitting side, in which n (n.gtoreq.3) columns of information bit strings to be transmitted are convolutionally coded for each column, and a first bit for outputting coded bits consisting of first and second bit sequences is output.
To n-th encoding means, and outputs the first and second bit sequence outputs of the encoding means to (Xi, Yi) (where 1 ≦ i
≤ n), the output (X1, Y1) of the first encoding means is output as it is, and the output (Xj, Yj) of the second to nth encoding means is (Yj￣, Xj). (Where 2 ≦ jn, and ￣ indicates the inversion of Yi of the signal), and a first bit string group (X1, Y2￣,...) Output from the data converting means. Yn￣), and a second parallel / serial converter for parallel / serial conversion of the second bit string group (Y1, X2,..., Xn) output from the data conversion means. A parallel / serial converter; and quadrature modulation means for quadrature modulating the output of the first and second parallel / serial conversion means and transmitting a modulated signal to a transmission path. Orthogonal demodulation means for orthogonally demodulating a signal and outputting a demodulated signal; 2 output the output of the regulating means and the first and second serial / parallel converter for serial / parallel conversion on the bit string of the n columns respectively, from said first and second serial / parallel converter
The first to n-th decoding means for performing Viterbi decoding for each column pair corresponding to each other in one bit string group, and outputting a decoded bit string and a four-phase uncertainty removal pattern signal; frequency-divided phase determining means for determining a frequency-divided phase in the serial / parallel conversion means based on a four-phase uncertainty removal pattern signal output from n decoding means, and outputting a determination signal; Switching means for switching the arrangement of the decoded bit strings so as to correspond to the arrangement of the bit strings on the transmission side in accordance with the judgment signal output from the judging means.