JPH10150053A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the high-frequency characteristics of a transistor by setting the conducting type of a semiconductor region at a part facing a base electrode with an insulating film in-between as the first conducting type so as to decrease the parasitic capacitance generated between the part and the base electrode. SOLUTION: A part, which faces a base electrode wiring 40 through an insulating film 20 in a collector region 14, is made to be a P-type region 22. The region is formed at the lower part of a base-electrode bonding pad and a drawing part 40A in the base electrode wiring 40 in the shape approximately equal to these parts and electrically connected to a P-type substrate 12. The potential of the P-type substrate 12 is made to be the same potential as an emitter potential. At the ordinary time, the potential is kept at the ground potential, i.e., 0volt. Thus, the base electrode wiring 40 does not form the MIS structure through the insulating film 20, the parasitic capacitance between the base and the collector is strikingly decreased and the high-frequency characteristics of a transistor can be remarkably improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same. More specifically, the present invention relates to a high-frequency amplification bipolar transistor having small parasitic capacitance and excellent frequency characteristics, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Bipolar transistors used in a high frequency band of 1 GHz to 2 GHz or higher are:
It is arranged at the first stage of the input unit of various communication devices and plays an important role. For example, in recent years, mobile phones and PHSs (personal handy-phones), which are rapidly spreading, have been recently developed.
systems) are key components that determine their performance. In addition, Si / Ge-based hetero bipolar transistors, which have been rapidly developed in recent years, are key components in a front-end portion such as a satellite broadcast receiver using a frequency band of 10 GHz or more.

FIG. 6 is a schematic diagram illustrating the structure of a conventional discrete bipolar transistor used as such a low noise amplifier. That is,
FIG. 6A is a schematic plan view thereof. FIGS. 6B and 6C respectively show XX of FIG. 6A.
It is the schematic sectional drawing cut | disconnected by the cutting line and the YY cutting line, and seen from the arrow direction.

In FIG. 6A, a bipolar transistor chip 100 is mounted on a collector lead frame 180. And the chip 10
0, a base electrode wiring 1 as a base wiring layer
40 and bonding pads 150, and emitter electrode wiring 145 and bonding pads 152, 152 are formed. The base electrode bonding pad 150 is connected to the base lead frame 185 by the wire 160. The emitter electrode bonding pad 152 is connected to the lead frames 190 and 192 for the emitter by wires 165 and 166, respectively.

The sectional structure will be described below with reference to FIGS. 6 (b) and 6 (c).

The transistor 100 has a structure in which an n-type collector / epitaxial layer 104 is stacked on an n-type substrate 102. A part of the collector layer 104 has p
A mold base region 106 is formed, and an n-type emitter region 108 is formed in a part of the base region 106. Then, the upper surface of the transistor 100 is
Covered by 10. A part of the insulating film 110 above the p-type base region 106 is opened to form a base electrode wiring 140. Further, in the insulating film 110,
The upper part of the n-type emitter region 108 is opened to form an emitter electrode wiring 145.

One of the important characteristics when using such a bipolar transistor in a high frequency band is a high frequency gain. The high-frequency gain depends on the parasitic capacitance between the base and the collector. If the parasitic capacitance is large, the high-frequency gain is reduced. The main elements constituting the base-collector capacitance in the conventional high-frequency discrete transistor shown in FIG. 5 are (i) the parasitic capacitance at the junction between the n-type collector region 104 and the p-type base region 106, and (ii) ) Insulating film 110 is connected to base electrode wiring 140 and n
MI caused by being sandwiched between
Parasitic capacitance of the S structure, and (iii) parasitic capacitance generated between the collector lead frame 180 and the base lead frame 185 can be cited. Therefore, in order to improve the high frequency characteristics of the transistor, it is necessary to reduce these parasitic capacitances. Then, a structure for reducing “(iii) those caused by the lead frame” among the above three types of parasitic capacitances has been proposed.

FIGS. 7A to 7C are conceptual diagrams showing the structure of such an improved conventional transistor.
Here, FIG. 1A is a schematic plan view thereof,
(B) and (c) are schematic sectional views cut along the XX cutting line and the YY cutting line in FIG.

As shown in FIG. 7A, the transistor 101 is mounted on a lead frame 190 for an emitter. On the upper surface of the transistor 101, a base electrode wiring 140 and a pad 150 are formed as a base wiring layer. Further, an emitter electrode wiring 145 and pads 152 and 152 are formed as an emitter wiring layer, and a collector electrode wiring 1 is formed as a collector wiring layer.
47 and pads 154 are formed. The base electrode bonding pad 150 is connected to the base lead frame 185 by the wire 160. Also, the emitter electrode bonding pads 152, 152
Are connected to emitter lead frames 190, 190 by wires 165, 166, respectively. Further, the collector electrode bonding pad 154 is connected to the collector lead frame 182 by a wire 170.

The sectional structure will be described below with reference to FIGS. 7B and 7C. The transistor 101 has p
N-type collector epitaxial layer 1 on mold substrate 102
04 are laminated. Here, the n-type buried region 10 is partially provided between the substrate 102 and the collector layer 104.
3 are formed. A p-type base region 106 is formed in a part of the collector layer 104, and an n-type emitter region 108 is formed in a part of the base region 106. Further, an n-type collector extraction region 109 is formed in a part of the collector layer 104. The upper surface of the transistor 100 is covered with an insulating film 110. A part of the insulating film 110 above the p-type base region 106 is opened to form a base electrode wiring 140. In the insulating film 110, the n-type emitter region 10
The upper part of 8 is opened to form an emitter electrode wiring 145. Further, a part of the insulating film 110 above the n-type collector extraction region 109 is opened to form a collector electrode wiring 147.

In the transistors shown in FIGS. 7A to 7C, the base lead frame 185 and the collector lead frame 182 are connected to the emitter lead frame 19.
Shielded by 0. Moreover, the emitter lead frame is normally held at ground potential, ie, 0 volts. Accordingly, the base lead frame 185
The parasitic capacitance between the lead frame 182 and the collector lead frame 182 is reduced to a negligible level. As a result, the high-frequency gain is improved over the transistor shown in FIG.

[0012]

[0007] However, FIGS.
Even the transistor shown in FIG. 1C may not be enough to obtain good characteristics in a high frequency band. Here, when the parasitic capacitance between the base and the collector of the conventional transistor was measured, it was about 0.5 pF for the transistor shown in FIG. 6 and about 0.2 pF for the transistor shown in FIG. . On the other hand, in order to evaluate the high frequency characteristics of the transistor, the gain for a DC input signal and the gain for a 2 GHz input signal were measured, and the following results were obtained. That is, in the transistor having the structure shown in FIG.
At B, the gain at 2 GHz was about 8 dB. on the other hand,
In the transistor having the structure shown in FIG. 7, the gain for a DC signal is 14 dB, and the gain at 2 GHz is about 10 dB.
Met. In other words, the improved type transistor as shown in FIG. 7 has improved high-frequency characteristics as compared with the transistor shown in FIG.
dB also decreases, and for use in the 2 GHz band,
It turned out that the frequency characteristic was not enough.

The present invention has been made in view of such a point. That is, an object of the present invention is to provide a transistor having improved high-frequency characteristics and a method of manufacturing the same by proposing a novel chip structure capable of reducing the parasitic capacitance between the base and the collector. is there.

[0014]

That is, a semiconductor device according to the present invention comprises a semiconductor substrate of a first conductivity type, a collector region made of a semiconductor of a second conductivity type, and a base region made of a semiconductor of a first conductivity type. A semiconductor device having an emitter region made of a semiconductor of the second conductivity type, an insulating film formed thereon, and a base electrode connected to the base region through an opening provided in the insulating film. Wherein the conductivity type of a portion of the semiconductor region facing the base electrode with the insulating film interposed therebetween is a first conductivity type so as to reduce a parasitic capacitance generated between the semiconductor region and the base electrode. It is configured to be characterized by having.

Further, the semiconductor device according to the present invention comprises a semiconductor substrate of a first conductivity type, a collector layer made of a semiconductor of a second conductivity type formed on the semiconductor substrate, and a part of the surface side of the collector layer. A base region formed by using the first conductivity type, an emitter region formed by using a portion of the surface side of the base region on the second conductivity type, the collector layer, the base layer, and the emitter layer An insulating film covering the surface of the insulating film, a base wiring layer disposed on the insulating film and connected to the base region through an opening provided in the insulating film, and an insulating film disposed on the insulating film; And an emitter wiring layer connected to the emitter region through an opening provided in the semiconductor device, wherein the semiconductor portion faces the base wiring layer with the insulating film interposed therebetween. The semiconductor portion that does not belong to any of the base region and the emitter region is substantially of the first conductivity type from the contact surface with the insulating film to the semiconductor substrate. The configuration is such that the parasitic capacitance generated between the two is reduced.

Further, in the above-described semiconductor device, the second conductive portion is provided between the semiconductor portion having the substantially first conductivity type and the base region so that they are not electrically short-circuited. A semiconductor part of the mold can be provided.

Further, in the above-described semiconductor device, a semiconductor portion that does not belong to any of the base region and the emitter region among the semiconductor portions facing the emitter wiring layer with the insulating film interposed therebetween is the same as the semiconductor device. Since the semiconductor substrate is substantially of the first conductivity type from the contact surface with the insulating film to the semiconductor substrate, the parasitic capacitance generated between the semiconductor substrate and the emitter electrode can be reduced.

In the above-described semiconductor device, a resistive element is connected to the base wiring layer on the insulating film, and a semiconductor portion facing the resistive element with the insulating film interposed therebetween is the insulating film. Is substantially of the first conductivity type from the contact surface to the semiconductor substrate,
It is possible to reduce the parasitic capacitance generated with the resistance element.

Further, the semiconductor device according to the present invention includes a semiconductor substrate of a first conductivity type, a collector layer made of a semiconductor of a second conductivity type formed on the semiconductor substrate, and a part of a surface side of the collector layer. A base region formed by using the first conductivity type, an emitter region formed by using a portion of the surface side of the base region on the second conductivity type, the collector layer, the base layer, and the emitter layer An insulating film covering the surface of the insulating film, a base wiring layer disposed on the insulating film and connected to the base region through an opening provided in the insulating film, and an insulating film disposed on the insulating film; And an emitter wiring layer connected to the emitter region through an opening provided in the semiconductor device. The semiconductor portion that does not belong to any of the emitter regions is substantially of the first conductivity type from the contact surface with the insulating film to the semiconductor substrate, so that the base wiring layer and the emitter wiring layer The configuration is such that the parasitic capacitance generated between the two is reduced.

Further, in the above-described semiconductor device, the second conductive portion is provided between the semiconductor portion having the substantially first conductivity type and the base region so that they are not electrically short-circuited. A semiconductor part of the mold can be provided.

Further, in the semiconductor device according to the present invention, in a planar type bipolar transistor formed on a semiconductor substrate, a portion of a collector layer facing a base wiring layer via an insulating film is not short-circuited to a base region. The MIS capacitance formed under the base wiring layer is reduced by making the same conductivity type as that of the substrate while keeping a constant interval between them, so that the MIS capacitance formed under the base wiring layer is reduced. Is done.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a collector layer made of a semiconductor of a second conductivity type on a semiconductor substrate of a first conductivity type; A step of forming a base region by using one conductivity type; a step of forming an emitter region by setting a part of the surface side of the base region to a second conductivity type; the collector layer, the base layer, and the emitter A method of manufacturing a semiconductor device, comprising: a step of covering a surface of a layer with an insulating film; and a step of forming a base wiring layer connected to the base region through an opening provided in the insulating film on the insulating film. In the semiconductor portion facing the base wiring layer with the insulating film interposed therebetween, the semiconductor portion does not belong to any of the base region and the emitter region and is in contact with the base region. The semiconductor portion of the first conductivity type from the contact surface with the insulating film to the semiconductor substrate is made to be of the first conductivity type, so that the semiconductor portion of the first conductivity type does not short-circuit with the base region, and The configuration is such that the parasitic capacitance generated between the layers is reduced.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the present invention, as an element for limiting the high-frequency gain of a transistor, the second one of the three types of parasitic capacitances described above is called "the insulating film 110 is connected to the base electrode wiring 140 and the n-type collector. By reducing the “parasitic capacitance of the MIS structure caused by being sandwiched between the region 104”, the high-frequency characteristics of the transistor are improved.

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are conceptual diagrams showing the structure of a transistor according to the present invention. That is, FIG. 1 is a schematic plan view thereof, and FIG.
(A), (b) and (c) are respectively cut along the XX cutting line, the YY cutting line and the ZZ cutting line in FIG. FIG.

As shown in FIG.
Are mounted on a lead frame 90 for an emitter. On the upper surface of the transistor 11, a base electrode wiring 40 and a base electrode bonding pad 50 are formed as a base wiring layer. Further, an emitter electrode wiring 45 and emitter electrode bonding pads 52 and 52 are formed as an emitter wiring layer, and a collector electrode wiring 47 and a collector electrode bonding pad 54 are formed as a collector wiring layer. The base electrode bonding pad 50 is connected to the wire 6
0 is connected to the base lead frame 85. Also, the emitter electrode bonding pads 52, 5
2 is connected to emitter lead frames 90, 90 by wires 65, 66, respectively. Further, the collector electrode bonding pad 54 is connected to a collector lead frame 82 by a wire 70. The emitter electrode wiring 45 and the collector electrode wiring 4
Numeral 7 is electrically insulated at the intersection 46 via an insulating film.

Next, the sectional structure is shown in FIG.
Description will be made with reference to (b) and (c). The transistor 11 has a structure in which an n-type collector layer 14 is stacked on a p-type substrate 12. The carrier concentration of the p-type substrate 12 can be, for example, 10 ¹⁵ cm ⁻³ . Also, n
The carrier concentration of the type collector layer 14 is, for example, 10 ¹⁶ c
m ⁻³ . Here, an n-type buried region 13 is partially formed between the substrate 12 and the collector layer 14. The buried region 13 has a low resistance at a carrier concentration of about 10 ²⁰ cm ⁻³ , and functions as a conductor that guides a collector current to the collector extraction region 19. A p-type base region 16 is formed in a part of the collector layer 14, and an n-type emitter region 18 is formed in a part of the base region 16. Here, the depth of the base region 16 can be about 0.2 μm from the surface. Further, an n-type collector extraction region 19 is formed in a part of the collector layer 14. The upper surface of the transistor 11 is covered with the insulating film 20. A part of the insulating film 20 above the p-type base region 16 is opened to form a base electrode wiring 40. A part of the insulating film 20 above the n-type emitter region 18 is opened to form an emitter electrode wiring 45. Further, in the insulating film 20, the n-type collector extraction region 19
The upper part is opened to form a collector electrode wiring 47.

Here, in the present invention, in the collector region 14, the base electrode wiring 40
The part opposite to is defined as a p-type region 22. This p
The mold region 22 is shown in FIGS. 2A and 2C. Further, as can be seen from FIG. 1 which shows the transistor in plan view, the p-type region 22 substantially coincides with the base electrode bonding pad 50 and the lower portion of the extraction portion 40A of the base electrode wiring 40. It is formed in a shape. The p-type region 22 is formed on the p-type substrate 12
Is electrically connected to Also, this p-type substrate 12
It is the same potential as the emitter potential and is normally kept at ground potential, ie, 0 volts. Thus, according to the present invention,
Unlike the conventional structure, the base electrode wiring 40 is
No MIS structure is formed through the structure. As a result, the parasitic capacitance between the base and the collector is significantly reduced,
The high-frequency characteristics of the transistor were significantly improved.

The measured capacitance between the base and the collector of the transistor according to the present invention was 0.1 pF. That is, the capacitance value of the conventional transistor shown in FIG.
It was half of 2 pF. Further, the gain at 2 GHz of the transistor according to the present invention is 14 dB,
Almost flat frequency characteristics could be obtained up to GHz.
That is, in the case of the conventional improved transistor shown in FIG. 6, the gain at 2 GHz is about 10 dB, and the frequency characteristic is remarkably improved as compared with 4 dB lower than the direct current. I understood.

Next, a method for manufacturing a transistor according to the present invention will be described with reference to FIGS. 1 and 2A to 2C. First, on the surface of the p-type silicon substrate 12,
An oxide film having an opening in a region to be the n-type buried region 13 is formed. Subsequently, for example, arsenic (As), antimony (Sb), or the like is introduced as an n-type impurity into the opening by, for example, a method such as thermal diffusion.
Form 3

Next, an n-type collector layer 14 is formed on the surface of the substrate 12 by epitaxial growth. This crystal growth is performed, for example, by thermally decomposing silane (SiH ₄ ) and a phosphorus compound (for example, PH ₃ ) at a high temperature to deposit an n-type silicon layer on the substrate 12. The layer thickness can be, for example, about 1 μm. That is, in order to improve the high frequency characteristics of the transistor,
It is necessary to reduce the traveling time of carriers between the emitter, base and collector. From this viewpoint, in order to obtain good characteristics in the 1 GHz band, the thickness of the n-type collector layer is 1 μm.
m or less. The carrier concentration can be, for example, 10 ¹⁶ cm ⁻³ .

Further, the wafer is exposed to a high-temperature oxidizing atmosphere to form an oxide film on the surface of the n-type collector layer 14, and the p-type region 22 is opened. For example, a p-type impurity such as boron (B) is selectively ion-implanted into the opening,
The p-type region 22 can be formed by activating by heat treatment and promoting diffusion. The p-type region 22 thus formed has a carrier concentration near the surface of about 10 ¹⁸ to 10 ¹⁹ cm ⁻³ , and the p-type substrate 12
The structure can be a p-type. Further, such a p-type region 22 may be formed by another method, for example, by using BS
It can also be formed by solid-phase diffusion using a G (boron silicate glass) film. That is, the p-type region 22 in the present invention may be formed by any method as long as the MIS structure under the base electrode can be electrically short-circuited to the p-type substrate 12.

After the formation of the p-type region 22, the transistor can be completed by a process similar to the conventional one. That is, exposing the wafer to a high temperature oxidizing atmosphere,
The insulating film 20 is formed by oxidizing the surface. Further, an opening is formed in a part of the insulating film 20 to form an n-type collector extraction region 19. Further, by the same process, the p-type base region 16 is formed by base diffusion, and the n-type emitter region is formed by emitter diffusion. Then, an insulating film is further formed on the wafer surface, and respective wirings are formed in predetermined openings, whereby the transistor 11 is completed.

As described above, the transistor according to the present invention can be manufactured only by adding patterning and diffusion steps for forming the p-type region 22 to the conventional transistor manufacturing process. That is, according to the present invention, the conventional manufacturing process and manufacturing apparatus are hardly changed,
A high-performance transistor can be obtained.

In forming the p-type region 22 according to the present invention, first, it is necessary to form the p-type region so as to reliably reach the substrate 12 in the depth direction of the wafer. Further, in the in-plane direction of the wafer, it is necessary to form the p-type region 22 at regular intervals so as not to short-circuit the p-type base region 16. However, in order to reduce the parasitic capacitance, it is desirable to make the p-type region 22 beneath the base electrode as much as possible. That is, the p-type region 2
2 is preferably formed so as to fill under the base electrode as widely as possible without causing a short circuit with the base region 16.

Next, a first modification of the present invention will be described. FIG. 3 is a conceptual diagram illustrating a first modification of the present invention. That is, FIG. 1A is a schematic plan view thereof,
(B) and (c) correspond to X- in FIG.
It is the schematic sectional drawing which cut | disconnected by the X cutting line and the YY cutting line, and looked at the principal part from the arrow direction.

In this modification, a p-type region is formed not only under the base electrode but also under the emitter electrode.
That is, first, as shown in FIGS. 3A and 3B, the p-type region 22 is formed with a base electrode bonding pad 50 which is a part of the base wiring layer and a lead portion 40A of the base electrode wiring 40. Are formed in the lower part of the base plate in a shape almost corresponding to them. Further, p-type region 2
As shown in FIGS. 3 (a) and 3 (c), 2 is also formed below the emitter electrode bonding pad 52 and the extraction portion 45A of the emitter electrode wiring so as to have a shape substantially coinciding therewith. . The other parts are denoted by the same reference numerals as in FIG. 1 and the description is omitted.

As described above, by forming the p-type region 22 below the emitter electrode, the parasitic capacitance between the emitter and the collector can be reduced. That is, in the conventional structure shown in FIG. 7, for example, the emitter electrode bonding pads 52, 52 and the emitter electrode wiring 45
Are opposed to the collector layer 14 via the insulating film 20. Then, a parasitic capacitance due to the MIS structure occurs.

According to this modification, however, the emitter potential is set by setting the p-type region 22 under the emitter electrode bonding pads 52, 52 and the lead-out portion 45A of the emitter electrode wiring. Therefore, the emitter-collector parasitic capacitance can be reduced.

Next, a second modification of the present invention will be described. FIG. 4 is a conceptual diagram illustrating a second modified example of the present invention. That is, FIG. 1A is a schematic plan view thereof,
4 (b) and (c) respectively show X-
It is the schematic sectional drawing which cut | disconnected by the X cutting line and the YY cutting line, and looked at the principal part from the arrow direction. In addition, FIG.
In (c), the same portions as those of the above-described transistor are denoted by the same reference numerals, and description thereof is omitted.

In this modification, the np of the transistor
The entire outer peripheral portion of the n-junction region is a p-type region 22. That is, in the region indicated by the broken line in FIG. 4A, the p-type region 22 is formed on the substrate 12. Also in the present modification, as described above, the parasitic capacitance between the base and the collector below the base wiring layer and the parasitic capacitance between the emitter and the collector below the emitter wiring layer can be reduced. Further, as described above, by making the entire outer peripheral portion of the transistor 13 the p-type region 22, the outer peripheral portion of the transistor 13 is maintained at the emitter potential, that is, the ground potential, and a shielding effect is generated. That is, the transistor 13 is shielded from electrical noise such as electromagnetic waves and static electricity, and can operate more stably.

Next, a third modification of the present invention will be described. FIG. 5 is a conceptual diagram illustrating a third modification of the present invention. That is, FIG. 1A is a schematic plan view thereof,
5 (b) and (c) respectively show X-
It is the schematic sectional drawing which cut | disconnected by the X cutting line and the YY cutting line, and looked at the principal part from the arrow direction. In addition, FIG.
In (c), the same portions as those of the above-described transistor are denoted by the same reference numerals, and description thereof will be omitted.

In this modification, a resistor 56 made of a polysilicon layer is connected to the tip of the base electrode wiring 40 of the transistor, and the electrode pad 50 is connected to the other end of the resistor 56. The resistor 56 plays a role of constituting a part of a base voltage supply circuit, for example. In the present modification, the p-type region 22 is formed below the lead portion of the base electrode wiring, the resistor 56, and the electrode pad 50 so as to have substantially the same shape as those in plan view. That is, in the present modification, by providing the p-type region 22 also under the resistor 56 added to the base wiring layer, the parasitic capacitance caused by the MIS structure in that portion can be reduced. Therefore, the base electrode wiring pattern on the insulating film 20 can be formed longer than before, and a resistor or other circuit component can be formed in the middle of the base electrode wiring without increasing the parasitic capacitance. become.

[0043]

The present invention is embodied in the form described above, and has the following effects.

That is, the transistor according to the present invention comprises:
It is possible to reduce the base-collector capacitance to about half of the conventional value. Further, it is possible to obtain a substantially flat frequency characteristic from DC to 2 GHz. That is, in the case of the conventional improved transistor, the gain at 2 GHz is about 4
It is remarkably improved as compared with the fact that it has been reduced by dB. Moreover, according to the present invention, such a high-performance transistor can be manufactured by a simple process. That is, it is only necessary to add a p-type region forming step without basically changing the conventional element structure and process.

Further, according to the present invention, the emitter-collector parasitic capacitance can be reduced by setting the p-type region below the portion where the emitter electrode bonding pad and the lead of the emitter electrode wiring are drawn.

Further, according to the present invention, the entire outer peripheral portion of the transistor is a p-type region, so that the outer peripheral portion of the transistor is maintained at the emitter potential, that is, the ground potential, and a shielding effect is produced. That is, the transistor is shielded from electric noise such as electromagnetic waves and static electricity, and can operate more stably.

Further, according to the present invention, the base wiring pattern can be formed longer than before and the resistance and other circuit components can be formed on the insulating film without increasing the parasitic capacitance. Become.

That is, according to the present invention, a transistor having low base-collector parasitic capacitance and greatly improved frequency characteristics can be obtained by a simple process, and the industrial merit is great. .

[Brief description of the drawings]

FIG. 1 is a schematic plan view illustrating a configuration of a transistor according to the present invention.

2 (a), (b) and (c) are cut along the XX cutting line, YY cutting line and ZZ cutting line in FIG. FIG.

FIG. 3 is a conceptual diagram illustrating a first modification of the present invention. That is, (a) is a schematic plan view thereof,
(B) and (c) are schematic sectional views cut along the XX cutting line and the YY cutting line of (a), respectively, and viewing the main part from the direction of the arrow.

FIG. 4 is a conceptual diagram illustrating a second modification of the present invention. That is, (a) is a schematic plan view thereof,
(B) and (c) are schematic sectional views cut along the XX cutting line and the YY cutting line of (a), respectively, and viewing the main part from the direction of the arrow.

FIG. 5 is a conceptual diagram illustrating a third modification of the present invention. That is, (a) is a schematic plan view thereof,
(B) and (c) are schematic sectional views cut along the XX cutting line and the YY cutting line of (a), respectively, and viewing the main part from the direction of the arrow.

FIG. 6 is a conceptual diagram illustrating a configuration of a conventional transistor. That is, (a) is a schematic plan view, and (b) and (c) are cut along the XX cutting line and the YY cutting line of (a), respectively. It is the schematic sectional drawing which looked at the part.

FIG. 7 is a conceptual diagram showing a configuration of an improved conventional transistor. That is, (a) is a schematic plan view, and (b) and (c) respectively show X-
It is the schematic sectional drawing which cut | disconnected by the X cutting line and the YY cutting line, and looked at the principal part from the arrow direction.

[Explanation of symbols]

 11, 12, 13, 14 Transistor 12 Substrate 13 N-type buried layer 14 N-type collector layer 16 P-type base region 18 Emitter region 19 N-type extraction region 20 Insulating film 22 P-type region 40 Base electrode wiring 40A Base electrode wiring lead portion 45 Emitter electrode wiring 47 Collector electrode wiring 50 Base electrode bonding pad 52 Emitter electrode bonding pad 54 Collector electrode bonding pad 60, 65, 66, 70 Wire 82 Collector lead frame 85 Base lead frame 90 Emitter lead frame 100 , 101 transistor 102 substrate 103 n-type buried layer 104 n-type collector layer 106 p-type base region 108 emitter region 19 n-type extraction region 110 insulating film 140 base electrode wiring 14 5 Emitter electrode wiring 147 Collector electrode wiring 150 Base electrode bonding pad 152 Emitter electrode bonding pad 154 Collector electrode bonding pad 160, 165, 166, 170 Wire 182 Collector lead frame 185 Base lead frame 190 Emitter lead frame

Claims (9)

[Claims] A first conductivity type semiconductor substrate; a second conductivity type semiconductor; a collector region; a first conductivity type semiconductor; a base region; a second conductivity type semiconductor; A semiconductor device comprising: an insulating film formed thereon; and a base electrode connected to the base region through an opening provided in the insulating film, wherein the base electrode has the insulating film interposed therebetween. A semiconductor device in which a portion of the semiconductor region opposite to the first region has a first conductivity type so as to reduce a parasitic capacitance generated between the semiconductor region and the base electrode. 2. A semiconductor substrate of a first conductivity type, a collector layer made of a semiconductor of a second conductivity type formed on the semiconductor substrate, and a part of the surface side of the collector layer being of the first conductivity type. A base region formed by the above, an emitter region formed by making a part of the surface side of the base region a second conductivity type, an insulating film covering surfaces of the collector layer, the base layer, and the emitter layer. A base wiring layer disposed on the insulating film and connected to the base region through an opening provided in the insulating film, and a base wiring layer disposed on the insulating film and passing through an opening provided in the insulating film. And an emitter wiring layer connected to the emitter region, wherein the base region and the emitter of a semiconductor portion facing the base wiring layer with the insulating film interposed therebetween. Since the semiconductor portion that does not belong to any of the heater regions is substantially of the first conductivity type from the contact surface with the insulating film to the semiconductor substrate, a parasitic capacitance generated between the semiconductor portion and the base electrode. A semiconductor device that reduces noise. 3. A semiconductor portion of a second conductivity type is provided between the semiconductor portion having the substantially first conductivity type and the base region so that they are not electrically short-circuited. 3. The semiconductor device according to claim 2, wherein: 4. A semiconductor portion that does not belong to any of the base region and the emitter region, of a semiconductor portion facing the emitter wiring layer with the insulating film interposed therebetween, from a contact surface with the insulating film. 4. The semiconductor according to claim 2, wherein the semiconductor substrate is substantially of the first conductivity type to reduce a parasitic capacitance generated between the semiconductor substrate and the emitter electrode. apparatus. 5. A semiconductor device, wherein a resistance element is connected to the base wiring layer on the insulating film, and a semiconductor portion facing the resistance element with the insulating film interposed therebetween is connected to the semiconductor substrate from a contact surface with the insulating film. 5. The semiconductor device according to claim 2, wherein the semiconductor device is substantially of the first conductivity type to reduce parasitic capacitance generated with the resistance element. 6. A semiconductor substrate of a first conductivity type, a collector layer made of a semiconductor of a second conductivity type formed on the semiconductor substrate, and a part of a surface side of the collector layer being a first conductivity type. A base region formed by the above, an emitter region formed by making a part of the surface side of the base region a second conductivity type, an insulating film covering surfaces of the collector layer, the base layer, and the emitter layer. A base wiring layer disposed on the insulating film and connected to the base region through an opening provided in the insulating film, and a base wiring layer disposed on the insulating film and passing through an opening provided in the insulating film. And an emitter wiring layer connected to the emitter region, wherein the semiconductor portion in contact with the insulating film does not belong to any of the base region and the emitter region. The semiconductor portion is substantially of the first conductivity type from the contact surface with the insulating film to the semiconductor substrate, thereby reducing parasitic capacitance generated between the base wiring layer and the emitter wiring layer. A semiconductor device designed to be reduced. 7. A semiconductor portion of a second conductivity type is provided between the semiconductor portion having the substantially first conductivity type and the base region so that they are not electrically short-circuited. The semiconductor device according to claim 6, wherein: 8. In a planar type bipolar transistor formed on a semiconductor substrate, a collector layer in a portion facing a base wiring layer via an insulating film is spaced apart from the base region by a predetermined distance so as not to be short-circuited. By making it the same conductivity type as the substrate, so that it has the same potential as the substrate,
A semiconductor device, wherein a MIS capacitance formed below the base wiring layer is reduced. 9. A step of forming a collector layer made of a semiconductor of a second conductivity type on a semiconductor substrate of a first conductivity type, and forming a base region by making a part of the surface side of the collector layer a first conductivity type. Forming, forming an emitter region by making a part of the surface side of the base region a second conductivity type, covering the surfaces of the collector layer, the base layer, and the emitter layer with an insulating film; Forming a base wiring layer connected to the base region through an opening provided in the insulating film on the insulating film, the method comprising the steps of: Of the semiconductor portion facing the base wiring layer, a semiconductor portion that does not belong to any of the base region and the emitter region and that is not in contact with the base region is a contact surface with the insulating film. From the first conductive type to the semiconductor substrate so that the semiconductor portion of the first conductive type is not short-circuited to the base region, and the parasitic capacitance generated between the semiconductor portion and the base wiring layer is reduced. A method for manufacturing a semiconductor device, comprising: