JPH10150000A - Manufacture of semiconductor device and semiconductor device therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a conductor device and method in which shallow junctions are formed by implanting ions containing boron as an impurity into the gate, source, and drain areas of the device. SOLUTION: An N-type well 102, a P-type well, a gate insulating film 103, a polysilicon gate area 104, and an extension section are successively formed on a silicon substrate 101. Then a source area and a drain area 107 are formed by simultaneously implanting boron-containing ions, such as boron dichloride ions, etc., having a mass number of at least 50 into a polysilicon gate area 104 and above the wells and heat-treating the implanted areas and the ions are activated. Since the silicon is transformed into amorphous silicon by instantaneously heating the silicon to a high temperature and/or implanting ions of silicon, etc., before and after implanting the boron-containing ions, the boron- containing ions can be activated at a high rate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device. In particular, the method is characterized in that a compound ion such as boron dichloride having a mass number of 50 or more (BCl ₂ ⁺ or the like) is implanted as an impurity into the gate region, the source region, and the drain region as an impurity, and then heat-treated to activate. The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In recent years, MOS type field effect transistors having a P type polysilicon gate have been increasingly used.
This is because this transistor uses a surface channel, and has advantages such as a low threshold value.

Conventionally, in the manufacturing method of the transistor, making a shallow junction source and drain portions, and boron ions in order to lower the resistance of the gate (B ⁺⁾ or 2 boron fluoride ions (BF ₂ ⁺⁾ To perform activation.

However, when boron difluoride ions are used, a large amount of fluorine is introduced into the gate, so that boron penetrates the gate oxide film. This is shown by the boron impurity concentration profile in FIG. For this reason,
The following problems have occurred.

(1) The threshold value of the transistor changes.

(2) The gate breakdown voltage deteriorates.

As a means for solving this problem, Japanese Patent Application Laid-Open No. 5-160148 discloses a method of implanting boron monochloride ion (BCl ⁺ ) containing no fluorine.

[0008] In addition, a technique of using ions having the following mass numbers as ions to be implanted is also conventionally used.

[0009] Boron ion (mass number 10, 11).

Boron difluoride ion (mass number 48, 4
9).

1 Boron chloride ion (mass number 45, 46,
47, 48).

However, when a dual gate type MOS field effect transistor is manufactured according to these prior arts, the following problems also occur.

(3) The throughput is greatly reduced.

This is for the following reason. Since the mass number of ions is small, the range of ion implantation is large. Therefore, the depth at which the ions are implanted increases. Therefore, when it is necessary to implant the ions not only in the gate but also in the source and drain regions at the same time, it is necessary to implant the ions with very low energy in order to ensure shallow coupling. For this purpose, it is necessary to keep the implantation current of the ion implantation apparatus low, but this is difficult due to the structure of the apparatus.

Here, a shallow junction means a junction having a junction depth (often represented by "Xj" in the art) of about 0.13 μm to 0.15 μm. Such bonding is particularly necessary when manufacturing a semiconductor device having a 0.25 μm rule.

The problem resulting from the small mass number of ions to be implanted is in the above-described method of manufacturing a P-type field-effect transistor. In a method for manufacturing an N-type field-effect transistor, ions containing arsenic having a mass number as large as 75 can be used. In this case, since the mass number of arsenic is large, the range becomes small, and a shallow junction can be formed.

[0017]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has been made in consideration of the following problems.
In a method of manufacturing a MOS type semiconductor having a source region and a drain region, an object is to form these regions by implanting ions containing boron, activate the ions by heat treatment, and simultaneously form a shallow junction. .

[0018]

The invention for achieving the above object is the following invention.

A first invention is a method for manufacturing a semiconductor device, comprising the following steps.

(A) A gate insulating film on a silicon substrate,
Forming a gate region on the gate insulating film and a sidewall in contact with the gate insulating film and the gate region on the silicon substrate, respectively, and (b) forming a mass number of 50 on the gate region and the silicon substrate. (C) heating the gate region and the silicon substrate to form a source region and / or a drain region in the silicon substrate, and (c) heating the gate region and the silicon substrate. Activating the.

According to the present invention, by implanting a compound ion containing boron and having a large mass number, a semiconductor device can be manufactured in which boron does not penetrate an insulating film and a shallow junction is realized.

A second invention is a method of manufacturing a semiconductor device, wherein the compound ion containing boron having a mass number of 50 or more is boron dichloride ion. According to the present invention, a semiconductor device using boron dichloride ion as an impurity can be manufactured.

In a third aspect, in the step (c),
A method for manufacturing a semiconductor device, wherein a heating temperature is 1100 ° C. or more and 1200 ° C. or less, and a heating time is 1 second or less. According to the present invention, compound ions can be activated and the semiconductor device can be prevented from being damaged by instantaneous heating.

According to a fourth aspect, before or after the step (b), there is further provided a step of implanting silicon ions or germanium ions into the gate region and / or the silicon substrate to perform amorphization. A method for manufacturing a semiconductor device characterized by the following. According to the present invention, activation of compound ions can be achieved.

According to a fifth aspect of the present invention, the depth at which the silicon ions or the germanium ions are implanted into the gate region and / or the silicon substrate is such that the ions containing boron having a mass number of 50 or less are formed in the gate region. And / or a depth equal to or less than a depth at which ions are implanted into the silicon substrate. According to the present invention, activation of compound ions can be achieved.

According to a sixth aspect of the present invention, before or after the step (b), silicon ions are added to the gate region and / or the silicon substrate in an amount of 5 × 10 ¹⁴ / cm ² or more and 5 × 10 ¹⁴ / cm ² or more.
A method of manufacturing a semiconductor device, comprising a step of performing ion implantation under conditions of 10 ¹⁶ / cm ² or less to perform amorphization. According to the present invention, activation of compound ions can be achieved.

According to a seventh aspect of the present invention, before or after the step (b), germanium ions are added to the gate region and / or the silicon substrate in an amount of 5 × 10 ¹³ / cm ^{2 to} 5 × 10 ¹⁵ / cm 2. ^{2. A} method for manufacturing a semiconductor device, comprising a step of performing ion implantation under the following conditions to perform amorphization. According to the present invention, activation of compound ions can be achieved.

An eighth invention is a semiconductor device comprising the following means.

(A) a silicon substrate, (b) a gate insulating film formed on the silicon substrate, and (c) a compound ion containing boron having a mass number of 50 or more formed on the gate insulating film. A polysilicon gate region implanted as an impurity, (d) a sidewall formed on the silicon substrate in contact with the gate insulating film and the polysilicon gate region, and (e) boron having a mass number of 50 or more. A source region and / or a drain region formed in the silicon substrate by implanting compound ions as impurities.

According to the present invention, a fine semiconductor device having a shallow junction can be provided.

[0031]

Embodiments of the present invention will be described below. The following embodiments are for explaining the present invention, and are not for limiting the scope of the present invention. Therefore, those skilled in the art can select other embodiments without departing from the principle of the present invention.

A first embodiment of the present invention will be described with reference to FIG. First, an N-type well 102 is placed on a silicon substrate 101.
And a P-type well (not shown) is formed by thermal diffusion.
The state after this step is shown in FIG.

Next, a gate insulating film 103 is formed by depositing a 7 nm thermal oxide film. Figure 1 shows the state after this step.
(B).

Next, 250 nm of undoped polysilicon is deposited. Figure 1 shows the state after this step.
It is shown in (c).

Further, by photolithography and dry etching, polysilicon is deposited on each well to a width of 350 nm to form a gate 104. The state after this step is shown in FIG.

Next, boron dichloride is applied to the N-type well 102 by photolithography at 20 KeV and 1 × 1.
It was injected at 0 ¹⁴ / cm ² conditions, to form the N-type extension part 105. Figure 1 shows the state after this step.
(E).

Further, arsenic ions are similarly implanted into the P-type well under the conditions of ²⁰ KeV and 1 × 10 ¹⁴ / cm ² to form a P-type extension portion (not shown).

Thereafter, the side wall 106 is formed by the CVD method and the etch back method. Figure 1 shows the state after this step.
(F).

This is one of the features of the present invention. That is, boron dichloride ions are simultaneously implanted into the N-type well 102 and the gate region 104 by photolithography at 20 KeV and 4 × 10 ¹⁵ ions / cm ² . The state of this step is shown in FIG. As a result, a source region and a drain region 107 are formed.

Thereafter, a heat treatment at 1040 ° C. for 10 seconds is performed by the RTA method to activate these regions.

The ions to be implanted include, for example, the following compound ions.

(A) Boron dichloride ion (mass number 80,
81, 82, 83, 84, 85).

(B) Boron bromide ion (BBr ⁺ )
(Mass number 89, 90, 91, 92).

(C) Boron dibromide ion (BBr ₂ ⁺ )
(Mass number 168, 169, 161, 162, 163).

All of these have a mass number of 50 or more and a small range, so that it is possible to solve the problem of the present invention of forming a shallow bond.

Thereafter, processes such as deposition of an interlayer insulating film, opening of a contact, deposition of an aluminum electrode, and patterning are performed, but these are omitted because they can be performed by a known technique.

FIG. 3 shows an impurity profile of boron in the semiconductor manufactured according to this embodiment. It can be seen that the impurity depth is shallower than the impurity profile obtained by the conventional manufacturing method, and a shallow junction is realized.

Most of the manufacturing method according to the second embodiment described below is the same as that of the first embodiment, but the heat treatment process for ion activation is different. That is, as in the first embodiment, boron dichloride ions are implanted to 1000
When the heat treatment is performed at about 10 ° C. for 10 seconds, the ion activation rate may be reduced due to the influence of chlorine. If this goes on,
The resistance of the portion where the ions are implanted increases.

Therefore, instead of the heat treatment process of the first embodiment, instantaneous heating at 1100 ° C. or more and 1 second or less is performed. In this method, the transistor is not adversely affected by heat because the thermal budget (which is proportional to the total amount of heat added) is not much different from the conventional method. On the other hand, since the treatment is performed at a higher temperature than in the past, the ion activation rate is the same as in the past, and the resistance can be reduced. Note that the heating temperature is desirably 1100 ° C. or more and 1200 ° C. or less in order to prevent the element from being changed due to exposure to a high temperature.

The manufacturing method according to the third embodiment is obtained by adding the following steps to the manufacturing methods according to the first and second embodiments. That is, before or after implanting boron dichloride ion, silicon ion (Si ⁺ )
Alternatively, a step of implanting germanium ions (Ge ⁺ ) to amorphize the gate region, the source region, and the drain region is performed.

The addition of such a pre-amorphization step is also used in actual manufacturing steps. However, the purpose of using these amorphization steps in the past is to prevent the channeling phenomenon.

The injection amount of boron dichloride ion is 1 × 10 ¹⁵
An example of the conditions for performing the amorphization in the case of about 5 × 10 ¹⁵ pieces / cm ² to 5 × 10 ¹⁵ pieces / cm ² is shown below.
One of the following is performed as the amorphization step.

(A) 1 × 10 ¹⁶ / cm ² , 20 KeV
Silicon ions are implanted under the following conditions.

(B) 1 × 10 ¹⁵ / cm ² , 40 KeV
Germanium ions are implanted under the condition of ５０50 KeV.

In an embodiment different from this,
These conditions are selected so as to provide an acceleration energy that is equal to or less than the depth at which boron dichloride is implanted.

[0056]

As described above, according to the present invention, an M having a gate region, a source region, and a drain region is provided.
In a method for manufacturing an OS-type semiconductor, it is possible to form these regions by implanting compound ions containing boron having a mass number of 50 or more, activate the ions by heat treatment, and create a shallow junction. According to the present invention, the amount of boron penetrating through the gate insulating film is extremely reduced as compared with the related art. The present invention can be applied particularly when manufacturing a fine MOS P-type field effect transistor.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of steps of a method for manufacturing a semiconductor device according to the present invention.

FIG. 2 is a cross-sectional view of a part of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to the present invention.

FIG. 3 is an impurity profile of boron according to the semiconductor device manufacturing method of the present invention.

FIG. 4 is an impurity profile of boron according to a conventional method of manufacturing a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Silicon base 102 N-type well 103 Gate insulating film 104 Polysilicon gate region 105 Extension part 106 Side wall 107 Source region and drain region

Claims (8)

[Claims] 1. A method for manufacturing a semiconductor device, comprising the following steps. (A) forming a gate insulating film on a silicon substrate, forming a gate region on the gate insulating film, and forming a sidewall in contact with the gate insulating film and the gate region on the silicon substrate, respectively; A) a mass number of 50 in the gate region and the silicon substrate;
(C) heating the gate region and the silicon substrate to form a source region and / or a drain region in the silicon substrate, and implanting the implanted ions. Activating the. 2. The method according to claim 1, wherein the compound ion containing boron having a mass number of 50 or more is boron dichloride ion. 3. In the step (c), the heating temperature is set to 1
The method according to claim 1, wherein the heating time is 100 ° C. or more and 1200 ° C. or less, and the heating time is 1 second or less. 4. The method according to claim 1, further comprising a step of implanting silicon ions or germanium ions into the gate region and / or the silicon substrate to perform amorphization before or after the step (b). A method for manufacturing a semiconductor device according to claim 1. 5. The depth at which the silicon ions or the germanium ions are ion-implanted into the gate region and / or the silicon substrate is such that the ions containing boron having a mass number of 50 or less are formed in the gate region and / or the silicon substrate. 5. The method according to claim 4, wherein the depth is less than a depth at which ions are implanted into the silicon substrate. 6. Before or after the step (b), a condition that silicon ions are contained in the gate region and / or the silicon substrate in an amount of 5 × 10 ¹⁴ / cm ² or more and 5 × 10 ¹⁶ / cm ² or less. 4. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of performing amorphization by implanting ions. 7. Before or after the step (b), germanium ions are added to the gate region and / or the silicon substrate in an amount of 5 × 10 ¹³ / cm ² or more and 5 × 10 ¹⁵ / cm ² or more.
4. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of performing an amorphous state by ion implantation under a condition of not more than cm ² . 8. A semiconductor device comprising the following means. (A) a silicon substrate; (b) a gate insulating film formed on the silicon substrate; and (c) a compound ion containing boron having a mass number of 50 or more formed on the gate insulating film and implanted as an impurity. (D) a sidewall formed on the silicon substrate in contact with the gate insulating film and the polysilicon gate region, and (e) a compound ion containing boron having a mass number of 50 or more. Source and / or drain regions formed in the silicon substrate by being implanted as impurities.