JPH10145684A - Bias fluctuation suppression circuit in solid-state image pickup element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress fluctuation resulting from an external application pulse in a bias voltage generated by a bias generating circuit built in the solid-state image pickup element without incurring the increased number of external components and terminals of the solid-state image pickup element and a large size. SOLUTION: The bias circuit is provided with a bias generating circuit 21, a source follower 22 provided to a final stage of the bias generating circuit 21, and an emitter follower 23 connecting to the source follower 22 and a shutter pulse applied to a shutter pulse input terminal 35 is clamped at a bias voltage Vbias and the clamped voltage is applied to a base of the solid-state image pickup element. The bias fluctuation suppression circuit 40 uses divider resistors 41, 42 to adjust an amplitude of the shutter pulse and uses a MOS transistor(TR) 44 to invert the pulse and the result is negatively fed back to the bias voltage outputted from the source follower 22 to suppress fluctuation in the bias voltage resulting from the shutter pulse.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a bias fluctuation suppressing circuit in a solid-state imaging device for suppressing a fluctuation caused by an externally applied pulse in a bias generated by a bias generation circuit built in the solid-state imaging device.

[0002]

2. Description of the Related Art A solid state imaging device using a CCD or the like has a built-in bias circuit for generating various biases used in the solid state imaging device.

On the other hand, some systems including a solid-state image sensor have an electronic shutter function. The electronic shutter function is a function in which signal charges accumulated in pixels are swept away to a substrate in the middle of one field period, and exposure (charge accumulation) can be performed for a desired time. In the case of a solid-state imaging device having a vertical overflow drain structure, a shutter pulse is applied to a substrate during an electronic shutter operation to sweep away signal charges to the substrate.

Here, FIG. 6 shows an example of a configuration of a bias circuit for generating a substrate bias, which is built in a solid-state imaging device having a vertical overflow drain structure. The bias circuit includes a bias generation circuit 101 for generating a predetermined bias voltage, a source follower 102 provided at the last stage of the bias generation circuit 101, and an emitter follower 103 connected to the source follower 102.
And In FIG. 6, a broken line frame 100 represents the inside of the solid-state imaging device.

The source follower 102 has a MOS (Metal Oxide Semiconductor) transistor 111, a resistor 112 having one end connected to the source of the MOS transistor 111 and the other end grounded, and the gate of the MOS transistor 111 having a bias. The power supply voltage V _DD is connected to the output terminal of the generation circuit 101 and the drain is applied to the drain.

The emitter follower 103 has an npn transistor 113 whose base is connected to the source of the MOS transistor 111 and whose emitter is connected to a shutter pulse input terminal 115 to which a shutter pulse is applied from outside the solid-state imaging device. Connected
The power supply voltage V _DD is applied to the collector. The emitter follower 103 is provided for reducing a bias fluctuation due to an influence of a current generated on a substrate of the solid-state imaging device and for clamping a shutter pulse to a bias voltage value generated by a bias circuit. Note that the shutter pulse input terminal 115 is connected to the substrate of the solid-state imaging device.

In the bias circuit shown in FIG. 6, a desired bias voltage value V _bias is obtained from between the source follower 102 and the emitter follower 103. When a shutter pulse is applied to the shutter pulse input terminal 115, the shutter pulse is clamped to the bias voltage value V _bias and applied to the substrate of the solid-state imaging device.

[0008]

By the way, in the bias circuit shown in FIG. 6, the MOS transistor 111 forming the source follower 102 shares the P-well which is an overflow barrier forming the pixel portion of the solid-state imaging device. When the shutter pulse is applied, the threshold voltage of the MOS transistor 111 fluctuates due to the so-called back gate effect (a change in the potential on the lower side of the channel produces an effect equivalent to a change in the gate voltage), and the emitter follower changes. NPN transistor 1 constituting 103
There is a problem that the bias voltage value V _bias fluctuates in synchronization with the shutter pulse applied from the outside due to the voltage fluctuation superimposed via the junction capacitance 117 between the base and the emitter 13.

The above back gate effect can be explained by an equivalent circuit indicated by reference numeral 120 in FIG. This equivalent circuit 120 includes a MOS transistor 111
Diode 121 whose anode is connected to the channel of
And a resistor 122 having one end connected to the cathode of the diode 121 and the other end grounded, and one end connected to the diode 121.
And a capacitor 123 having the other end connected to the substrate. Here, when the voltage of the substrate changes, the lower potential of the channel changes via the equivalent circuit 120.

In the above description, an example has been described in which the bias circuit generates the substrate bias, and the pulse externally applied to the solid-state image sensor is a shutter pulse. Similarly, in the case of the externally applied pulse, there is a problem that the externally applied pulse is superimposed (coupled) on the bias and the bias is varied. When a bias such as a substrate bias fluctuates due to an externally applied pulse such as a shutter pulse, the amount of signal accumulated in the sensor of the solid-state image sensor changes, or a forward There is a problem that a large current flows due to bias.

As means for suppressing the above-mentioned fluctuation in bias, as shown in FIG.
Immediately after the above, a method of adding a decoupling capacitor 131 can be considered. However, in order to incorporate the capacitor 131 in the solid-state imaging device, a relatively large area is required, which is very disadvantageous in recent demands for downsizing of the device. For this reason, the decoupling capacitor 131 is added as an external component. In this case, in addition to the problem that the number of external components increases, a new terminal 132 needs to be added.
There is a problem that the number of terminals of the solid-state imaging device increases and the chip area increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object thereof is to provide a solid-state imaging device without increasing the number of external components and terminals and increasing the size of the solid-state imaging device. An object of the present invention is to provide a bias fluctuation suppressing circuit in a solid-state imaging device capable of suppressing a fluctuation caused by an externally applied pulse in a bias generated by a built-in bias generating circuit.

[0013]

According to a first aspect of the present invention, there is provided a bias fluctuation suppressing circuit which is built in a solid-state imaging device having a bias generating circuit for generating a predetermined bias, and which is externally applied to the solid-state imaging device. A bias adjustment circuit is provided that adjusts the bias generated by the bias generation circuit in accordance with the pulse, thereby suppressing the fluctuation of the bias.

According to a third aspect of the present invention, there is provided a bias fluctuation suppressing circuit.
The bias generation circuit is built in the solid-state imaging device having a bias generation circuit for generating a predetermined bias, and the bias generation circuit responds to a variation superimposed on the bias generated by the bias generation circuit due to an externally applied pulse. The apparatus includes a bias adjustment circuit that suppresses a change in bias by adjusting the generated bias.

In the bias fluctuation suppressing circuit according to the first aspect, the bias generated by the bias generating circuit is adjusted by the bias adjusting circuit in accordance with an externally applied pulse applied to the solid-state imaging device from the outside. Fluctuations are suppressed.

In the bias fluctuation suppressing circuit according to the third aspect, the bias adjusting circuit controls the bias generated by the bias generating circuit in accordance with the fluctuation superimposed on the bias generated by the bias generating circuit due to the externally applied pulse. The generated bias is adjusted to suppress the fluctuation of the bias.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

First, with reference to FIG. 3, a configuration of a main part of a CCD solid-state imaging device camera system as an example of a system to which the present invention is applied will be described. This system comprises a solid-state imaging device 1 using a CCD and a vertical synchronizing signal V
D and a synchronization signal generator 11 for generating synchronization signals such as a horizontal synchronization signal HD, and a vertical synchronization signal VD and a horizontal synchronization signal HD output from the synchronization signal generator 11 are input to drive the solid-state imaging device 1 Generator 12 for generating various timing signals for use in the solid-state imaging device 1 for inputting a timing signal output from the timing generator 12 and for sweeping out a vertical transfer clock, a horizontal transfer clock, and signal charges. Driver 1 that drives a solid-state imaging device 1 by giving a shutter pulse or the like applied to a substrate of
3 is provided. Note that the timing generator 12 directly supplies a timing pulse such as a reset gate pulse to the solid-state imaging device 1 as necessary. In FIG. 3, a signal processing system for an output signal of the solid-state imaging device 1 is omitted.

FIG. 4 is an explanatory diagram showing an example of the configuration of the solid-state imaging device 1 in FIG. The solid-state imaging device 1 in this example includes a plurality of light receiving units 2 arranged in a matrix, a plurality of vertical shift registers 3 connected to the light receiving units 2 for one column via a readout gate 6, respectively. A horizontal shift register 4 is connected to a lower end of the vertical shift register 3 and an output unit 5 is connected to one end of the horizontal shift register 4.

Although not shown, the solid-state imaging device 1 has a vertical overflow drain structure. For example, an overflow barrier composed of a P well is formed on an N-type semiconductor substrate, and a light receiving section 2 is formed on the overflow barrier. a charge storage section comprised of N ⁺ layer constituting a transfer channel comprising a N ⁺ layer constituting the vertical shift register 3 is formed. A read gate 6 is formed between the charge storage section and the transfer channel. A channel stop composed of a P ⁺ layer is formed between adjacent pixels. Further, a virtual gate made of a P ⁺ layer is formed on the charge storage portion. In this solid-state imaging device 1,
By applying a shutter pulse to the substrate, the signal charges stored in the charge storage portion are swept away by the substrate, and an electronic shutter function is realized.

FIG. 1 is a circuit diagram showing a configuration of a bias circuit including a bias fluctuation suppressing circuit according to a first embodiment of the present invention. Here, an example of a bias circuit for generating a substrate bias of the solid-state imaging device 1 is described.
The bias circuit includes a bias generation circuit 21 for generating a predetermined bias voltage, a source follower 22 provided at the last stage of the bias generation circuit 21, and an emitter follower 23 connected to the source follower 22. I have. In FIG. 6, a broken-line frame 20 indicates the inside of the solid-state imaging device 1.

The source follower 22 has a MOS transistor 31 and a resistor 32 having one end connected to the source of the MOS transistor 31 and the other end grounded. The gate of the MOS transistor 31 is connected to the output terminal of the bias generation circuit 21. , And the power supply voltage V _DD is applied to the drain.

The emitter follower 33 has an npn transistor 33. The base of the npn transistor 33 is connected to the source of the MOS transistor 31, and the emitter is a shutter pulse input terminal to which a shutter pulse is applied from outside the solid-state imaging device 1. The power supply voltage V _DD is applied to the collector. The emitter follower 23 is provided to reduce the fluctuation of the bias due to the influence of the current generated on the substrate of the solid-state imaging device 1 and to clamp the shutter pulse to the bias voltage value generated by the bias circuit. . Note that the shutter pulse input terminal 35 is connected to the substrate of the solid-state imaging device 1.

As for the bias generation circuit 21,
There are various circuit configurations such as a circuit having a MOS transistor and a resistance division circuit using polycrystalline silicon.

The solid-state imaging device 1 has a built-in bias fluctuation suppressing circuit 40 according to the present embodiment. The bias fluctuation suppressing circuit 40 includes a resistor 41 having one end connected to the shutter pulse input terminal 35, a resistor 42 having one end connected to the other end of the resistor 41, and the other end grounded, and gates of the resistors 41 and 42. A MOS transistor 43 connected to the connection point, the source of which is grounded via a ground or a resistor, and a resistor connected at one end to the drain of the MOS transistor 43 and the other end connected between the source follower 22 and the emitter follower 23 44. The resistors 41 and 4
2 and the gate of the MOS transistor 43,
A capacitor 45 for removing a DC component may be provided.

Next, the operation of the bias circuit shown in FIG. 1 and the bias fluctuation suppressing circuit 40 according to the present embodiment will be described. In the bias circuit shown in FIG. 1, a desired bias voltage value V _bias is obtained from between the source follower 22 and the emitter follower 23. When a shutter pulse is applied to the shutter pulse input terminal 35, the shutter pulse is clamped to the bias voltage value V _bias and applied to the substrate of the solid-state imaging device 1.

Here, M constituting the source follower 22
Assuming that the OS transistor 31 shares a P-well serving as an overflow barrier constituting the pixel portion of the solid-state imaging device 1, if the bias fluctuation suppressing circuit 40 according to the present embodiment is not provided, the OS transistor 31 shown in FIG. When a shutter pulse is applied as shown in FIG.
The back gate effect on the OS transistor 31 and the npn transistor 3 forming the emitter follower 103
3, the bias voltage value V _bias fluctuates in synchronization with the shutter pulse due to the voltage fluctuation superimposed via the junction capacitance between the base and the emitter. In addition, FIG.
5 shows a change in voltage at a connection point A between the source of the S transistor 31 and the resistor 32.

In the bias fluctuation suppressing circuit 40 according to the present embodiment, the amplitude of the shutter pulse applied to the shutter pulse input terminal 35 is reduced at a predetermined ratio by the divided resistors including the resistors 41 and 42, and the MOS transistor The direct-current component is removed directly from the gate of 44 or by a capacitor 45 and input. At this time, MOS
At the point B on the drain side of the transistor 44, FIG.
As shown in (c), an output having a phase opposite to that of the input shutter pulse is generated. Therefore, a pulse having an opposite phase to the output fluctuation due to the shutter pulse is applied to the output of the source follower 22. Since both the fluctuation of the output of the source follower 22 due to the shutter pulse and the output of the opposite phase by the bias fluctuation suppressing circuit 40 are simultaneously generated based on the same input pulse (shutter pulse), as a result, the source follower due to the shutter pulse is generated. The fluctuation of the output of the output 22 is suppressed by the output of the opposite phase by the bias fluctuation suppressing circuit 40, and is completely removed. Accordingly, the bias voltage value V _bias is _calculated as shown in FIG.
As shown in (1), the fluctuation due to the shutter pulse is suppressed and further completely removed.

The bias fluctuation suppressing circuit 40 according to the present embodiment has effects on both the back gate effect on the MOS transistor 31 and the voltage fluctuation superimposed via the junction capacitance between the base and the emitter of the npn transistor 33. There is. MO constituting the bias fluctuation suppressing circuit 40
The threshold value of the S transistor 43 and the resistances 41, 42, 4
The resistance value of No. 4 is set to an optimum value according to the magnitude of the fluctuation of the bias.

As described above, according to the bias fluctuation suppressing circuit 40 according to the present embodiment, the amplitude of the shutter pulse applied from the outside is adjusted and inverted, and the source follower 2 is controlled.
2 is negatively fed back to the bias output from 2 to adjust the bias according to the shutter pulse.
Variations in bias due to shutter pulses can be suppressed.

Further, according to the bias fluctuation suppressing circuit 40 according to the present embodiment, since the decoupling capacitor as shown in FIG. 6 is not required, the number of external parts and the number of terminals of the solid-state imaging device 1 are reduced. Bias fluctuations can be suppressed without increasing the size or increasing the size of the solid-state imaging device 1 (increase in chip area).

Further, since the bias fluctuation suppressing circuit 40 built in the solid-state imaging device 1 can be formed by using an existing manufacturing process, it is necessary to take a special structure for suppressing the bias fluctuation. However, it can be formed by a manufacturing process substantially similar to the conventional one, and does not significantly increase the number of steps.

FIG. 5 is a circuit diagram showing a configuration of a bias circuit including a bias fluctuation suppressing circuit according to a second embodiment of the present invention. In the present embodiment, instead of the bias fluctuation suppressing circuit 40 according to the first embodiment, the output of the circuit is set between the source follower 22 and the emitter follower 23 with respect to the bias fluctuation caused by the shutter pulse. Push-pull bias fluctuation suppressing circuit 50 that changes in the opposite direction
Is provided. The bias fluctuation suppressing circuit 50 includes an n-channel MOS transistor 51 and a p-channel MO transistor.
MOS transistor 5 having an S transistor 52
The gates of 1, 52 are M
The source of the MOS transistor 51 is connected to the source of the OS transistor 31, and the sources of the MOS transistors 51 and 52 are connected to the emitter follower 23.
Are connected to the base of an npn transistor 33 constituting The power supply voltage V _DD is applied to the drain of the MOS transistor 51, and the drain of the MOS transistor 52 is grounded.

In the bias circuit shown in FIG. 5, a desired bias voltage value V _bias is obtained from between the bias fluctuation suppressing circuit 50 and the emitter follower 23. In the bias fluctuation suppressing circuit 50 according to the present embodiment, np
Due to the junction capacitance between the base and the emitter of the n-transistor 33, the emitter follower 2
3, the current flowing through the n-channel MOS transistor 51 decreases, and the p-channel
The current flowing through the S transistor 52 increases, and the bias is adjusted. As a result, the fluctuation of the bias is suppressed.

The following three types of configurations are conceivable in the bias fluctuation suppressing circuit 50 from the viewpoint of current consumption. The MOS transistors 51 and 52 are both of the depletion type, and a current is steadily supplied to the bias fluctuation suppressing circuit 50 to perform class A operation. The sources of MOS transistors 51 and 52 are connected to ground resistance 5
3 is grounded, and a small current is passed through the grounding resistor 53 so that the output (source) voltage is always constant, thereby performing the class B operation. In this case, the MOS transistors 51 and 52 may be of the depletion type or of the enhancement type. The sources of MOS transistors 51 and 52 are connected to ground resistance 5
3, the MOS transistor 51 is of an enhancement type, and the MOS transistor 52 is also adjusted in threshold value toward the enhancement type, so that the MOS transistor 52 is normally in the off state, but the bias voltage V _bias is increased by the shutter pulse. It is turned on when it fluctuates, and the class C operation is performed.

Other structures, operations and effects of the present embodiment are the same as those of the first embodiment.

The present invention is not limited to the above embodiments. For example, in each of the above embodiments, the bias circuit generates the substrate bias, and the pulse applied from the outside to the solid-state imaging device 1 Although the example in which the shutter pulse is used has been described, the present invention can be similarly applied to a circuit for generating another bias and another externally applied pulse.

[0038]

As described above, according to the bias fluctuation suppressing circuit in the solid-state imaging device according to any one of the first to fourth aspects, the bias adjustment circuit built in the solid-state imaging device externally connects the solid-state imaging device. The bias generated by the bias generation circuit is adjusted in accordance with an externally applied pulse applied from the external device or in accordance with a variation superimposed on the bias generated by the bias generation circuit due to the externally applied pulse. Then, since the fluctuation of the bias is suppressed, the number of external parts and the number of terminals of the solid-state imaging device are increased, and without increasing the size of the solid-state imaging device, a bias generation circuit built in the solid-state imaging device is used. There is an effect that fluctuation in the generated bias due to an externally applied pulse can be suppressed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a bias circuit including a bias fluctuation suppressing circuit according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram for explaining an operation of the bias fluctuation suppressing circuit in FIG. 1;

FIG. 3 shows C as an example of a system to which the present invention is applied;
It is a block diagram showing composition of an important section of a CD solid-state image sensor camera system.

FIG. 4 is an explanatory diagram illustrating an example of a configuration of a solid-state imaging device in FIG. 3;

FIG. 5 is a circuit diagram showing a configuration of a bias circuit including a bias fluctuation suppressing circuit according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing an example of a configuration of a bias circuit built in the solid-state imaging device.

[Description of Signs] 1 ... Solid-state imaging device, 21 ... Bias generating circuit, 22 ... Source follower, 23 ... Emitter follower, 31 ... MOS
Transistor, 32 resistor, 33 npn transistor, 35 shutter pulse input terminal, 40 bias fluctuation suppressing circuit, 41, 42, 44 resistor, 43 MOS transistor

Claims (4)

[Claims] 1. A solid-state imaging device having a bias generation circuit for generating a predetermined bias, wherein the bias generated by the bias generation circuit is changed according to an externally applied pulse applied to the solid-state imaging device from outside. A bias fluctuation suppressing circuit in a solid-state imaging device, comprising: a bias adjusting circuit that suppresses the bias fluctuation by adjusting the bias. 2. The solid-state imaging device according to claim 1, wherein the bias adjustment circuit is a circuit that negatively feedbacks an externally applied pulse with respect to a bias generated by the bias generation circuit. circuit. 3. A variation built in a solid-state imaging device having a bias generation circuit for generating a predetermined bias, the variation being superimposed on the bias generated by the bias generation circuit due to the externally applied pulse. A bias fluctuation suppressing circuit in a solid-state imaging device, comprising: a bias adjusting circuit that suppresses the fluctuation of the bias by adjusting a bias generated by the bias generating circuit. 4. The bias adjustment circuit according to claim 1, wherein said bias adjustment circuit is a push-pull circuit provided at a stage subsequent to said bias generation circuit, wherein an output of said circuit changes in a direction opposite to said variation. 4. A bias fluctuation suppressing circuit in the solid-state imaging device according to 3.