JP2007081943A - Solid-state imaging module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging module with a novel configuration. <P>SOLUTION: The solid-state imaging module includes: a substrate voltage control means for a solid-state imaging element including an operational amplifier; and a pulse generating circuit for generating a voltage pulse, an output stage of the operational amplifier includes PMOS transistors, a diode, and NMOS transistors, the anode of the diode is connected to the drain of the PMOS transistor, and the cathode of the diode is connected to the drain of the NMOS transistor, the PMOS transistors, the diode, the NMOS transistors are formed on one and same semiconductor substrate, and the pulse generating circuit applies a voltage pulse to the cathode of the diode. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a solid-state imaging module, and more particularly to a solid-state imaging module for resetting a photoelectric conversion element included in a charge coupled device solid-state imaging element by an electronic shutter.

  A charge coupled device (CCD) area sensor is used as a solid-state imaging device. The CCD area sensor is manufactured, for example, by forming a p-type well region (p-well) on an n-type semiconductor substrate and forming a photoelectric conversion element (photodiode) or a charge transfer path in the p-well. The photoelectric conversion element accumulates an amount of charge corresponding to the amount of incident light.

  The amount of charge accumulated in the photoelectric conversion element is controlled by an overflow drain (OFD) voltage applied to the substrate. The stored charge amount increases as the OFD voltage decreases, and the stored charge amount decreases as the OFD voltage increases. The OFD voltage is set to about 10V, for example.

  By making the potential of the substrate extremely high (for example, by setting it to 30 to 40 V), it is possible to discharge all charges accumulated in the photoelectric conversion element to the substrate (electronic shutter). At the start of exposure, the photoelectric conversion element is reset by the electronic shutter. During the electronic shutter operation, a high voltage obtained by superimposing a voltage pulse on the OFD voltage (referred to as a shutter voltage) is applied to the substrate. The amplitude of the superimposed voltage pulse is set to about 20V, for example.

  FIG. 12 shows an example of a circuit of a solid-state imaging module that applies an OFD voltage and a shutter voltage to the CCD area sensor. The circuit shown in FIG. 12 includes a resistance bleeder B for generating a direct current (DC) bias, a diode D1, a capacitor C1 for alternating current (AC) coupling, and a clock driver circuit CD. A diode D1 is inserted between the resistance bleeder B and the substrate NSUB so that an anode is disposed on the resistance bleeder B side and a cathode is disposed on the substrate NSUB side.

  During the exposure, the output voltage of the clock driver CD is at a low level, and the OFD voltage determined by the resistors R1 and R2 of the resistor bleeder B is applied to the substrate NSUB.

  After the charge is read from the photoelectric conversion element, immediately before the next exposure is started, the output voltage of the clock driver CD becomes a high level. Due to capacitive coupling, the output voltage of the clock driver CD is superimposed on the OFD voltage to generate a shutter voltage.

  During the electronic shutter operation, a reverse bias voltage is applied to the diode D1, the diode D1 is turned off, and the resistance bleeder B and the substrate NSUB are electrically separated.

  The level of the OFD voltage applied to the substrate NSUB from the resistance bleeder determines the saturation output charge amount of the photoelectric conversion element. Since the relationship between the OFD voltage level and the amount of saturated output charge changes due to variations in the manufacturing process, a resistance bleeder and a fuse are built in the same chip as the area sensor in the manufacture of a CCD area sensor. In many cases, adjustment is performed so as to obtain a unique OFD voltage.

  When the circuit described with reference to FIG. 12 is used, it is necessary to set the DC voltage in consideration of the voltage drop (Vf) of the diode D1. However, the voltage drop of the diode D1 varies from individual to individual, and also varies depending on the temperature. Due to this, it is difficult to improve the accuracy of the OFD voltage level. Increasing the bleeder resistance system does not necessarily increase the accuracy of the output voltage.

JP 2002-262186 A

  During the electronic shutter operation, a high voltage reaching 30-40V is used. In some cases, the solid-state imaging module may be configured using MOS transistors.

  An object of the present invention is to provide a solid-state imaging module that can be manufactured without using a MOS transistor with a particularly high breakdown voltage.

  Another object of the present invention is to provide a solid-state imaging module having a novel configuration.

  According to a first aspect of the present invention, there is provided a substrate voltage control means for a solid-state imaging device including an operational amplifier, and a pulse generation circuit for generating a voltage pulse, and the output stage of the operational amplifier includes a PMOS transistor, A diode and an NMOS transistor, the drain of the PMOS transistor and the anode of the diode are connected, the cathode of the diode and the drain of the NMOS transistor are connected, and the PMOS transistor, diode, and NMOS transistor are The solid-state imaging module is formed on the same semiconductor substrate, and the pulse generation circuit applies a voltage pulse to the cathode of the diode.

  According to the second aspect of the present invention, in the solid-state imaging device according to the first aspect, further, in synchronization with the timing at which a voltage pulse is applied to the drain of the NMOS transistor connected to the cathode of the diode, A solid-state imaging module is provided having a control circuit that raises the voltage applied to the gate of the NMOS transistor.

  In the solid-state imaging module according to the first aspect, the shutter voltage is obtained by superimposing the voltage pulse on the output supplied by the cathode of the diode. The diode suppresses the forward bias current caused by the shutter voltage from flowing through the PMOS transistor. By forming the PMOS transistor, the diode, and the NMOS transistor on the same semiconductor substrate, the number of components can be reduced as compared with, for example, an external diode.

  In the solid-state imaging module according to the second aspect, the control circuit increases the voltage applied to the gate of the NMOS transistor, thereby suppressing the gate-drain voltage difference in the NMOS transistor from exceeding the breakdown voltage.

  Prior to the description of the solid-state imaging module according to the embodiment of the present invention, the solid-state imaging module proposed above will be described. FIG. 8 is a block diagram showing a solid-state imaging device including the solid-state imaging module 1 according to the previous proposal and a solid-state imaging device (charge coupled device (CCD) area sensor) 2 driven by the solid-state imaging module 1. It is.

  The solid-state imaging module 1 includes an overflow drain (OFD) control circuit 31 and a pulse generation circuit 32. The OFD control circuit 31 and the pulse generation circuit 32 are formed on the same semiconductor substrate.

  An analog output voltage OFDI is input from the CCD area sensor 2 to the OFD control circuit 31. The OFD control circuit 31 generates an OFD voltage OFDO based on OFDI, and OFDO is applied to the CCD area sensor 2. OFDO is, for example, about 10V.

  The pulse generation circuit 32 outputs a voltage pulse SUBO. The amplitude of the voltage pulse SUBO is 20V or more. A capacitor 11 is inserted between the output of the pulse generation circuit 32 and the output of the OFD control circuit 31, and the voltage pulse SUBO is superimposed on OFDO by capacitive coupling. The shutter voltage is generated by superimposing the voltage pulse SUBO on OFDO. The shutter voltage is, for example, 30 to 40V.

  A high power supply voltage (this is referred to as VH) and a low power supply voltage (this is referred to as VL) are supplied to the pulse generation circuit 32. The high power supply voltage VH is, for example, 18V, and the low power supply voltage VL is, for example, -10V. By amplifying the voltage between VL and VH, a voltage pulse SUBO is generated.

  A control clock is input to the OFD control circuit 31 and the pulse generation circuit 32 to control the operation timing of the OFD control circuit 31 and the pulse generation circuit 32.

  Next, the configuration of the OFD control circuit 31 will be described with reference to FIG. The OFD control circuit 31 includes a voltage amplification type amplification circuit 3 and a switch circuit 4. The amplifier circuit 3 is configured using complementary metal oxide semiconductor (CMOS) transistors. The non-inverting input voltage of the amplifier circuit 3 is OFDI, and the output voltage is OFDX. The output voltage OFDX is negatively fed back as an inverted input voltage, so that OFDX is controlled to be equal to the input voltage OFDI.

  The output stage of the amplifier circuit 3 is generally composed of an inverter circuit, for example. If the output OFDX of the inverter circuit is directly used as the output OFDO for the area sensor, the following problems may occur.

  Considering the PMOS transistor in the inverter circuit, it is assumed that the drain of the PMOS transistor is formed in an n-type well region (n-well), and the n-well is connected to the high power supply voltage VH. An output is supplied from the drain of the PMOS transistor.

  During the electronic shutter operation, a shutter voltage higher than the high power supply voltage VH is applied to the drain of the PMOS transistor. For this reason, a forward current flows from the drain of the PMOS transistor to the n-well. This forward current causes a reduction in shutter voltage.

  Therefore, a switch circuit 4 is provided to electrically cut off the amplifier circuit 3 and the output terminal OFDO during the electronic shutter operation. As the switch circuit, a diode or a circuit constituted by a CMOS is generally used. In the OFD control circuit 31 proposed above, the switch circuit 4 is configured by CMOS.

  OFDX is input to the switch circuit 4. The output voltage of the switch circuit 4 is OFDO. During the electronic shutter operation, a voltage pulse is superimposed on the OFD voltage OFDO.

  Next, the configuration of the switch circuit 4 will be described with reference to FIG. As will be described below, the switch circuit 4 is turned on when the switch signal OE is at a high level, and the switch circuit 4 is turned off when the switch signal OE is at a low level.

  Since the switch circuit 4 handles a high voltage of about 10 V to 30 V (or 40 V), the level shift circuit 5 is used to set the control signal to a high voltage. The input of the level shift circuit 5 is a switch signal OE, and the output is a switch signal OEH. The high level of the switch signal OE is, for example, 2.5 to 5V. When the high level switch signal OE is inputted, the level shift circuit 5 converts it into a high power supply voltage VH and outputs it. When the low level switch signal OE is input, the level shift circuit 5 outputs the ground potential.

  The PMOS transistor M3 and the NMOS transistor M4 constitute an inverter circuit. The source of the NMOS transistor M4 is grounded, and the source of the PMOS transistor M3 is connected to OFDO. The input of this inverter circuit is the switch signal OEH, and the complementary output is the switch signal OEHB.

  The drain of the PMOS transistor M1 and the source of the NMOS transistor M2 are connected, and the source of the PMOS transistor M1 and the drain of the NMOS transistor M2 are connected to constitute an analog switch. The source and bulk of the PMOS transistor M1 are connected to OFDO, and the bulk of the NMOS transistor M2 is grounded.

  The switch signal OEHB is applied to the gate of the PMOS transistor M1, and the switch signal OEH is applied to the gate of the NMOS transistor M2. The output voltage OFDX from the amplifier circuit 3 is applied to the drain of the PMOS transistor M1 and the source of the NMOS transistor M2. The source of the PMOS transistor M1, the drain of the NMOS transistor M2, and the source of the PMOS transistor M3 are connected, and this connection point supplies the output voltage OFDO.

  When the switch signal OE is at a high level, the switch signal OEH is equal to the high power supply voltage VH, the transistor M3 is turned off, the transistor M4 is turned on, and the switch signal OEHB is at the ground potential.

  At this time, if the potentials of OFDX and OFDO are at a level close to the ground potential, for the transistor M1, the gate-source voltage VGS1 decreases and the on-resistance increases. On the other hand, for the transistor M2, the gate-source voltage VGS2 increases and the on-resistance decreases. Therefore, at this potential level, the transistor M2 has a lower impedance than the transistor M1, and the transistor M2 is dominant in the switching operation. Thereby, OFDO is set to the same potential as OFDX.

  If the potential of OFDX rises, the potential of output OFDO also rises, VGS2 becomes smaller, and the threshold value of transistor M2 rises due to the back bias effect peculiar to the MOS transistor, and the on-resistance increases. Become. On the other hand, in the transistor M1, VGS1 increases and the on-resistance decreases. For this reason, the transistor M1 becomes dominant in the switch operation. Thereby, OFDO is set to the same potential as OFDX.

  When the OFD voltage is about 10 V, the transistor M1 has a lower impedance than the transistor M2, and the transistor M1 becomes dominant in the switching operation, so that OFDO is controlled to a potential equal to OFDX.

  When the switch signal OE is at a low level, the switch signal OEH is at the ground potential, and the NMOS transistor M4 is turned off. As for the transistor M3, if the potential of OFDO is higher than the threshold value VTP of the PMOS transistor, the gate-source voltage VGS3 is larger than the threshold value, so that the transistor M3 is turned on, and OEHB is equal to OFDO. The transistor M2 is turned off because VGS2 is 0V or less, and the transistor M1 is turned off because VGS1 is 0V.

  Even if the potential of OFDO is equal to or lower than VTP, the potential of OEHB is an intermediate potential between the ground potential and the OFDO potential. Therefore, VGS1 does not become higher than VTP and transistor M1 is turned off. In this state, if the inputs OFDX and OFDO are substantially equal, or if OFDO is higher than OFDX, both signals are electrically disconnected.

  However, if the potential of OFDO swings in a direction lower than OFDX, a forward current flows from OFDX to OFDO in transistor M1 when the forward threshold value of the parasitic diode between the drain and the bulk constituting the PMOS transistor is exceeded. In the beginning, a state in which a drop below a certain voltage is suppressed occurs. However, in actual use of the CCD, this is not a problem because the switch is turned off with the potential of OFDO being higher than that of OFDX.

  During the electronic shutter operation, the switch circuit 4 is turned off, and the potential of the SUBO is displaced from VL to VH, so the OFDO swings to a high potential exceeding the VH (here, the voltage on which the SUBO is superimposed is also called OFDO) ). At this time, since the transistor M3 is on, OEHB also rises to the same potential as OFDO. For this reason, VGS1 is kept at 0V and the transistor M1 is not turned on. The transistor M2 is also kept off. Therefore, OFDX can be kept at the potential before switching off, and the shutter voltage can be boosted to a specified value.

  The bulk of the NMOS transistor M2 can also be connected to OFDX. In this case, the source becomes OFDX and the drain becomes OFDO, the back bias effect is eliminated, and the threshold value is kept constant. Further, as in the case of the transistor M1, when OFDO falls below the potential of OFDX, a forward current from OFDX to OFDO flows. Note that whether or not the bulk potential can be arbitrarily determined also depends on the process configuration.

  The outputs of the MOS transistors M1 to M4 and the level shift circuit 5 are made possible by high voltage MOS transistors that can use a high power supply voltage. The high breakdown voltage MOS transistor used for the switch circuit 4 can be formed by the same process as the high breakdown voltage MOS used in the pulse generation circuit 32 originally using the high power supply voltage. The previously proposed switch circuit 4 can be formed on the same semiconductor substrate as the pulse generation circuit 32.

  The OFD control circuit of the solid-state imaging module according to the above-described proposal described above depends on the conductivity type of the semiconductor substrate and the breakdown voltage of the MOS transistor. This will be specifically described below with reference to FIGS. 11A and 11B.

  11A and 11B show portions of the MOS transistors M1 and M2 in the switch circuit 4 shown in FIG. The MOS transistor M1 is a PMOS transistor, and the MOS transistor M2 is an NMOS transistor.

  First, the case where MOS transistors M1 and M2 are formed on a p-type substrate will be described with reference to FIG. In the solid-state imaging module proposed above, a p-type substrate is used as a substrate, and MOS transistors M1 and M2 are formed on the p-type substrate.

  The PMOS transistor M1 is manufactured by forming a well (n-well) which is an n-type region on a p-type substrate, and forming a source and a drain which are p-type regions in the n-well. The NMOS transistor M2 is manufactured by forming a source and a drain which are n-type regions on a p-type substrate. The source of the PMOS transistor M1 and the n-well are connected, and the p-type substrate is grounded.

During the electronic shutter operation, the source of the PMOS transistor M1 becomes the shutter voltage. Here, it is assumed that the shutter voltage is 38V. The source of the PMOS transistor M1 and the n-well are connected and are equipotential. This prevents a forward bias voltage from being applied between the source of the PMOS transistor M1 and the n-well during the electronic shutter operation.
Since the PMOS transistor on the p-type substrate is isolated from other PMOS transistors by the n well, the source and the n well can be connected.

  Next, a case where MOS transistors M1 and M2 are formed on an n-type substrate will be described with reference to FIG. The PMOS transistor M1 is manufactured by forming a source and a drain which are p-type regions on an n-type substrate. The NMOS transistor M2 is manufactured by forming a well (p well) which is a p-type region in an n-type substrate, and forming a source and a drain which are n-type regions in the p well. The p-well of the NMOS transistor M2 is grounded, and a high power supply voltage VH (for example, 15V) is applied to the n-type substrate.

  During the electronic shutter operation, the source of the PMOS transistor M1 becomes the shutter voltage. Since the shutter voltage is higher than the high power supply voltage VH, a forward bias voltage is applied between the source of the PMOS transistor M1 and the n-type substrate during the electronic shutter operation. Since the PMOS transistor on the n-type substrate does not have a well and shares the back gate (substrate in this case) with other PMOS transistors, it cannot be isolated.

  In both cases where the NMOS transistor M2 is formed on the p-type substrate and in the p-well of the n-type substrate, the drain of the NMOS transistor M2 becomes the shutter voltage during the electronic shutter operation. A voltage of 38V is applied between the drain of M2 and the back gate.

  As described above, when the PMOS transistor M1 is formed on the n-type substrate, a forward bias voltage is easily applied to the PMOS transistor M1 during the electronic shutter operation. If the shutter voltage is 38V, for example, the breakdown voltage of the NMOS transistor M2 is required to be 38V or higher. There is no problem if the breakdown voltage of the NMOS transistor M2 is 40V, for example, but if the breakdown voltage is 30V, the element may be destroyed.

  A solid-state imaging module that is easy to manufacture even when using an n-type substrate is desired. Further, a solid-state imaging module that is easy to manufacture even if the MOS transistor has a low breakdown voltage (for example, 30 V or less) is desired.

  Next, a solid-state imaging module according to an embodiment of the present invention will be described. The solid-state imaging module according to the embodiment differs from the previously proposed solid-state imaging module in the configuration of the OFD control circuit.

  FIG. 1 is a block diagram illustrating a solid-state imaging device including a solid-state imaging module 101 according to an embodiment and a solid-state imaging device (CCD area sensor) 102 driven by the solid-state imaging module 101.

  The solid-state imaging module 101 includes an OFD control circuit 131 and a pulse generation circuit 132. The OFD control circuit 131 and the pulse generation circuit 132 can be formed on the same semiconductor substrate. As a substrate on which the OFD control circuit 131 and the pulse generation circuit 132 are formed, for example, an n-type substrate is used.

  The OFD control circuit 131 includes an OFD amplifier circuit 131a and a diode 131b. The diode 131b is formed on the same semiconductor substrate as the OFD amplifier circuit 131a.

  The OFD amplifier circuit 131a is a current output type operational amplifier. An analog output signal OFDI from the CCD area sensor 102 is input to the OFD amplifier circuit 131a, and a voltage OFDX is output from the OFD amplifier circuit 131a. The output of the OFD amplifier circuit 131a is connected to the anode of the diode 131b, and OFDO is output from the cathode of the diode 131b. By feeding OFDO back to the OFD amplifier circuit 131a, OFDO is controlled to a voltage equal to OFDI. OFDO is about 10-12V (for example, 10V).

  As the output OFDX of the OFD amplifier circuit 131a, a voltage higher than OFDO is output by the threshold voltage of the diode 131b. When the threshold voltage of the diode 131b is 0.7V, for example, the value obtained by adding 0.7V to OFDO is OFDX.

  The pulse generation circuit 132 outputs a voltage pulse SUBO. The amplitude of the voltage pulse SUBO is 20V or more. A capacitor 111 is inserted between the output of the pulse generation circuit 132 and the output of the OFD control circuit 31, and the voltage pulse SUBO is superimposed on OFDO by capacitive coupling. The shutter voltage is generated by superimposing the voltage pulse SUBO on OFDO. The shutter voltage is, for example, 30 to 40V.

  A high power supply voltage VH and a low power supply voltage VL are supplied to the pulse generation circuit 132. The high power supply voltage VH is, for example, 18V, and the low power supply voltage VL is, for example, -10V. By amplifying the voltage between VL and VH, a voltage pulse SUBO is generated. During the electronic shutter operation, the diode 131b electrically shuts off the OFDO and OFDX except for the feedback path.

  Next, the OFD amplifier circuit 131a will be further described with reference to FIG. The OFD amplifier circuit 131a includes a plurality of MOS transistors M101 to M111.

  An input stage amplifier is configured including the MOS transistors M103 to M107. A differential pair is configured including NMOS transistors M103 and M104. The gate of the NMOS transistor M104 corresponds to the positive input of the operational amplifier, and the gate of the NMOS transistor M103 corresponds to the negative input. The NMOS transistor M107 functions as a current source that supplies current to the differential pair. The sources of the NMOS transistors M103 and M104 and the drain of the NMOS transistor M107 are connected to each other.

  An output stage amplifier is configured including PMOS transistors M109 and M111 connected in series, a diode 131b, and NMOS transistors M101 and M102 connected in series. The drain of the PMOS transistor M111 and the drain of the NMOS transistor M111 are connected via a diode 131b. The anode of the diode 131b is connected to the drain of the PMOS transistor M111, and the cathode of the diode 131b is connected to the drain of the NMOS transistor M111.

  The output of the drain of the PMOS transistor M111 is OFDX, and the output of the diode 131b is OFDO. OFDO is input to the drain of the NMOS transistor M101 and the gate of the NMOS transistor M103. OFDI is input to the gate of the NMOS transistor M104.

  The output OFDO of the diode 131b is input to the gate of the NMOS transistor M103, and feedback is applied. For this reason, even if the temperature and the power supply potential fluctuate, the output OFDO of the diode 131b is controlled to be equal to the positive input (reference voltage) OFDI of the OFD amplifier circuit 131a.

  A diode 131b is arranged in the feedback path, and the output OFDO is controlled in consideration of the influence of the voltage drop of the diode 131b. For this reason, the OFD voltage can be controlled with high accuracy.

  The switch circuit SW1 switches the voltage applied to the gates of the NMOS transistors 101 and M107. For example, the control device C configured using a central processing unit (CPU) controls the switch circuit SW1. The control device C also controls the pulse generation circuit 132. The power supply voltage generation circuit P generates a high power supply voltage VH and a low power supply voltage VL based on a normal power supply voltage (for example, 3 V) and a ground potential.

  It is assumed that the breakdown voltage of each MOS transistor is 30V, the threshold voltage Vth is 2.5V, and the saturation voltage is 0.5V. The shutter voltage is 38V. During the electronic shutter operation, a shutter voltage is applied to the drain of the NMOS transistor M101 and the gate of the NMOS transistor M103. The shutter voltage 38V is higher than the withstand voltage 30V of the NMOS transistors M101 and M103.

  During the electronic shutter operation, the diode 131b electrically separates the anode side and the cathode side, so that it is possible to prevent a forward bias current from flowing through the PMOS transistor M111 from the shutter voltage.

  Next, a method for preventing a voltage higher than the withstand voltage from being applied to the MOS transistor M101 will be described with reference to FIG. The state other than during the electronic shutter operation is referred to as normal operation.

  Since the threshold voltage Vth of the MOS transistors M101 and M102 is 2.5V and the saturation voltage is 0.5V, for example, the gate-source voltage difference between the MOS transistors M101 and M102 is 3.0V during normal operation, and the drain Each source voltage difference is 0.5V. That is, during normal operation, for example, the gate voltage of the MOS transistor M102 is 3.0V, the drain voltage of the MOS transistor M102 is 0.5V, the gate voltage of the MOS transistor M101 is 3.5V, and the drain voltage of the MOS transistor M101 is 1.0V.

  As shown in FIG. 3A, a shutter voltage is applied to the drain of the MOS transistor M101 during the electronic shutter operation. Simultaneously with the timing at which the shutter voltage is applied (or slightly before that timing), the gate voltage of the MOS transistor M101 is raised to the high power supply voltage VH (18V). The control device C synchronizes the increase in the gate voltage with the application of the shutter voltage.

  Even if the gate voltage of the MOS transistor M101 is increased, a current equal to that before the electronic shutter operation flows through the MOS transistor M101. Therefore, the gate-source voltage difference of the MOS transistor M101 is maintained at 3.0 V, which is the same as before the electronic shutter operation. Be drunk. For this reason, the source voltage of the MOS transistor M101 is 15V which is the difference between the gate voltage 18V and the gate-source voltage difference 3V. Therefore, the drain-source voltage difference of the MOS transistor M101 is 23V which is the difference between the drain voltage 38V and the source voltage 15V. This is the breakdown voltage of the MOS transistor M101 is 30V or less.

  Assume that the gate voltage of the MOS transistor M101 is kept at 3.5V without being changed during the electronic shutter operation. In this case, since the source voltage of the MOS transistor M101 is maintained at 0.5V, the drain-source voltage difference of the MOS transistor M101 is 37.5V which is the difference between the drain voltage 38V and the source voltage 0.5V. This exceeds the withstand voltage 30V of the MOS transistor M101.

  In this way, by increasing the voltage applied to the gate of the MOS transistor M101 in synchronization with the timing at which the shutter voltage is applied to the drain of the MOS transistor M101, the drain-source voltage difference is reduced as compared with the case where the shutter voltage is not applied. Therefore, the drain-source voltage difference can be suppressed to a withstand voltage or less.

  By raising the gate voltage of the MOS transistor M101, the source voltage of the MOS transistor M101 is raised. That is, the drain-source voltage difference of the MOS transistor M102 is enlarged, but the drain-source voltage difference of the MOS transistor M102 is limited by the gate voltage (high power supply voltage VH) of the MOS transistor M1, and therefore remains below the breakdown voltage.

  In the example described with reference to FIG. 3A, a voltage higher than the breakdown voltage of the MOS transistor is applied to the drain of the MOS transistor M101, and the drain-source voltage difference of the MOS transistor M101 and both are equal to or lower than the breakdown voltage. The voltage can be divided into the drain-source voltage difference of M102.

  When a voltage pulse whose absolute amplitude exceeds the withstand voltage is applied to the drain of the MOS transistor (NMOS or PMOS transistor), the voltage applied to the gate of the MOS transistor is synchronized with the application of the voltage pulse. By increasing the absolute value, the drain-source voltage difference can be suppressed to a withstand voltage or less.

  Next, a method for preventing a voltage higher than the withstand voltage from being applied to the MOS transistor M103 will be described with reference to FIG. It is assumed that OFDI input to the MOS transistor M104 during normal operation is 10V. During normal operation, the gate voltage Vbias2 for turning on the MOS transistor M107 is applied to the gate of the MOS transistor M107, and current is supplied to the MOS transistors M103 and M104. During normal operation, 10 V equal to OFDI is also applied to the gate of the MOS transistor M103.

  Since the threshold voltage Vth of the MOS transistors M103 and M104 is 2.5V and the saturation voltage is 0.5V, for example, the gate-source voltage difference between the MOS transistors M103 and M104 is 3.0V during normal operation. That is, during normal operation, for example, the source voltages of the MOS transistors M103 and M104 are 7V.

  As shown in FIG. 3B, a shutter voltage is applied to the gate of the MOS transistor M103 during the electronic shutter operation. Simultaneously (or slightly before the timing) when the shutter voltage is applied, the gate of the MOS transistor M107 is grounded. The control device C synchronizes the grounding of the gate with the application of the shutter voltage.

  By grounding the gate of the MOS transistor M107, the MOS transistor M107 is turned off, and no current is supplied to the MOS transistors M103 and M104. As a result, the gate-source voltage difference between the MOS transistors M103 and M104 becomes the threshold voltage Vth (2.5 V) or less. For this reason, the source voltage of the MOS transistor M103 is considered to rise to 35.5V, which is the difference between 38V and 2.5V. However, since the high power supply voltage VH is 18V, the source voltage of the MOS transistor M103 is changed to the power supply voltage 18V. stay.

  When the source voltage of the MOS transistor M103 rises to 18V, the gate-source voltage difference of the MOS transistor M103 becomes 20V, which is the difference between the gate voltage 38V and the source voltage 18V. This is a withstand voltage of 30 V or less of the MOS transistor M103.

  Suppose that the gate voltage of the MOS transistor M107 is not changed during the electronic shutter operation. In this case, since the source voltage of the MOS transistor M103 is maintained at 7V, the gate-source voltage difference of the MOS transistor M103 is 31V which is the difference between the gate voltage 38V and the source voltage 7V. This exceeds the withstand voltage 30 V of the MOS transistor M103.

  As described above, by increasing the source voltage of the MOS transistor M103 in synchronization with the timing at which the shutter voltage is applied to the gate of the MOS transistor M103, the gate-source voltage difference can be reduced as compared with the case where the shutter voltage is not applied. As a result, the gate-source voltage difference can be suppressed to a withstand voltage or less.

  Next, a configuration example of the switch circuit SW1 for switching the gate voltages of the MOS transistors M101 and M107 will be described with reference to FIG. The switch circuit SW1 includes MOS transistors M121 to M126.

  The switch switching voltage Vsw is input to the switch circuit SW1. The switch switching voltage Vsw is set to a high level during normal operation and to a low level during electronic shutter operation. The high level of Vsw is equal to the high power supply voltage VH (18V), and the low level of Vsw is equal to the ground potential (0V).

  A switch switching voltage Vsw is applied to the gates of the PMOS transistor M121 and the NMOS transistor M122. A high power supply voltage VH is applied to the source of the PMOS transistor M121. Vbias1 is applied to the source of the NMOS transistor M122. Vbias1 is a voltage to be applied to the gate of the MOS transistor M101 during normal operation. The drains of the PMOS transistor M121 and the NMOS transistor M122 are connected to the gate of the MOS transistor M101.

  When the switch switching voltage Vsw is at a high level (during normal operation), the PMOS transistor M121 is off and the NMOS transistor M122 is on, so that Vbias1 is applied to the gate of the MOS transistor M101 via the NMOS transistor M122. .

  When the switch switching voltage Vsw is at a low level (during electronic shutter operation), the PMOS transistor M121 is on and the NMOS transistor M122 is off, so that the high power supply voltage VH is connected to the gate of the MOS transistor M101 via the PMOS transistor M121. Is applied.

  The PMOS transistor M125 and the NMOS transistor M126 constitute an inverter circuit that receives the switch switching voltage Vsw. This inverter circuit outputs a ground potential when Vsw is at a high level, and outputs a high power supply voltage VH when Vsw is at a low level. The output of the inverter is applied to the gates of the PMOS transistor M123 and the NMOS transistor M124.

  Vbias2 is applied to the source of the PMOS transistor M123. Vbias2 is a voltage to be applied to the gate of the MOS transistor M107 during normal operation. The source of the NMOS transistor M124 is set to the ground potential. The drains of the PMOS transistor M123 and the NMOS transistor M124 are connected to the gate of the MOS transistor M107.

  When the switch switching voltage Vsw is at a high level (during normal operation), the inverter output is at a low level. Therefore, since the PMOS transistor M123 is turned on and the NMOS transistor M124 is turned off, Vbias2 is applied to the gate of the MOS transistor M107 via the PMOS transistor M123.

  When the switch switching voltage Vsw is at a low level (when the electronic shutter is operating), the inverter output is at a high level. Accordingly, the PMOS transistor M123 is turned off and the NMOS transistor M124 is turned on, so that the ground potential is applied to the gate of the MOS transistor M107 via the NMOS transistor M124.

  Thus, by using the switch circuit SW1, the voltage applied to the gates of the MOS transistors M101 and M107 can be switched.

  In the OFD control circuit according to the embodiment, since the shutter voltage is not applied to the source or drain of the PMOS transistor, problems associated with the forward bias voltage as described with reference to FIG. 11 are suppressed. Therefore, there is no restriction on the conductivity type of the semiconductor substrate.

  As described above, the solid-state imaging module according to the embodiment can be easily manufactured even when an n-type substrate is used, and can be easily manufactured even if the breakdown voltage of the MOS transistor is not particularly high.

  Next, the structure of the diode 131b is described with reference to FIGS. 5A is a plan view of a region where the diode 131b of the semiconductor substrate is formed, and FIG. 5B is a cross-sectional view of the region where the diode 131b of the semiconductor substrate is formed. (C) is an equivalent circuit diagram of the diode 131b.

As shown in FIG. 5A, a high breakdown voltage p-well 202 is formed on the surface of an n-type substrate 201. The impurity concentration of the high breakdown voltage p-well 202 is about 1 × 10 ¹⁶ atoms / cm ³ .

An octagonal first n ⁺ -type region 203 and a ring-shaped second n ⁺ -type region 204 surrounding the first n ⁺ -type region are formed inside the high breakdown voltage p-well 202. First n ⁺ -type region 203 and second n ⁺ -type region 204 are separated from each other by p-well 202. The impurity concentration of the first n ⁺ -type region 203 and the second n ⁺ -type region 204 is 1 × 10 ²⁰ atoms / cm ³ or more. The distance between the first n ⁺ -type region 203 and the second n ⁺ -type region 204 is, for example, 1 to 3 μm.

A p ⁺ type contact region 205 is formed in the p well 202 in a region away from the first and second n ⁺ type regions. The impurity concentration of the p ⁺ type contact region 205 is 1 × 10 ¹⁹ atoms / cm ³ or more. The p ⁺ type contact region 205 can be regarded as a part of the p well 202.

As shown in FIG. 5B, a buried p-well 206 is formed under the high breakdown voltage p-well 202. The impurity concentration of the buried p-well 206 is about 5 × 10 ¹⁶ atoms / cm ^{3 to} 5 × 10 ¹⁷ atoms / cm ³ . The depth of the buried p-well 206 is, for example, 3 μm, and the depth of junction between the buried p-well 206 and the n-type substrate 201 is, for example, 4-6 μm.

The first n ⁺ -type region 203, the p-well 202, and the second n ⁺ -type region 204 constitute a lateral NPN bipolar transistor NPN1. A diode 131b is configured by directly connecting the base and collector of the lateral NPN bipolar transistor NPN1. The first n ⁺ -type region 203 is connected to the cathode terminal Ca of the diode 131b. Both the second n ⁺ type region 204 and the p ⁺ type contact region 205 are connected to the anode terminal of the diode 131b.

The n ⁺ -type region 203, the p-well 202, and the n-type substrate 201 constitute a vertical NPN bipolar transistor NPN2 as a parasitic element. However, when the p-well 202 is formed by high energy ion implantation, since the impurity concentration at the bottom of the p-well 202 is higher than the impurity concentration at other portions of the p-well, the electron transport efficiency is low, and the current amplification factor of the transistor NPN2 (HFE) is much smaller than that of the transistor NPN1 and can be ignored.

  Note that when forming the p-well 202 without performing high-energy ion implantation, the hFE of the parasitic transistor NPN2 may not be ignored. However, in this case, as shown in FIG. 6, the transistor NPN2 operates as a mere current source, and has only an influence that the output voltage is slightly offset, so that no particular problem occurs.

  Next, a voltage applied to the diode 131b during the electronic shutter operation will be described with reference to FIG. During the electronic shutter operation, a shutter voltage (38 V) is applied to the cathode. Since the cathode and the anode are electrically separated, the anode voltage during the electronic shutter operation remains 10.7 V, which is the OFD voltage 10 V plus the threshold voltage 0.7 V of the diode 131 b. Therefore, the voltage difference between the anode and the cathode is 27.3V. This is 30V or less of the withstand voltage of the diode 131b.

Next, consider the parasitic transistor NPN2. The collector (n-type substrate 201) of the parasitic transistor NPN2 is connected to the high power supply voltage VH (18V). A shutter voltage (38 V) is applied to the emitter (first n ⁺ -type region 203). Therefore, the voltage difference between the collector and the emitter is 20V. This also has a breakdown voltage of 30 V or less.

  Next, advantages of the arrangement of the diode 131b in the circuit will be described. Generally, when a diode is used, it is necessary to flow a constant constant current. If this current does not flow, it is equivalent to not being connected in direct current.

  In the above-described OFD amplifier circuit 131a, a diode 131b is inserted in series between the MOS transistors M111 and M101. In the OFD amplifier circuit 131a, a bias current is passed through the MOS transistors M109, M111, M101, and M102. For this reason, the bias current for flowing through the MOS transistors M109, M111, M101, and M102 can also be used as the bias current for the diode 131b. It is not necessary to pass a bias current only for the diode 131b.

  FIG. 7 shows an output part of the OFD amplifier circuit of the solid-state imaging module according to the reference example. The solid-state imaging module of the reference example shows an example of a circuit configuration in which no diode is inserted in series between the MOS transistors M111 and M101.

  In the circuit of the reference example, the anode of the diode D is connected to the drain of the MOS transistor M111 and the drain of the MOS transistor M101. The cathode of the diode D is connected to the capacitor 111 for capacitive coupling.

  In such a circuit, a biasing resistance element R is required between the cathode of the diode D and the ground. Such a resistance element is not necessary in the circuit according to the embodiment.

  In the circuit of the reference example, in addition to the original bias current, a diode bias current also flows through the MOS transistors M109 and M111. As a result, performance degradation as an operational amplifier (voltage gain) Decrease). When the voltage gain is A, the relationship between the input voltage Vin and the output voltage Vout is as follows:

It is expressed by the formula. When the voltage gain A is reduced, the accuracy of the output voltage OFDO is reduced.

  In the circuit of the reference example, a phase compensation capacitor C is required between the anode of the diode D and the ground. Since a shutter voltage is applied during the electronic shutter operation, a reverse bias is applied to the diode D. At this time, the circuit is electrically disconnected before and after the diode D. At this time, if the capacitor C is not arranged, the phase margin of the amplifier circuit cannot be obtained, and the circuit becomes unstable (oscillation or ringing of the waveform occurs).

  In the circuit of the embodiment, during normal operation, the capacitive coupling capacitor 111 also plays a role of phase compensation. During the electronic shutter operation, the MOS transistor M107 is grounded, and the differential pair composed of the MOS transistors M103 to M107 does not operate as a circuit. For this reason, during the electronic shutter operation, the circuit of the embodiment does not have a gain as an amplifier circuit.

  The conditions for oscillation in the feedback system are when the gain is 1 or more and the phase is rotated 180 ° or more. Since no oscillation can occur as long as the amplifier circuit does not have a gain, the circuit of the embodiment does not require phase compensation during the electronic shutter operation. Therefore, in the circuit of the embodiment, it is not necessary to arrange a phase compensation capacitor in addition to the capacitive coupling capacitor 111.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

It is a block diagram which shows the structure of the solid-state image sensor driven by the solid-state imaging module by the Example of this invention, and the solid-state imaging module of an Example. It is a circuit diagram which shows schematically the OFD amplifier circuit by an Example. FIG. 3A and FIG. 3B are circuit diagrams for explaining a method of driving the OFD amplifier circuit according to the embodiment. FIG. 3 is a circuit diagram schematically showing a switch circuit according to an embodiment. 5A is a plan view of a region where the diode 131b of the semiconductor substrate is formed, and FIG. 5B is a cross-sectional view of the region where the diode 131b of the semiconductor substrate is formed. (C) is an equivalent circuit diagram of the diode 131b. It is a circuit diagram which shows that a parasitic bipolar transistor operates as a current source. It is a circuit diagram which shows roughly a part of solid-state imaging module by a reference example. It is a block diagram which shows the structure of the solid-state imaging module by the previous proposal, and the solid-state imaging device driven with the said solid-state imaging module. It is a block diagram in the case where the OFD control circuit included in the solid-state imaging module proposed above is configured with CMOS. It is an example of the circuit which comprised the switch circuit of the proposal previously shown in FIG. 9 with CMOS. FIG. 11A and FIG. 11B are circuit diagrams for explaining problems that may occur in the solid-state imaging module proposed above. It is a circuit diagram which shows the conventional solid-state imaging module schematically.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Solid-state imaging module 102 CCD area sensor 131 OFD control circuit 131a OFD amplifier circuit 131b Diode 132 Pulse generation circuit 111 Capacitance M101-M111 MOS transistor SW1 Switch circuit C Control circuit 201 N-type board | substrate 202 P well 203 1st n ⁺ type area | region 204 Second n ⁺ type region 205 p ⁺ type contact region Ca Cathode terminal An An anode terminal

Claims (4)

A substrate voltage control means for a solid-state imaging device, including an operational amplifier;
A pulse generation circuit for generating a voltage pulse,
The output stage of the operational amplifier includes a PMOS transistor, a diode, and an NMOS transistor, the drain of the PMOS transistor and the anode of the diode are connected, and the cathode of the diode and the drain of the NMOS transistor are connected. The PMOS transistor, the diode, and the NMOS transistor are formed on the same semiconductor substrate,
The pulse generation circuit is a solid-state imaging module that applies a voltage pulse to the cathode of the diode.   The diode has a lateral bipolar structure including a p-type region formed on the surface of the semiconductor substrate and first and second n-type regions formed apart from each other in the p-type region. The solid-state imaging module according to claim 1, which is a base-collector direct connection type diode.   The solid-state imaging module according to claim 1, wherein the second n-type region is disposed so as to surround the first n-type region.   4. A control circuit for increasing a voltage applied to the gate of the NMOS transistor in synchronization with a timing at which a voltage pulse is applied to the drain of the NMOS transistor connected to the cathode of the diode. The solid-state imaging module according to any one of the above.

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