JPH10136285A - Video signal converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the video signal processing unit that conducts companding processing of an image. SOLUTION: An input video signal is fed to a memory 14 via an interpolation filter 12. A signal is read from the memory 14 in a form that a horizontal direction and a vertical direction of the input signal are replaced with each other, and in the case of processing of the input signal in the vertical direction, processing in the horizontal direction is applied to an output of the memory 14. A read output from the memory 14 is given to an interpolation filter 15. The interpolation filter 15 is made up of delay elements 120-122 arranged in series and coefficient devices 123-126 receiving outputs from the delay elements 120-122 and the input video signal and outputs from the coefficient devices 123-126 are added by an adder circuit 121.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal conversion device which is a television signal for converting an aspect ratio of a screen.

[0002]

2. Description of the Related Art In an NTSC color television broadcast currently being broadcast in Japan, the aspect ratio of a screen is set to 4: 3. On the other hand, in a high-definition HDTV, a landscape aspect ratio of 16: 9, which is longer than that of the current television broadcasting, is preferable. In the case of Hi-Vision and Wide-Clear Vision, broadcasting on such a 16: 9 screen is performed, and therefore, television receivers having a 16: 9 aspect ratio screen are widely used.

As a means for effectively using such a large-screen wide television screen having an aspect ratio of 16: 9, it is fundamental to display a powerful image utilizing the width of the screen. For example, a two-screen display in which the screen is divided into two parts in the horizontal direction and used is performed. When such a two-screen display is performed, two images cannot be displayed on one screen if the received television signal is left as it is. Therefore, it is necessary to change the screen size, that is, to compress or expand the screen.

For example, a case where a screen is compressed horizontally and vertically by 3/4 will be described. As shown in FIG. 4, a television image signal received by an antenna and subjected to reception processing by a tuner is input to a terminal 51. Is done. This input video signal is input to the horizontal processing unit 52, and compression or expansion processing in the horizontal direction is performed. The compressed or decompressed video signal from the horizontal processing unit 52 is further processed by the vertical processing unit 53
And is compressed or expanded in the vertical direction.
Then, the output from the vertical processing unit 53 is output from the terminal 54 as an output video signal.

The control signal generating circuit 54 receives the horizontal synchronizing signal (HD) and the vertical synchronizing signal (VD) at terminals 55 and 56.
Is entered from The control signal generation circuit 54 outputs a horizontal processing control signal and a vertical processing control signal. The horizontal processing control signal is input to the horizontal processing unit 52, and the vertical processing control signal is input to the vertical processing unit 53. . The horizontal processing unit 52 controls compression or expansion processing in the horizontal direction and the vertical processing unit 53 controls compression or expansion processing in the vertical direction.

FIG. 5 shows a specific configuration of the horizontal processing section 52. An input video signal is input from a terminal 501 and input to delay elements 502 to 504 connected in series. Each of the delay elements 501 to 504 sequentially delays the input signal by one clock. The input signal and the output from each of the delay elements 502 to 504 are converted by a coefficient unit.
505 to 508 are input. These coefficient units 505-
In 508, the input signal is multiplied by k1 times, k2 times,
The output is multiplied by k3 and k4.

The output signals from each of the coefficient units 505 to 508 are added in an adder circuit 509 and output. The output is input to a memory 510.
Then, all input signals are written according to a write control signal output from the control circuit 511. Also,
In this memory 510, a signal which has already been written is read in response to a read control signal from the control circuit 511. This read output is output from a terminal 512 as an output signal from the horizontal processing section 52. .

The control circuit 511 receives a horizontal processing control signal from a terminal 513. The control circuit 511 outputs a coefficient control signal, a write control signal, and a read control signal. 508 and memory 510
Is performed. More specifically, the coefficients are input to coefficient units 505 to 508 to switch the respective coefficients, and a write control signal and a read control signal are supplied to a memory 510 to control writing and reading, respectively.

Next, the principle of the compression process will be described with reference to FIG. Here, as an example, a case in which the compression is performed by 3/4 will be described. Here, A1, A2,... In the figure (A) are the original signals, and the circles in the figure represent pixels. This is 3
When compression is performed at / 4 times, the pixel interval is 3/4 times as shown in FIG. 7B. However, since the interval from the input signal is different as it is in FIG. As shown, the signals are converted into signals of the original pixel intervals B1, B2,.
This conversion is performed by interpolating the original signal, and in this example, can be expressed by the following equation.

B1 = M3 × A1 + Mo × A2 + M3 × A3B2 = M4 × A2 + M1 × A3 + M2 × A4 + M5 × A5 B3 = M5 × A3 + M2 × A4 + M1 × A5 + M4 × A
6 By repeating the processing represented by this equation,
A double compressed signal can be obtained.

When the operation of the horizontal processing unit 52 thus configured is performed with reference to FIG. 7, the video signal input from the terminal 501 is as shown in FIG. And the delay element 50
Outputs from 2 to 504 are as shown in (B), (C) and (D), respectively. Here, coefficient units 505 to 508
Are set as shown in the diagrams (E), (F), (G) and (H), the output from the adder circuit 509 is intermittently compressed to 3/4 times as shown in the diagram (I). Signals B1, B
2, ... are obtained. Since this signal is an unnecessary signal for every four pixels, only the necessary signal is written into the memory 510. Then, by continuously reading the signal written in the memory 510, a signal compressed to 3/4 times can be obtained.

FIG. 8 shows the structure of the vertical processing unit 53.
The input video signal from the terminal 521 is sequentially supplied to one-line delay circuits 522 to 524 connected in series. The input video signal and the output from each of the one-line delay circuits 522 to 524 are supplied to coefficient units 505 to 508.
.. 508 are added by an adder circuit 509 and written to the memory 525.

The vertical synchronizing signal input to the terminal 525 is input to the control circuit 526, and the output from the control circuit 526 is supplied to the coefficient units 505 to 508 and the memory 510 as a control signal.

The one-line delay circuits 522 to 524 delay the input signal by one line and output the signals. Therefore, the interpolation processing performed in the coefficient units 505 to 508 and the addition circuit 509 is vertical processing. You. Then, processing similar to that described with reference to FIGS. 6 and 7 is performed in the vertical direction, and compression processing in the vertical direction is performed. Therefore, the compression processing and the expansion processing are freely performed in the horizontal and vertical directions in this manner. However, a large number of one-line delay circuits are required particularly for performing the processing in the vertical direction, and the circuit configuration is inevitably increased in size.

[0015]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has been developed in order to deal with the problem that a large number of line memories and the like are required for performing vertical processing. An object of the present invention is to provide a video signal conversion device which can surely reduce the circuit scale without using a line memory for vertical processing.

[0016]

A video signal converter according to the present invention intermittently outputs a signal whose input signal has a limited band, and writes the intermittently output signal to a memory according to a write address. , And read in accordance with the read address. Then, the read address and the write address are controlled so that the output read from the memory is switched between the horizontal direction and the vertical direction of the input signal, so that the processing in the vertical direction is performed.

That is, according to such a video signal conversion apparatus, since processing in the vertical direction can be performed without using a line memory, the video signal conversion apparatus can be sufficiently miniaturized without increasing the circuit scale. .

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. This embodiment performs an operation of 3/4 compression, and FIG. 1A shows a basic configuration thereof. That is, the video signal input to the input terminal 11 is input to the interpolation filter 12. The interpolation filter 12 includes delay elements 120 to 122 arranged in series as shown in FIG.
Coefficient multiplier 123 supplied with output from each of 120 to 122
And outputs from the respective coefficient units 123 to 126 are added by an adder circuit 127. The coefficient units 121 to 123 of the interpolation filter 12 are controlled by the control circuit 13, and the operation of the circuit portion configured as described above is the same as that described with reference to FIG.

That is, in the interpolation filter 12, the band of the input video signal is limited and an intermittent output can be obtained. The output from the interpolation filter 12 is supplied to the memory 14.

The output of the interpolation filter 12 is, for example, 3 /
In the case of quadruple compression, unnecessary data is obtained for every four pixels. Therefore, in the memory 14, only necessary data is written, and reading from the memory 14 is performed as follows.
This is performed in such a manner that the horizontal direction and the vertical direction of the input signal are interchanged. Therefore, when processing the input signal in the vertical direction, the output of the memory 14 may be processed in the horizontal direction.

The read output from the memory 14 is input to the interpolation filter 15, and the configuration of the interpolation filter 15 is the same as that of the interpolation filter 12. The interpolation filter 12 performs horizontal processing, but the interpolation filter 15 performs vertical processing for the above-described reason. The output from the interpolation filter 15 is
Like the output from, the data is unnecessary intermittent data every four pixels. The output from the interpolation filter 15 is input to the memory 16 and only the necessary data is written.

Reading from the memory 16 is performed in such a manner that the horizontal direction and the vertical direction of the input of the memory 16 are exchanged, and as a result, the output from the memory 16 returns to the original horizontal and vertical directions. This memory 16
Is supplied to a terminal 17 to be an output video signal.

For the control circuit 13, a horizontal synchronizing signal (H
D) and a vertical synchronizing signal (VD).
The control circuit 13 outputs control signals for the coefficient units of the interpolation filters 12 and 15, and control signals for the memories 14 and 16.

That is, the input image signal is interpolated by the interpolation filter 12.
The output is intermittently output, written to the memory 14 according to the write address, and read from the memory 14 according to the read address. Reading from the memory 12 is performed in such a manner that the horizontal direction and the vertical direction of the input signal are switched. Therefore, in the processing in the vertical direction, a one-line delay circuit is not required, and
A video signal processing device with a small hardware scale can be configured.

FIG. 2 shows a second embodiment.
Is supplied to the multiplex processing circuit 30. The output from the multiplex processing circuit 30 is input to the interpolation filter 31, and the output from the interpolation filter 31 is input to the memory 32. Then, the read output from the memory 32 is input to the separation processing circuit 33, and one of the two separated signals from the separation processing circuit 33 is supplied to the multiplex processing circuit 30 and multiplexed with the input video signal. . Then, the other output of the separation processing circuit 33 is output from the terminal 34 as an output video signal. Horizontal synchronization signal (HD) and vertical synchronization signal (V
D) is input to a control circuit 35, which controls the interpolation filter 31 and the memory 32.

The video signal input from the input terminal 11 passes through the multiplex processing circuit 30, and then is passed through an interpolation filter 31 and a memory 32.
Thus, horizontal compression processing and horizontal and vertical rearrangement are performed. Thereafter, the signal is supplied again to the interpolation filter 31 and the circuit section of the memory 32 through the separation processing circuit 33 and the multiplex processing circuit 30. At this time, compression processing in the vertical direction and rearrangement in the horizontal and vertical directions are performed. And
The signal is separated and extracted by the separation processing circuit 33, and is taken out to the terminal 34 as an output video signal.

Therefore, the interpolation filter 31 and the memory 32 perform both horizontal processing and vertical processing. For example, if time-division processing is performed in the multiplex processing circuit 30, horizontal processing and vertical processing in the interpolation filter 31 and the memory 32 may be performed in a time-division manner.

FIG. 3 shows a third embodiment. As in the first embodiment shown in FIG. 1, a video signal input to a terminal 11 is supplied to an interpolation filter 12, and its output is stored in a memory. 13
Is written to. The read output from the memory 14 is supplied to an interpolation filter 15, and the interpolation filter 15
Is input to the video display device 40. The horizontal synchronization signal (HD) and the vertical synchronization signal (VD) are input to the control circuit 13. This control circuit 13 includes an interpolation filter
The horizontal synchronization signal and the vertical synchronization signal which are supplied as control signals to 12 and 15 and the memory 14 are supplied to the video display device 40.

In the memory 14, the horizontal direction and the vertical direction of the input signal are interchanged and output. For this reason, the output of the interpolation filter 15 is also
Is input, the display is displayed with the horizontal direction and the vertical direction interchanged.

In an ordinary image display device, an image is displayed by displaying an input signal in a horizontal direction and displaying the signal in a vertical direction from top to bottom. In the image display device 40, since the horizontal direction and the vertical direction of the input signal are switched, the image display device is operated to sequentially display the vertical display in the horizontal direction. . Therefore, the image displayed on the image display device 40 is normal.

In the above description, an example in which processing is performed using four pixels in the interpolation filter has been described. However, the present invention is not limited to this, and the number of pixels used may be increased or decreased. Similar effects can be obtained. In the above description, 3/4 compression has been described as an example. However, the present invention is not limited to this ratio, but can be applied to any ratio. The technique is adaptable.

[0032]

As described above, according to the video signal conversion apparatus of the present invention, the processing in the vertical direction can be performed using the memory, so that the configuration is sufficiently small in hardware scale. , The image can be compressed or decompressed.

[Brief description of the drawings]

FIG. 1A is a circuit configuration diagram illustrating a video signal processing device according to a first embodiment of the present invention, and FIG. 1B is a configuration diagram illustrating an example of an interpolation filter of the device.

FIG. 2 is a circuit diagram illustrating a second embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating a third embodiment of the present invention.

FIG. 4 is a circuit diagram illustrating a conventional video signal processing device.

FIG. 5 is a diagram illustrating a configuration of a horizontal processing unit of the apparatus.

FIG. 6 is a view for explaining the principle of compression processing of the horizontal processing unit.

FIG. 7 is a diagram illustrating the operation principle of the horizontal processing unit.

FIG. 8 is a diagram illustrating a configuration of a vertical processing unit of the device.

[Explanation of symbols]

12, 15, 31 ... interpolation filter, 13, 35 ... control circuit, 14, 1
6, 32 ... memory, 121-123 ... delay element, 123-126 ...
Coefficient unit, 127 ... Addition circuit, 30 ... Multiple processing circuit, 33 ... Separation processing circuit, 40 ... Image display device.

Claims (6)

[Claims] A writing unit for writing an input video signal to a memory in accordance with a write address; a reading unit for reading a video signal written in the memory in accordance with a read address; Control means for controlling the read address and the write address so that the horizontal and vertical directions of the signal are interchanged and intermittent, and signal generation means for generating a signal with a missing output from the memory. A video signal conversion device characterized in that: 2. The apparatus according to claim 1, further comprising means for limiting a band of the input video signal, and intermittently outputting the band-limited signal, and the output is written to the memory.
The video signal conversion device according to the above. 3. A signal multiplexing unit that receives an input video signal as a first signal and multiplexes the signal with another second signal; a writing unit that writes the multiplexed signal to a memory according to a write address; Reading means for reading the signal stored in the memory according to the read address; and the read address and the write address so that the read output from the memory is intermittent while the horizontal and vertical directions of the input video signal are interchanged. And a signal generation unit that generates a signal with a missing output from the memory; and a signal separation unit that separates the generated signal into an output signal and the second signal. The second signal separated by the signal separating means is multiplexed with the input video signal by the signal multiplexing means. Video signal converting means. 4. A band of a signal multiplexed by said signal multiplexing means is limited, and said band-limited multiplexed signal is written to said memory, and an output from said memory is multiplexed. 4. The video signal converter according to claim 3, wherein the horizontal direction and the vertical direction of the signal are interchanged. 5. The input video signal is written to the memory, and a signal written according to a read address is read, and a read output from the memory is switched between a horizontal direction and a vertical direction of the input video signal. 5. The image processing apparatus according to claim 4, further comprising address control means for inputting a readout output from said memory to an image display means, wherein said input signal causes a vertical display to be performed while moving in a horizontal direction. Video signal converter. 6. A first band limiting unit for limiting a band of an input video signal, a writing unit for writing the first band-limited signal to a memory according to a write address, and reading from the memory according to a read address. Read means; control means for controlling the read address and the write address so that the read output from the memory is switched between the horizontal direction and the vertical direction of the output signal from the first band limiting means; and A second band limiting unit for limiting the band of the read output; and an image display unit to which the output of the second band limit unit is input. The image display unit displays the input signal in a vertical direction. A video signal conversion device characterized in that the video signal conversion is performed while moving in the horizontal direction.