JPH10136040A - Phase modulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase modulation circuit reduced in circuit scale and power consumption. SOLUTION: In the circuit, a Gray code generator 21, an Ex-OR circuit and a cosine wave/sine wave table 23 respectively output cosines obtained, by adding the codes of cosine waves vibrating at the frequency of modulation waves to the sines of phase modulation signals to a cosine wave register 25 through a delay register 24 and output the cosines obtained by adding the codes of the cosine waves to the cosines of the phase modulation signals to a sine wave register 26. Then, an adder 7 adds them and a D/A converter 8 converts the added value into an analog signal, and BPF 9 extracts a fundamental wave which is the modulation wave from the analog signal so as to output it.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase modulation circuit used in a wireless communication device, and more particularly, to a method of generating a phase modulation wave without using an integrator, thereby reducing the circuit scale and reducing the power consumption of the modulation wave. And a phase modulation circuit capable of outputting the same.

[0002]

2. Description of the Related Art A conventional phase modulation circuit will be described with reference to FIG. FIG. 5 is a configuration block diagram illustrating an example of a conventional phase modulation circuit. The conventional phase modulation circuit performs phase modulation using the sine addition theorem, and as shown in FIG. 5, a cosine wave table 1 and a sine wave table 2
, Carrier generation circuits 3 and 4, multipliers 5 and 6, adder 7, D / A converter 8, band-pass filter (BP
F) 9).

[0003] Each component will be described in detail below. The cosine wave table 1 receives the input of the phase signal θ, calculates the cosine cos θ corresponding to the input θ, and outputs it to the multiplier 5. The sine wave table 2 receives the input of the phase signal θ, calculates a sin sine corresponding to the θ, and outputs it to the multiplier 6.

[0004] The carrier generation circuit 3 receives an input from a carrier oscillator and receives sin (ω) for a constant angular velocity ωc.
The sine wave represented by ct) is generated as a carrier wave and output to the multiplier 5. The carrier generation circuit 4 receives an input from the carrier oscillator, and sets a constant angular velocity ωc to co.
A sine wave of s (ωct) is generated as a carrier wave and output to the multiplier 6. The outputs of the carrier wave generating circuits 3 and 4 are performed by digital signals.

The multiplier 5 calculates the product of the cosine value cos θ input from the cosine wave table 1 and the sine wave sin (ωct) input from the carrier generation circuit 3 and adds the product.
Is output to

The multiplier 6 calculates the product of the sine value sinθ input from the sine wave table 2 and the cosine wave cos (ωct) input from the carrier wave generation circuit 4 and adds the product.
Is output to

The adder 7 receives the inputs from the multipliers 5 and 6, respectively, adds them, calculates the following equation (1), and calculates the carrier wave whose phase is shifted by θ. D /
The signal is output to the A converter 8.

[0008]

(Equation 1)

A D / A converter 8 converts a carrier wave shifted in phase by θ into an analog signal, and converts the carrier wave into a phase modulated signal.
Output to PF9. The BPF 9 receives a phase modulation signal from the D / A converter 8 and outputs a modulated wave obtained by extracting only a necessary frequency band from the analog signal. The conventional phase modulation circuit outputs a modulated wave in this manner.

[0010]

However, the above-mentioned conventional phase modulation circuit has a problem that a multiplier is required, the circuit scale cannot be reduced, and the power consumption cannot be reduced.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a phase modulation circuit capable of simplifying a circuit, reducing a circuit scale, and reducing power consumption.

[0012]

According to a first aspect of the present invention, there is provided a phase modulation circuit, wherein an MSB of a phase modulation signal of a cosine wave / sine wave table used for phase modulation is used in a phase modulation circuit. And performing binary phase modulation by alternately outputting the exclusive OR of the MSB of the phase modulation signal and the upper and lower bits of a 2-bit periodic Gray code that changes faster than the phase modulation signal. Therefore, the circuit scale can be reduced or the power consumption can be reduced.

According to a second aspect of the present invention, there is provided a phase modulation circuit for synchronizing a frequency of a periodic Gray code with a carrier frequency. The circuit scale or power consumption can be reduced.

According to a third aspect of the present invention, there is provided a gray code generator, an exclusive OR circuit, a cosine / sine wave table, a delay register, and a cosine wave register. , A sine wave register, an adder,
A D / A converter and a BPF, wherein the Gray code generator outputs a 2-bit periodic Gray code at a carrier frequency, and outputs the upper bits of the Gray code at a frequency twice the carrier frequency. A gray code generator that outputs “1” and “0” alternately as a clock signal in synchronization with the timing of outputting the lower bits.
The exclusive OR circuit outputs an exclusive OR of an MSB of a phase modulation signal and the periodic Gray code input from the Gray code generator to each of the cosine and sine wave tables alternately. A cosine wave / sine wave table, wherein the cosine wave / sine wave table is a cosine value and a sine value of a signal obtained by replacing the MSB of the phase modulation signal with an exclusive OR output from the exclusive OR circuit. Is a cosine wave / sine wave table that sequentially outputs as digital information, wherein the delay register receives an input of a clock signal from the Gray code generator, and outputs the upper bits of the Gray code while outputting the higher bit. The digital information input from the cosine wave / sine wave table is latched, and the low-order bit of the gray code is output to the cosine wave register. A delay register for outputting digital information, wherein the cosine register receives an input of a clock signal from the gray code generator and receives digital information from the delay register while the lower bits of the gray code are being output. And a cosine register that receives and latches the clock signal from the gray code generator and outputs the lower bit of the gray code while receiving the clock signal from the gray code generator. Is a sine register that receives and latches digital information from the cosine wave / sine wave register, and outputs the latched data to the adder.
An adder that receives digital information from the cosine register and the digital information from the sine register and adds and outputs the digital information; the D / A converter converts the digital information input from the adder into an analog signal And a D / A converter for converting and outputting the D / A.
It is a BPF that receives an analog signal input from a converter and extracts a fundamental wave, and can obtain a modulated wave without using a multiplier and a carrier generation circuit. Power consumption can be reduced.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a phase modulation circuit (this circuit) according to the present invention, sgn (sin (ωct)) is cos (kωc
t) to the Fourier series and sgn (co
Focusing on the fact that s (ωct) can be expanded into a Fourier series based on sin (kωct), the sine function and the sine
The circuit for calculating the sum of products with the cosine is simply realized by a digital circuit, and the circuit scale can be reduced and a modulated wave can be output with low power consumption. Where sgn
(X) is defined as in the following [Equation 2].

[0016]

(Equation 2)

This circuit will be described with reference to FIGS. FIG. 1 is a block diagram showing the configuration of this circuit, and FIG.
FIG. 4 is a timing chart illustrating the operation of the present circuit. As shown in FIG. 1, this circuit includes a Gray code generator 21, an exclusive OR circuit (Ex-OR circuit) 22,
A cosine wave / sine wave table 23, a delay register 24,
It comprises a cosine wave register 25, a sine wave register 26, an adder 7, a D / A converter 8, and a BPF 9.

Hereinafter, each part will be described in detail. As shown in FIG. 2A, the gray code generator 21 continuously and periodically outputs a changing 2-bit digital signal having a value of “1” or “0” as a gray code. . Here, fc represents a carrier frequency.

As shown in FIG. 2A, the output of the gray code generator 21 is "1, 1, 2" every 1 / (8fc).
1,0,0,0,0,1 "
In other words, when divided by 1 / (4fc), "11",
This means that digital signals that are 2-bit periodic gray codes of “10”, “00”, and “01” are output. That is, the gray code generator 21 determines that the upper bit and the lower bit of the gray code are 1 / (8f
The output is alternately performed every c).

Further, the gray code generator 21 outputs, for example, a clock signal (CL) having a timing of 1 / (8fc).
K) is output to the delay register 24, the cosine wave register 25, and the sine wave register 26.

The Ex-OR circuit 22 receives the MSB (Most Significant) of the phase signal θ input as a digital signal.
Bit) and the gray code input from the gray code generator 21 are calculated, and the exclusive OR is replaced with the MSB of the original phase modulation signal θ and output. Hereinafter, only the MSB of the phase modulation signal θ is Ex-
What is replaced by the output of the OR circuit 22 is referred to as “φ”. That is, φ is added with a phase rotation of “0” or “π” radians by a gray code as a carrier signal, in addition to the phase fluctuation caused by the phase modulation signal θ.

The cosine wave / sine wave table 23 receives the input of φ, and at the timing when the gray code generator 21 outputs the upper bit (G1) of the gray code, the cosine cos φ corresponding to the φ. To the delay register 24 and the sine wave register 26.

The cosine / sine wave table 23 has a φ
At the timing when the gray code generator 21 outputs the lower bit (G2) of the gray code,
The sin sine sine corresponding to the φ
And the sine wave register 26.

That is, of the 2-bit periodic Gray code, the upper bit (G1) corresponds to the cosine wave, and when G1 is "0", cos θ is output to the cosine wave register 27 as cos φ, and G1 is When "1", -cos
θ is output to the cosine wave register 27 as cos φ.

In the 2-bit periodic Gray code, the lower bit (G2) corresponds to a sine wave, and when G2 is "0", sinθ is output to the sine wave register 26 as sinφ, and G2 is When "1", -sin
θ is output to the sine wave register 26 as sinφ.

That is, by the upper bit (G1) and the lower bit (G2) of the two-bit periodic Gray code, binary phase modulation of 0 or π radian is equally applied to cos θ and sin θ. . This is because the phase modulation signal θ is a signal modulo 2π radians,
The fact that the logical value of the MSB is not inverted by the x-OR circuit 22 corresponds to a phase change of 0 radians.
Inverting the logical value of the MSB corresponds to a phase change of π radians, which is based on the principle that it is equivalent to binary phase modulation.

Thus, for example, 0 (= 0 / f)
For Gray codes output between c) and 1 / (4fc), -cos θ and -sin θ are 1 / (4f
For the Gray code output between c) and 1 / (2fc), -cos θ and sin θ are output to the delay register 24 and the sine wave register 26, respectively.

Further, from 1 / (2fc) to 3 / (4f
For the Gray code output during c), cos
For a Gray code in which θ and sin θ are output between 3 / (4fc) and 1 / fc, cos θ and -si
nθ is the delay register 24 and the sine wave register 2
6 is output.

The delay register 24 receives the clock signal from the gray code generator 21, delays the input digital information by 1 / (8fc), and outputs the delayed digital information to the cosine wave register 25. In addition, cosine wave register 2
5 and the sine wave register 26 latch the input digital information for a predetermined time and receive the clock signal from the gray code generator 21 so that the gray code generator 21 outputs the lower bits of the gray code. At this time, the latched digital information is output to the adder 7.

The operation timing of the delay register 24, the cosine wave register 25, and the sine wave register 26 will be described later in detail.

When the frequency of the periodic change of the upper and lower bits of the periodic Gray code is set to be the same as the angular frequency ωc of the carrier, the cosine wave register 25 stores cos θ as the upper bit of the Gray code, sgn (sinωct). Sgn (sin), which is digital information amplitude-modulated by
ωct) · cosθ is latched, and the sine wave register 26 stores sgn (cosωct) · sinθ in which sinθ is digital information amplitude-modulated by sgn (cosωct) which is the lower bit of the gray code.
Is latched.

The adder 7 adds digital information input from the cosine wave register 25 and the sine wave register 26 and outputs the digital information to the D / A converter 8. Therefore, the digital signal output from the adder 7 is stored in the cosine wave register 2
5 and the sine wave register 26 add the digital signal latched at the timing when the gray code generator 21 outputs the lower bits, and the result is shown in the following [Equation 3].

[0033]

(Equation 3)

The D / A converter 8 and the BPF 9 are the same as those of the prior art, and the description is omitted.

Here, the operation timing of the delay register 24, the cosine wave register 25, and the sine wave register 26 will be described in detail. FIG. 2A shows a gray code generator 2.
1 shows an example of a periodic Gray code output by 1.
As described above, in the periodic Gray code, the set of the upper bit (G1) and the lower bit (G2) is 1 / (4f).
c) "11", "10", "00", "01"
The digital information is repeated.

The clock signal output from the gray code generator 21 is, as shown in FIG.
It is a signal of "1" and "0" that alternate at the timing of (8fc). The delay register 24 latches the input digital information at the falling timing of the clock signal (timing between G1 and G2) and at the rising timing (timing between G2 and G1 of the next gray code). , And outputs the latched digital information to the cosine wave register 25.

The cosine wave register 25 and the sine wave register 2
Reference numeral 6 indicates that the input digital signal is latched and output at the rising timing of the clock signal.

Next, the operation of this circuit will be described with reference to FIG. The MSB of the phase signal θ externally given as a digital signal is extracted, the Ex-OR 22 calculates the exclusive OR of the MSB and the output of the gray code generator 21, and the MSB of the phase modulation signal θ is obtained by the Ex-OR 22
The signal φ replaced by the output of cosine wave / sine wave table 2
3 is input.

The cosine wave / sine wave table 23 outputs cos φ to the delay register 24 and the sine wave register 26 at the timing when the gray code generator 21 outputs the upper bit (G1). Specifically, t = 0 in FIG.
At the timing, the MSB of cos φ is “0”. In FIG. 2C, only the MSBs of the delay register 24, the cosine wave register 25, and the sine wave register 26 are shown.

When the gray code generator 21 outputs the low-order bit (G2) from the high-order bit (G1), the clock signal falls, and the delay register 24 and the sine wave register 26 store the cosine wave / sine wave. The cos φ output by the wave table 23 is latched, and the MSB is stored in the delay register 24 and the sine wave register 26.
Is stored as “0”.

Then, sin φ is output to the delay register 24 and the sine wave register 26 at the timing when the gray code generator 21 outputs the lower bit (G2).
Here, for example, if the MSB of sinφ is “0”, the sine wave register 26 stores a value whose MSB is “0”.

Eventually, the gray code generator 21 changes the lower bit (G2) to the upper bit (G
At the timing of outputting 1), the clock signal rises, and the delay register 24 outputs the digital information latched in the cosine wave register 25. Then, the MSB of the value stored in the cosine wave register 25 becomes “0”.

Here, the reason why the MSB is "0" is as follows.
Since a phase change of 0 radians corresponds to a phase change of π radians and “1” corresponds to a phase change of π radians, the cosine wave register 25 and the sine wave register 26 have sgn (si
An output equivalent to that subjected to amplitude modulation by nωct) and sgn (cosωct) is stored.

Further, at this timing, the cosine wave register 25 latches the digital information input from the delay register 24, outputs the digital information to the adder 7, and outputs the sine wave register 26
Latches sinφ output by the cosine wave / sine wave table 23 and outputs it to the adder 7. Then, the adder 7 adds and combines these cos φ and sin φ to calculate [Equation 3] and output it.

Then, the D / A converter 8 converts the digital information into an analog signal. This waveform is the output carrier sin of the carrier generation circuits 3 and 4 in the conventional circuit.
The modulated wave is the same as that obtained when a rectangular wave is used for each of ωct and cosωct.

Then, the D / A converter 8 outputs a spectrum as shown in FIG. FIG. 3 shows the D / A
FIG. 4 is an explanatory diagram illustrating a waveform output by a converter 8. The spectrum output from the D / A converter 8 is as shown in FIG.
Since the carrier based on the periodic Gray code is a square wave, in addition to the fundamental wave component, odd-order (3fc, 5fc in FIG. 3)
) Shows relatively large harmonic spurious.

Here, the reason why the odd-order relatively large harmonic spurious of the fundamental wave component appears in the spectrum output from the D / A converter 8 will be described. First, sgn (sinωct) and sgn (cos
ωct) can be Fourier-expanded as in the following [Equation 4].

[0048]

(Equation 4)

As is clear from (1) and (2) in [Equation 4], if k is an even number, its component (even-order component) is almost a value close to "0", but k is an odd number. , The component (odd order component) is | sin (x) / x | (where x is k
In proportion to the higher harmonics).

If the fundamental wave component of f (t) obtained by substituting [Equation 4] into [Equation 3] is f1 (t), f1 (t) is given by the following [Equation 5]. Become like

[0051]

(Equation 5)

As shown in [Equation 5], the phase modulation carrier signal f1 having the angular frequency ωc having the phase modulation signal θ as the phase angle.
It can be seen that (t) is obtained as a fundamental wave. Therefore, if harmonic components (harmonic spurs such as odd harmonics of the modulated wave) of the waveform output from the D / A converter 8 are removed by the BPF 9, the modulated wave shown in [Equation 5] can be obtained. .

If the center frequency of the BPF 9 is set to an odd-order harmonic (for example, k = 3, 5, etc.), the phase-modulated carrier signal fk of the carrier frequency kfc (k is an odd number of 3 or more).
(T) is obtained.

[0054]

Next, an embodiment of a modulated wave output by the present circuit will be described with reference to FIG. FIG. 4 is a comparative explanatory diagram of a modulated wave spectrum obtained by an experiment. 4A shows a modulated wave spectrum output from a conventional phase modulation circuit, and FIG. 4B shows a modulated wave spectrum output from the present circuit.

Here, the spectrum measurement conditions in each figure are as follows. Four-level FSK is adopted as the modulation method, carrier frequency fc = 455 KHz, and the characteristics of the BPF used are as follows.
Center frequency 455KHz, 3dB pass bandwidth 17KH
z. As can be seen by comparing FIGS. 4 (a) and 4 (b), although this circuit does not use a carrier wave generation circuit and a multiplier, it can generate a modulated wave equivalent to that of a conventional phase modulation circuit. You can see that it is outputting.

According to this circuit, a modulated wave can be output without using a carrier generation circuit and a multiplier, and the circuit size and power consumption can be reduced.

[0057]

According to the first and second aspects of the present invention, the MSB of the phase modulation signal of the cosine wave / sine wave table used for phase modulation is changed to the MSB of the phase modulation signal and a 2-bit signal which changes faster than the MSB of the phase modulation signal. Since the phase modulation circuit performs binary phase modulation by replacing the periodic gray code with the exclusive OR of the upper and lower bits and outputting the same alternately, the circuit scale is reduced without using a multiplier. Or power consumption can be reduced in some cases.

According to the third aspect of the present invention, the gray code generator alternately outputs the upper bit and the lower bit of the gray code at twice the carrier frequency, and the exclusive OR circuit outputs the gray code and the gray code. The exclusive OR with the MSB of the phase modulation signal is calculated, replaced with the MSB of the phase modulation signal, and output to the cosine wave / sine wave table. The cosine digital signal and the sine digital signal of the modulation signal are output in order, the delay register delays the cosine digital signal by the time of the lower bit of the gray code, and the cosine register receives the digital signal input from the delay register. And outputs the result to the adder, and the sine register latches the digital signal input from the cosine / sine wave table. Output to an arithmetic unit, an adder adds those values, a D / A converter converts the value into an analog signal, and a BPF extracts a fundamental wave and outputs a modulated wave as a phase modulation circuit. Therefore, a modulated wave can be obtained without using a multiplier and a carrier wave generation circuit, and there is an effect that a circuit scale can be reduced and power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of the present circuit.

FIG. 2 is a timing chart illustrating the operation of the present circuit.

FIG. 3 is an explanatory diagram illustrating a waveform output by a D / A converter.

FIG. 4 is a comparative explanatory diagram of a modulated wave spectrum obtained by an experiment.

FIG. 5 is a configuration block diagram illustrating an example of a conventional phase modulation circuit.

[Explanation of symbols]

1: Cosine wave table, 2: Sine wave table, 3, 4
... Carrier wave generation circuit, 5,6 Multiplier, 7 ... Adder,
8 D / A converter, 9 BPF, 21 Gray code generator, 22 Ex-OR circuit, 23 cosine / sine wave table, 24 switch, 25 cosine wave register, 26 sine wave register

Claims (3)

[Claims] 1. The MSB of a phase modulation signal of a cosine wave / sine wave table used for phase modulation and the MSB of a phase modulation signal and the upper and lower bits of a 2-bit periodic Gray code that changes faster than the phase modulation signal. A phase modulation circuit, which outputs an exclusive OR with a bit alternately and performs binary phase modulation. 2. The phase modulation circuit according to claim 1, wherein the frequency of the periodic Gray code is synchronized with the carrier frequency. 3. A gray code generator, an exclusive OR circuit, a cosine wave / sine wave table, a delay register, a cosine wave register, a sine wave register, an adder, and a D / A.
A gray code generator that outputs a 2-bit periodic Gray code at a carrier frequency and an upper bit and a lower bit of the gray code at a frequency twice the carrier frequency. A gray code generator that alternately outputs “1” and “0” as a clock signal in synchronization with the output timing of the phase-modulated signal. An exclusive-OR circuit for alternately outputting an exclusive-OR with the periodic Gray code input from the device to each of the cosine-wave and sine-wave tables, wherein the cosine-wave / sine-wave table includes The exclusive OR output from the logical OR circuit, and the MSB of the phase modulation signal
A cosine wave / sine wave table for sequentially outputting the cosine value and the sine value of the signal obtained by replacing the cosine value and the sine value as digital information, wherein the delay register receives a clock signal input from the Gray code generator, The digital information input from the cosine wave / sine wave table was latched while the upper bits of the gray code were being output, and the digital information was latched in the cosine wave register while the lower bits of the gray code were being output. A delay register that outputs digital information, wherein the cosine register receives a clock signal from the gray code generator and receives digital information from the delay register while the lower bits of the gray code are being output. A cosine register for receiving and latching, and outputting to the adder; Receives a clock signal from the Gray code generator, receives digital information from the cosine wave / sine wave register while the lower bits of the Gray code are being output, and latches the received digital information. A sine register for outputting to the adder, the adder receiving digital information from the cosine register and the digital information from the sine register, adding the digital information, and outputting the digital information; The DPF is a D / A converter that converts digital information input from the adder into an analog signal and outputs the analog signal. The BPF receives an analog signal input from the D / A converter and outputs a fundamental wave. A phase modulation circuit, which is a BPF for extracting a phase shift.