JP2542263B2 - Digital FM modulator - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an FM modulator used for recording a video signal, performing wireless communication, and the like, and is applicable to a large frequency deviation. A wide and highly stable FM modulation output can be obtained, and the circuit can be configured as a pure digital type.

[Related Art] When a video signal is recorded on an optical disk, a VTR, or the like, the video signal is usually once FM-modulated and then recorded.

The FM modulator used in such a case is the 9th
The multi-vibrator type shown in the figure and the frequency conversion type shown in FIG. 10 are well known.

The FM modulator 10 shown in FIG. 9 includes a pair of transistors 1 and 2
The base terminal 3 is supplied with a video signal as a modulation signal in common, and an FM modulation output is obtained from the terminal 4.

The FM modulator 10 shown in FIG. 10 has an FM modulator 6 having a center frequency of f1 and an FM modulator 7 having a center frequency of f2,
The FM modulation outputs are frequency mixed by the frequency converter 8. The low-pass filter 9 extracts only the difference frequency (f1-f2) from the FM modulation output after frequency mixing.

When the direction of frequency deviation is opposite between FM modulators 6 and 7, and when one of the FM modulation frequencies increases for a positive input,
The other acts to decrease. Therefore, the final
The difference frequency (f1-f2), which is the FM modulation output, is actually the sum frequency of each.

[Problems to be Solved by the Invention] In the above-described FM modulators 10 conventionally used, since all are processed in a pure analog manner, particularly: (1) Non-linearity of input voltage versus output frequency ( 2) Higher-order distortion, especially second-order distortion, included in the FM modulated output wave. (3) Oscillation frequency stability, especially stability due to temperature characteristics. Absent.

In order to improve these, various adjustments and compensations are required, but sufficient accuracy has not yet been obtained.

In order to solve such a problem, the carrier signal may be digitally modulated by the modulation signal, but in order to do so, it is necessary to perform the digital multiplication processing of the modulation signal and the carrier signal. Since the carrier signal is a sine wave signal or a cosine wave signal in this multiplication output,
In particular, there is a drawback that the structure of the multiplier for multiplying the modulated signal and the carrier signal becomes complicated. If the multiplier can be configured by a logic circuit or the like, the circuit configuration will be easy, and it will be advantageous for IC implementation.

Therefore, the present invention solves such a problem and proposes a digital FM modulator. In particular, when realizing a circuit for performing all FM modulation processing digitally, the digital multiplier is simplified. The main purpose is to make it

One means of such an FM modulator has already been proposed by the present applicant (Japanese Patent Application Nos. 1-88325 and 1-88326).
issue).

[Means for Solving the Problems] In order to solve the above problems, the present invention includes an integrator that integrates a modulation signal, a phase modulator that phase-modulates the integrated output, and generation of a carrier signal. In the integrator, which includes an analog / digital converter, is input as an analog signal, and the modulated signal converted into a digital signal by the analog / digital converter is integrated, and in the carrier signal generator, the reference oscillation output is output. Are sequentially shifted by π / 2, and four types of digital carrier signals are formed. The phase modulator converts the integrated output modulation signal into a digital modulation signal, and the digital modulation signal and the carrier signal are combined. When being multiplied by the digital multiplier, a pair of digital modulation signals having a quadrature phase relationship as the above modulation signal. When converted to are those, wherein a pair of digital multipliers are used, that the sum output of the multiplication output is adapted to be used as an FM modulated output.

[Operation] The digital FM modulator 10 is configured by the integrator 20 that integrates the modulation signal, the phase modulator 30 that phase-modulates the integrated output, and the carrier signal generator 50. The modulation signal is a video signal or the like.

Referring to FIG. 1 and FIG. 8, in the integrator 20,
The AD converter 22 integrates the analog-to-digital converted modulation signal. Then, the modulated signal which is the integrated output of the integrator 20 is converted into the first and second digital modulated signals having the quadrature phase relationship in the phase modulator 30. This phase modulator 30 includes a first phase modulator 30 having a quadrature phase relationship.
And a second digital carrier signal is provided.

Then, the first digital modulated signal and the first digital carrier signal are supplied to the multiplier 35, and the second digital modulated signal and the second digital carrier signal are supplied to the multiplier 36, respectively. The respective digital multiplication outputs are added. By adding the digital multiplication outputs, an output in which only the phase of the second digital carrier signal is modulated is obtained.

This output changes the phase of the digital carrier signal every cycle according to the amplitude of the input digital modulated signal, and this is equivalent to the result that the digital carrier signal is frequency-modulated by the digital modulated signal. become. That is, the FM modulation output is obtained at the output terminal 42.

Embodiment An example of the digital FM modulator according to the present invention will be described below.
A detailed description will be given with reference to FIG.

The digital FM modulator 10 includes an integrator 20 that integrates an input signal supplied to a terminal 21, a phase modulator 30 that phase-modulates the integrated output, and a carrier signal generator 50. The input signal may be an analog video signal.

Since the processing of this FM modulator 10 is purely digital,
The integrator 20 is also configured to be digitally processed. Therefore, the integrator 20 has an A / D converter 22, and converts the video signal supplied to the terminal 21 into a digital signal having a predetermined number of bits, in this example, 8 bits.

The digitized video signal is added by the adder 24 to the digital video signal output from the register 23 one clock before.

The adder 24 is a 2n-bit (n is an integer) adder, and in this example, n = 5. Therefore, the 8-bit digital video signal is input to the lower 8 bits, and the remaining 2 bits are input to 0. Then, this addition output (10-bit configuration) is input to the register 23 again.

In this way, by sequentially adding the digital video signals one clock before, the integrated digital video signal is obtained from the register 23.

The clock CK used in the A / D converter 22 and the register 23 is the digital carrier signal CK0 (the third phase) of the reference phase among the digital carrier signals output from the shift register 52 provided in the carrier signal generator 50. Figure B) is used.

Reference numeral 51 is a reference oscillator composed of a crystal oscillator or the like, and in this example, since a video signal whose time axis is extended 15 times is used, its clock frequency is 2.5 × 4.
= 10.0 MHz is used. Reference numeral 25 is an input terminal of the clock CK0.

A clear signal is supplied to a terminal 26 provided in connection with the register 23, whereby the contents of the register 23 are initialized.

This also takes into account that a video signal from which a DC component is lost is supplied to the terminal 21. Even when there is no DC component, once the contents of the register 23 are reset once every horizontal cycle in the sync chip portion of the horizontal synchronization signal, the initial value of the register 23 is fixed, so the integrated value at the sync chip level Can be fixed.

The digitally integrated video signal is supplied to the phase modulator 30.

The phase modulator 30 is provided with a pair of waveform conversion ROMs 32 and 33, and the input digital video signal is converted into two digital video signals having a quadrature relationship with each other.

That is, the amplitude values (digital signals) corresponding to the cosine wave and the sine wave as shown in FIG. 2 are stored in the respective waveform conversion ROMs 32 and 33, and the amplitude values corresponding to the level of the input digital video signal are simultaneously referred to. Then, two digital video signals {cosine digital video signal cos (c) and sine digital video signal sin (c)} which are orthogonal to each other are output. Here, the phase c corresponds to the level of the input digital video signal.

The cosine digital video signal cos (c) and the sine digital video signal sin (c) both function as digital modulation signals as described later.

The cosine digital video signal cos (c) and the sine digital video signal sin (c) are composed of first and second 2n-bit signals.
Are supplied to the digital multipliers 35, 36 of. First and second
The digital multipliers 35 and 36 are supplied with the digital carrier signal CK in addition to the digital video signal.

50 is a carrier signal generator as described above,
In this example, the reference clock signal 4CK from the reference oscillator 51
(FIG. 3A) is supplied to the 4-bit shift register 52 to form four digital carrier signals CK0 to CK3 (B to E in FIG. 3) whose phases are sequentially shifted by π / 2.

Assuming that the carrier signal having the reference phase is CK0, by using four carrier signals CK0 to CK3 which are shifted by π / 2, 2π / 2, 3π / 2 from this, the state 1
It is possible to deal with a signal that repeatedly changes in the order of → state 0 → state 1 → state 0.

A signal that repeatedly changes is a carrier signal when a digital carrier signal is converted into an analog signal, and the above-described states are 0, π / 2, 2π of a sine wave signal sin (2πfct) having the same frequency as the carrier signal CK. It is possible to correspond to the amplitude value in the phase of / 2, 3π / 2. Therefore,
One sine wave signal sin (2πfct) can be expressed by the four digital carrier signals CK0 to CK3, and the amplitude values at that time are 0, 1, 0 and -1, respectively.

In the following description, four digital carrier signals CK0
~ CK3 is referred to as a sine digital carrier signal sin (2πfct).

Now, the four digital carrier signals CK0 to CK3 forming the sine digital carrier signal sin (2πfct) are supplied to the 1-clock delay unit 31 formed of a register,
Each is delayed by one clock. Since this delay amount corresponds to π / 2 in terms of phase, by passing through this 1-clock delay unit 31, the cosine digital carrier signal CKc {=
-Cos (2πfct)} is output.

Due to the presence of this one-clock delay device 31, the carrier signal CK
Is the first and second digital carrier signals {sine digital carrier signal sin (2πfct) which have a quadrature relationship.
And the cosine digital carrier signal −cos (2πfct)}.

The sine digital carrier signal sin (2πfct) and the cosine digital video signal cos (c) are supplied to the first digital multiplier 35, and the cosine digital carrier signal −cos
(2πfct) and the sine digital video signal sin (c) are supplied to the second digital multiplier 36.

 The multiplication operation of the digital multiplier 35 will be described.

By using the four digital carrier signals CK0 to CK3 as the sine digital carrier signals,
To realize two states, for example, state 0 (0 phase and 2π
/ 2 phase 2), the cosine digital video signal cos
Multiplication in which 0 is output regardless of the contents of bit Di (i = 0 to 8) in (c), is output as it is in state 1, and is inverted and output in state −1. It is sufficient to realize the operation.

Such a multiplication operation can be constituted by a simple logic circuit.

FIG. 4 shows an example thereof, and the 10-bit digital multiplier 35 is composed of 10 NAND circuits 35A and exclusive OR circuits 35B and 35C.

Each of the bits D0 to D9 forming the cosine digital video signal is supplied to the corresponding NAND circuit 35A, and two digital carrier signals CK0 and CK2 of the sine digital carrier signals are commonly supplied to the NAND circuit 35A. .

The NAND output is supplied to the respective exclusive OR circuits 35B, and the digital carrier signal CK3 is commonly supplied to these exclusive OR circuits 35B except for the exclusive OR circuit 35C to which the NAND output for the most significant bit is supplied.

Since the most significant bit D9 is a sign bit, an inverted signal of the digital carrier signal CK1 is supplied to the exclusive OR circuit 35C corresponding thereto.

The truth table for this configuration is shown in FIG. Figure A
Indicates the input / output relationship between bits D0 to D8. The upper row is when bits D0 to D8 are "L", and the lower row is when it is "H". In state 0, "L"
(This level is set to 0), the input is output as it is in state 1, and the inverted output is output in state -1.

Similarly, FIG. 9B is a truth table for the bit D9, where “L” is minus (−) and “H” is plus (+).
Shall be represented.

When considering an analog carrier signal (sine wave signal), its zero point is set to “0 (= 1000000000)”, the minimum value is “−512 (= 0000000000)”, and the maximum value is “+511”.
(= 1111111111) ", the multiplication output with the bit D9 in the state 0 is 0, so (0000000000)
Instead, it should be (1000000000). The logical configuration has been made so.

Further, as is clear from FIG. 9B, the sign bit D9 is output as it is in the state 1, and is inverted and output in the state -1.

Since the digital multiplier 36 has the same configuration, its description is omitted.

If the digital multipliers 35 and 36 are configured as described above,
With a relatively simple structure, it is possible to obtain digital multiplication outputs of the sine signal and the cosine signal, respectively. Therefore, sin (2πfct) · cos (c) (1) is output from the first digital multiplier 35.

 The second digital multiplier 36 outputs -cos (2πfct) · sin (c) (2).

The respective multiplication outputs are added by the digital adder 39 via the buffer registers 37, 38, and subtracted in this example. The output of the digital adder 39 is as follows.

sin (2πfct) ・ cos (c) ＋ cos (2πfct) ・ sin
(C) = cos (2πfct + c) (3) Thus, the cosine digital carrier signal cos (2πf
The cosine digital carrier signal cos (2πfct + c) whose phase is delayed by c with respect to ct) is output. This cosine digital carrier signal cos (2πfct + c) is the D / A converter 4
When it is 0, it is converted into an analog signal, which is band-limited by the bandpass filter 41.

In the cosine digital carrier signal cos (2πfct + c) obtained at the output terminal 42 in this manner, the phase of the digital carrier signal is increased at high speed in accordance with the amplitude of the input video signal with respect to this digital carrier signal every cycle. (1 / fc time) can be changed, and as a result, FM modulation can be performed.

The band characteristic of the bandpass filter 41 is shown in FIG. It is desirable to select the band characteristics so that the attenuation is 1 / (2 ⁿ -1) or more at ± 4fo around the carrier frequency fo and the frequency in the range of ± 1 / 2fo can be sufficiently passed. .

Further, the phase characteristic of the bandpass filter 41 is selected so that the phase delay characteristic maintains a linear characteristic with respect to the frequency within a frequency range of ± 1/2 fo centering on the carrier frequency fo as shown in FIG. Is desirable.

By the way, the phase resolutions of the sine digital carrier signal sin (2πfct) and the cosine digital carrier signal −cos (2πfct) input to the digital multipliers 35 and 36 described above depend on the bit configurations of the digital multipliers 35 and 36, respectively. For example, if each of the digital multipliers 35 and 36 has a 10-bit configuration, the phase resolution is 0.35 ° (= 360 ° / 1023).

The relationship between the minimum phase change dc per unit time and the frequency change df is expressed by the following equation.

df = (1 / 2π) (dc / dt) (4) Therefore, the relationship between the minimum phase change dc per unit time and the maximum frequency shift Δf is as follows.

Δf = df (2 ⁸ -1) (5) Therefore, when dc = 6.14 × 10 ^-3 radians (6) dt = 400nsec (= 1 / fc = 2.5MHz) (7), Δf = 0.623MHz (8) df = 2443Hz (9), and the input voltage and output frequency are completely linear. That is, it has a linear characteristic.

In the above example, the carrier frequency fc is set to 2.5 MHz, this frequency is applied to the sync tip level of the video signal, and the maximum frequency shift Δf is set to 0.623 MHz, so that FM modulation is performed in a direction to increase the frequency. It is.

 FIG. 8 shows another example of the present invention.

In the figure, the sine digital carrier signal sin (2
πfct) is supplied to the attenuator 44 and its input level is 1
It is attenuated to / (2 ⁿ -1) and then supplied to the third digital multiplier 45. n is the number of bits and is 5 in this example.
Bit. The lower 5 bits of the cosine digital video signal cos (c) are further supplied to the third digital multiplier 45.

In the third digital multiplier 45, the amplitude of the cosine digital video signal cos (c) is modulated by the sine digital carrier signal and then supplied to the digital adder 39 via the buffer register 46.

Similarly, cosine digital carrier signal −cos (2πfc
When t) is supplied to the attenuator 47, its input level is attenuated to 1 / (2 ⁿ −1) and then supplied to the fourth digital multiplier 48.

The lower 5 bits of the sine digital video signal sin (c) are supplied to the fourth digital multiplier 48. Then, the upper 5 bits of the sine digital video signal sin (c) are supplied to the second digital multiplier 36. Then, the respective multiplication outputs are supplied to the digital adder 39 via the buffer register 49.

When the maximum amplitude of the digital carrier signal is decomposed into n bits, that is, 5 bits, the size per bit is 1 / (2 ⁵ −
It becomes 1). Therefore, the attenuator 44 and the third digital multiplier 45 decompose the minimum resolution amplitude of the first digital multiplier 35 into 5 bits. as a result,
The pair of digital multipliers 35 and 45 and the attenuator 44 function as a 2n-bit digital multiplier.

Therefore, according to this configuration, a 5-bit digital multiplier can be used, and the price thereof is very low.

Both the examples in Fig. 1 and Fig. 8 are sine ROM33 and cosine ROM.
This is a case where sine and cosine digital video signals are obtained by using each of 32. Since the sine signal and the cosine signal have a quadrature phase relationship, the sine and cosine digital video signals can be generated by using only one of the ROMs.

The present invention is not limited to the above embodiment. For example, sine and cosine signals have a 1/4 phase
Since the signals are exactly the same just by shifting the period, even if the sine wave signal and the cosine wave signal are exchanged in the above-described embodiment, the same effect can be obtained.

Further, the digital multipliers 35, 36, 45 and 48 may be configured to multiply sine waves and cosine waves.

In the digital multiplier 39, not the subtraction process,
An addition process may be performed.

[Effects of the Invention] As described above, according to the present invention, first and second digital modulated signals having a quadrature phase relationship and first and second digital carrier signals having a quadrature phase relationship are also provided. Is multiplied by each other, and the output obtained by adding the respective digital multiplication outputs is used as the FM modulation output.

According to this, one of four types of digital carrier signals
Since FM modulation is performed by digital processing, in which calculation is performed for each cycle, it is possible to realize an FM modulator with excellent linear characteristics, high-order distortion, and good temperature characteristics. Therefore, there is a practical benefit of providing a highly reliable FM modulator.

In addition, the phase of the digital carrier signal is 0, π / 2, 3π / 2
Since it is defined as a timing pulse corresponding to, and is used instead of the sine carrier signal, it has a practical advantage that the digital multiplier can be configured by a simple logic circuit. I c
It is easy to convert.

[Brief description of drawings]

1 and 8 are block diagrams each showing an example of an FM modulator according to the present invention, FIG. 2 is a diagram showing data contents of ROM, FIG. 3 is a waveform diagram of a digital carrier signal, and FIG. Connection diagram of digital multiplier, FIG. 5 is a diagram of its truth table, FIG. 6 is a band characteristic diagram of a bandpass filter, FIG. 7 is its phase characteristic diagram, and FIGS. 9 and 10 are conventional FMs. It is a systematic diagram of a modulator. 10 …… FM modulator 20 …… Integrator 30 …… Phase modulator 32,33 …… Sine and cosine ROM 35,36,45,48 …… Digital multiplier 50 …… Carrier signal generator 52 …… Shift Registers 37,38,46,49 …… Buffer registers

Claims (1)

(57) [Claims] 1. An integrator for integrating a modulation signal, a phase modulator for phase-modulating the integrated output thereof, and a carrier signal generator, wherein the integrator includes an analog-digital converter,
The modulated signal, which is input as an analog signal and converted into a digital signal by the analog / digital converter, is integrated. In the carrier signal generator, the four types of digital carriers whose reference oscillation outputs are sequentially shifted in phase by π / 2 A signal is formed, and in the phase modulator, the modulated signal which is an integrated output is converted into a digital modulated signal, and when this digital modulated signal and the carrier signal are multiplied in a digital multiplier, the quadrature signal is used as the modulated signal. When converted into a pair of digital modulation signals having a phase relationship, a pair of digital multipliers are used, and an addition output of these multiplication outputs is used as an FM modulation output. FM modulator.