JPH02190063A - Digital quadruple phase psk modulator - Google Patents

Abstract

PURPOSE:To avoid phase shift and the influence of noise by storing a digital waveform data for one cycle of a carrier at a prescribed frequency, shifting sequentially the waveform data, acquiring four pieces of waveform data with different phases, selecting the four pieces of waveform data in response to a transmission data and converting the selected data into an analog signal. CONSTITUTION:A modulator is provided with a memory section 10 storing the waveform data (for one period) of a carrier at a prescribed frequency, a counter section 11 generating repetitively an address reading out the waveform data sequentially and an address generating means composed of a clock generating section 12 or the like. Moreover, a shift register section 13 shifting the waveform data read from the memory section 10, retarding the carrier phase by the waveform data and outputting the waveform data shifting the phase, a multiplexer section 14 selecting the four pieces of waveform data with different phases and a D/A converter section 16 converting the selected waveform data into an analog waveform and modulating the wave into a modulated wave are provided. Thus, no phase shift takes place in the modulated wave and the influence due to noise is prevented.

Description

[Detailed Description of the Invention] [Industrial Field of Application]
Phase 5hift Keying
) The present invention relates to a modulator, and more specifically relates to a novel digital four-phase PSK modulator that eliminates phase shift of modulated waves.

[Conventional Example] Conventionally, this type of four-phase PSK modulator has a configuration shown in FIG. 4, for example.

In this figure, the 4-phase PSK modulator includes a signal generator WX1 that generates a carrier of 1 frequency fc (cos 2πf c-t), and a sin signal that is phase-shifted by π/2 of the carrier.
π/2 phase shifter 2 that outputs 2πfc-t, cos2 tc fc-t and 5in2πfC-t of these carriers
(mutually orthogonal relationships) are multiplied by multipliers 3 and 4 to perform two-phase modulation using manual data, and those two-phase PSK.
An adder 5 for adding modulated waves is provided.

By the way, the modulated wave obtained by the above four-phase PSK modulator is S (t) = cos (2x f c-t + ki・7
C/2). Note that ki is 0, 1,
It is a coefficient of 2°3. In other words, as can be seen from the signal space diagram shown in Figure 5, the modulated wave can take four different phase states: 0 phase, π/2 phase, π phase, and (3/2) π phase of the carrier. The above four-phase PSK modulator is a combination of two digital signals (data 1, data 2), (0,0), (0°1), (1,1), (1,
0) can be sent.

[Problems to be Solved by the Invention] However, the above-mentioned four-phase PSK modulator is composed of an analog circuit, and modulates the carrier with transmission data,
This is because two two-phase PSK modulated waves are obtained and they are added.

A phase shift inevitably occurs, and it is easily affected by noise. Therefore, on the demodulation side.

This may cause problems when demodulating digital signals from modulated waves, and it may not be possible to demodulate the digital signals accurately.

This invention has been made to address the above-mentioned problems.

The purpose is to provide a digital four-phase PSK modulator that can eliminate phase shifts and the effects of noise.

[Means for Solving the Problems] In order to achieve the object (h), the digital four-phase PSK modulator of the present invention includes a storage means for storing one cycle of a carrier of a predetermined frequency as digital waveform data; address generating means that repeatedly generates addresses for sequentially reading waveform data; shift register means that sequentially shifts the read waveform data to obtain four waveform data having different phases; and a shift register means that sequentially shifts the read waveform data to obtain four waveform data having different phases. The gist of the present invention is that the present invention is provided with a selection means for making a selection, and a D/A conversion means for converting the selected waveform data into an analog signal.

[Function] Since the configuration described in 11- is adopted, if the carrier is a sine wave, the storage means stores one cycle (2π) of the sine wave.
) waveform data is stored. Then, when the waveform data for one cycle is read out repeatedly, it is sequentially shifted by the shift register means, and the O phase is shifted to π72.
Four waveform data with a phase delay, a π phase delay, and a (3/2) π phase delay are sequentially output.

At this time, the selection means selects the digital signal ((0,0) of the transmission data (data 1, data 2).

(0,1), (1,1), (1,0)), the waveform data of these four carriers with different phases are selected,
Furthermore, the selected waveform data is converted into an analog signal in the A/I conversion means. In other words, the analog signal is a modulated wave whose carrier is modulated by a digital signal, and the modulated wave has a digital signal ((0
,0), (0,1), (1,1), (1,0)). Therefore, according to the digital four-phase PSK modulator, the combination of two digital signals, (0,0
), (0°1), (1,1), (1,0) can be transmitted.

[Example] Hereinafter, one embodiment of the present invention will be described based on the drawings.

In FIG. 1, the digital four-phase PSK modulator includes a memory (FROM) section 10 that stores waveform data (for one cycle) of a carrier (sine wave) of a predetermined frequency (fc), and Address generation means includes a counter section 11 that repeatedly generates addresses to be sequentially read out, a clock generation section 12 that generates a clock for the counter section 11, and the like; The carrier phase is 01(1/2)π.

A shift register unit 13 that outputs waveform data delayed by π, (3/2)π and shifted in phase, a multiplexer (MPX) unit 14 that selects four waveform data with different phases, and a A data section 15 that outputs digital signals of selection control and transmission data (data 1 and data 2), and a D/A conversion section that converts the waveform data selected by the multiplexer section 14 into an analog waveform and makes it a modulated wave. 16 are provided.

Here, the waveform data stored in the memory section IO is as follows:
For example, as shown in FIG. 2, one period of a carrier (sine wave) is divided into 32, and the carrier data (for example, 8 bits) at the 32 division points is obtained.

In this case, the clock frequency generated by the clock generating section 12 is fcX32 (fc is the carrier frequency), and the output (address) of the counter section 11 is, for example, 5 bits. The shift register section 13 also includes the memory section 10.
Shift the waveform data read out in 8 clocks,
A first D-FF (D-type flip-flop) circuit 13a that sequentially outputs data, and a second D-FF (D-type flip-flop) circuit 13a that shifts the output waveform data of the first D-FF circuit 13a every 8 clocks and sequentially outputs the data. D-FF circuit 13b and this second
A third D-FF circuit 13 that shifts the output waveform data of the D-FF circuit 13b in 8 clocks and sequentially outputs the same.
c, and a fourth D-FF circuit that shifts the output waveform data of the third D-FF circuit 13c every 8 clocks and sequentially outputs the data.
-FF circuit 13d.

Each D-FF circuit 13a, 13b, 13c,
A clock signal from the same clock generating section 12 as the counter section 11 is input to 13d.

Then, as shown in FIG. 3(a), in the first shift register section 13a, the waveform data (8 bits) read out from the memory section 10 is transferred every 8 clocks (π7
new waveform data is shifted every 2 minutes), and new waveform data is shifted over the next 8 clocks, and the original waveform data is sequentially output. At this time, FIGS. 3(b) to (d)
As shown in , in the second D-FF circuit 13b, the waveform data (waveform data of the π72 delayed multiplier carrier) output from the first D-FF circuit 13a is
The waveform data is shifted in 8 clocks, and new waveform data is shifted in the next 8 clocks, and the original waveform data is sequentially output. In addition, the second D-
Similarly to the FF circuit 13b, in the third D-) lower circuit 13c, the waveform data shifted to the first υ-FF circuit 13a is shifted with a delay of π, and is transferred in the next 8 clocks. The shifted waveform data is sequentially output. Further, in the fourth D-FF circuit 13d, the waveform data shifted to the first D-FF circuit 13a is shifted with a delay of (3/2)π, and the waveform data is shifted to the next 8
The shifted waveform data is sequentially output by the clock.

In this way, the first D-FF circuit 13a obtains waveform data of a carrier with phase O, and the second D-FF circuit 13b obtains waveform data of a carrier with a phase delay of π/2, The third D-FF circuit 13c obtains carrier waveform data with a phase delay of π, and the fourth υ-FF circuit 13d
Waveform data of a carrier whose phase is delayed by (3/2) π is obtained.

Then, in the multiplexer section 14, the waveform data of the four carriers having different phases are selected based on data 1 and data 2 (modulated signals) of the data section 15.

Therefore, when data 1 and data 2 are (0, 0), waveform data with phase O is selected, and when data 1 and data 2 are (0, 1), waveform data with a phase delay of π/2 is selected, and (1 ,1
), select waveform data with a phase delay of π, and select (1,
0), it is determined that waveform data with a phase delay of (3/2) π is selected. Thereby, waveform data of four different phases can be selected according to data 1 and data 2 from the data section 15, and the D/A converter 16
The selected waveform data is converted into an analog signal. What about that analog signal?

The waveform data carrier (
The frequency fc) becomes a modulated wave modulated by data 1 and data 2. Therefore, the analog signal includes the digital signals of data 1 and data 2, and a combination of the two digital signals can be transmitted.

Note that the shift register section 13 of the above embodiment is a D-FF
Although the circuit is connected in series, the carrier waveform data can be divided into O phase, π/2 phase, π phase, (3/2)
The D-Fl'' circuit with a π phase delay may be configured with four circuits.

[Effects of the Invention] As explained above, the digital four-phase PSK of the present invention
According to the modulator, when modulating the carrier with the transmitted data, it is done entirely by digital circuits without using analog circuits, so there is no phase shift in the modulated waves, and the effects of noise are prevented. be able to.

[Brief explanation of the drawing]

FIG. 1 shows a digital four-phase PS showing an embodiment of the present invention.
A schematic block diagram of the K modulator, FIG. 211g, and FIG.
The figure is a schematic block diagram of a conventional 4-phase PSK modulator.
The figure is a signal space diagram in a four-phase PSK modulation system. In the figure, lO is a memory (PHOM) section, 11 is a counter section, 12 is a clock generation section (fcX32 clock), and I3
1 is a shift register section, 13a is a first D-FF circuit, 1
3b is the second D-FF circuit, 13c is the third D-FF circuit, 13d is the fourth D-lower circuit, 14 is the multiplexer (MPX) section, 15 is the data section, 16 is the D/A conversion Department. Patent Applicant Fujitsu General Co., Ltd. Agent Patent Attorney Takuya Ohara

Claims (2)

[Claims] (1) Storage means for storing one cycle of a carrier of a predetermined frequency as digital waveform data; Address generation means for repeatedly generating an address for sequentially reading out the waveform data; and Sequentially shifting the read waveform data to create different phases. The carrier comprises a shift register means for obtaining data of four waveforms, a selection means for selecting the four waveform data according to the transmission data, and a D/A conversion means for converting the selected waveform data into an analog signal. A digital four-phase PSK modulator, characterized in that a modulated wave is obtained by modulating with the transmission data. (2) The shift register means is configured to control 1/1/2 of the carrier.
A first D-FF circuit that shifts and sequentially outputs waveform data for four cycles; and a second D-FF circuit that shifts and sequentially outputs the output waveform data of the first D-FF circuit.
A third D-FF circuit that shifts the output waveform data of the FF circuit and the second D-FF circuit and sequentially outputs the output waveform data of the third D-FF circuit, and a fourth D-FF circuit that sequentially outputs the 0 phase, (1/2) π phase, π phase, and (3
/2) Claim (1) wherein waveform data of π phase is obtained.
) Digital 4-phase PSK modulator.