JPH0998027A - Digital clock generation device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To heighten the frequency range and to reduce spurious waves. SOLUTION: The digitizing signal sin (2π fct) sent from a reference signal generator 50 undergoes phase modulation via a phase modulator 30 based on Δf that is set at a terminal 21 of an integrator 20. This modulation output is outputted to the terminals 44 and 43 as the clock signals of frequency fc ±▵f. That is, cos (C) and sin (C) which are produced by C corresponding to the set ▵f are digitally multiplied by sin (2π fct) and -cos (2π fct) from a reference signal by the multipliers 35 and 36 and then added together at an OR gate 39'. Thus a modulated signal cos (2π fct+C) is obtained and outputted. The spurious waves caused by a cos ROM 32 can be reduced when a complement of +1 sent from an IDR 46 undergoes the phase updating of the ROM 32 as a 2CK via a correction circuit 45 against a reference cycle CK.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generator capable of obtaining an arbitrary clock frequency within a predetermined frequency range with respect to a reference signal. More specifically, the main part of the clock generator is of pure digital type. The present invention relates to a configured digital clock generator.

[0002]

2. Description of the Related Art Conventionally, as a clock generator for obtaining a certain frequency (including a clock frequency), a reference frequency is multiplied or divided to obtain it, or a phase locked loop (PLL) is used. I am asking for it.

FIG. 16 is an example of the former, showing an example of a clock generator by a combination of multiplication and division of a reference frequency. In FIG. 16, the reference clock output from the crystal oscillator 1 is supplied to the resonance circuit 3 via the buffer 2. The resonance circuit 3 functions as a frequency multiplication circuit, and is composed of a pair of capacitors 3a and 3b and a primary coil 4a of the resonance transformer 4 connected in series, and the reference frequency of the reference clock is multiplied and output. . The multiplied reference signal is supplied to the comparator 5 through the secondary coil 4b of the resonance transformer 4 and binarized. Then, finally, the frequency divider 6 divides the frequency to a predetermined clock frequency, and the output terminal 7 outputs a clock signal having a predetermined frequency.

FIG. 17 shows an example of the latter clock generator, in which the reference clock output from the crystal oscillator 11 is supplied to the PLL 18. PLL1
Reference numeral 8 is composed of a variable oscillator (VCO) 13, a frequency divider 14 that divides the frequency of the frequency, and a phase comparator 12. The reference clock and the frequency division output are phase-compared, and the variable output uses the comparison output. The oscillation frequency of 13 is controlled. PLL18
The output clock output from the
The value is digitized and the output is frequency-divided by the frequency divider 16 to a predetermined ratio, whereby a clock signal of a predetermined frequency is output to the output terminal 17. This clock generator is applied as a generator of a reference clock used when recording a video signal or performing wireless communication. FIG.
In the clock generator shown in FIG. 3, the frequency selection circuit composed of the resonance circuit 3 includes capacitors 3a and 3b and a coil 4a.
Since the filter is used, the frequency selection function is not sufficient, and there is a drawback that the waveform of the output signal is accompanied by jitter. In the clock generator shown in FIG. 17, depending on the performance of the variable oscillator 13 and the loop filter of the PLL 18,
It becomes difficult to stably generate the generation frequency in a wide range.

In order to solve such a problem, a clock generator proposed by the present applicant (Japanese Patent Laid-Open No. 2-312).
No. 319 and Japanese Patent Application Laid-Open No. 2-312320), a frequency setting signal is used as a reference signal (clock signal).
The frequency may be digitally modulated, but in order to do so, it is necessary to perform digital multiplication processing of the setting signal and the reference signal.

Further, in such a clock generator, if the multiplier can be configured by a simple logic circuit or the like, the circuit configuration will be easy and it will be advantageous for IC implementation. The digital clock generator (Japanese Patent Laid-Open No. 1-197776) proposed by the present applicant has solved such a problem. However, even in the above proposal, there is a problem in spurious characteristics that can be used for wireless communication, and since the addition time in the high-speed addition circuit is long, the increase in the frequency range that can be generated is limited.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and the clock generator which operates digitally, and the spurious magnitude improvement and the high frequency range which can be generated. It is an object of the present invention to provide the clock generation device including the conversion means.

[0008]

According to a first aspect of the invention, an integrator for integrating a setting signal for setting a clock frequency (Δf), a generator for a reference signal (fc), and an integrator for the integrator are provided. In a digital clock generator having a phase modulator for phase-modulating an output as an input, the reference signal generator forms a digital reference signal whose phase is sequentially shifted by π / 2 as a reference oscillation output, and the integration is performed. In the converter, the integrated output signal is converted into a digital setting signal, and in the phase modulator, the digital setting signal is converted into a component of the setting phase signal in a periodic function having a quadrature phase relationship with each other by the digital ROM means, and the digital reference signal is converted. After the signal is converted by the π / 2 phase delay means into the components of the digital reference phase signal having the quadrature relationship with each other, these two components are mutually converted. After being multiplied in a multiplier and the outputs of the multipliers are logically summed with each other,
The D / A converter forms a discrete analog signal, and the D / A
The output of the converter is the output of the true analog signal converted by passing through the bandpass filter, and the output of the reference signal (f
It is designed to be used as a clock signal having a predetermined frequency (fc ± Δf) determined by the clock frequency (Δf) set as c).

According to a second aspect of the invention, in the first aspect of the invention, the periodic function of the digital ROM means forms a sine or cosine function, and the maximum positive or negative amplitude is 1 with respect to full scale. Formed with a step difference,
A complement correction circuit is provided in front of the D / A converter to improve spurious characteristics.

According to a third aspect of the present invention, in the first aspect of the present invention, the periodic function of the digital ROM means forms a sine or cosine function, and the frequency of the periodic function formed with respect to the reference cycle CK is generated. In this configuration, the necessary phase shift update is generated in 2CK cycles, and the spurious based on the reference cycle is moved outside the frequency generation in principle.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION The operation principle of a digital clock generator according to the present invention will be described below with reference to FIGS.
Will be described in detail with reference to. In FIG. 7, the digital clock generator comprises an integrator 20 that integrates the setting signal supplied to the terminal 21, a phase modulator 30 that phase-modulates the integrated output, and a reference signal generator 50. It The setting signal is used to determine the frequency of the clock signal to be obtained at the output terminal 43. By setting the number of bits (content of bit data) of the clock signal as will be described later, a clock signal of a desired single frequency can be obtained. can get.
However, the frequency range of the output clock signal is within the range of the predetermined frequency Δf. The digital setting signal (in this example, an 8-bit digital signal) supplied to the terminal 21 is added by the adder 24 to the setting signal output from the register 23 one clock before. Adder 24
Is an adder having a 2n-bit (n is an integer) configuration, and in this example, n = 5. Therefore, the 8-bit setting signal is input to the lower 8 bits and the remaining 2 bits are input to 0. Then, this addition output (10-bit configuration) is input to the register 23 again. in this way,
By sequentially adding the setting signals one clock before,
The integrated digital setting signal is obtained from the register 23.

The clock CK ₀ used in the register 23 is one of the digital reference signals output from the shift register 52 provided in the reference signal generator 50.
The reference phase digital reference signal CK ₀ (FIG. 9B) is used. The clock CK ₀ is also supplied to the terminal 25.
The terminal 26 is a clear terminal for initial setting with respect to the register 23. Reference numeral 51 is a reference oscillator composed of a crystal oscillator or the like, and in this example, 2.5 MHz × 4 = 10.0 MHz is used. The setting signal digitally integrated and output from the register 23 as described above is the phase modulator 3
0 is supplied.

The phase modulator 30 includes a pair of waveform conversion ROs.
M32 and M33 are provided, and the input digital setting signals are converted into two digital setting signals having a quadrature relationship with each other. That is, each waveform conversion ROM
Amplitude values (digital signals) corresponding to the cosine wave and the sine wave as shown in FIG. 8 are stored in 32 and 33, and the amplitude values corresponding to the contents of the bit data of the input digital setting signal are simultaneously referred to, Two digital setting phase signal components in a periodic function that are orthogonal to each other {cosine digital setting signal cos (C) and sine digital setting signal s
in (C)} is output. Phase C corresponds to the content of the bit data of the input digital setting signal.

The cosine digital setting phase signal cos (C) and the sine digital setting phase signal sin (C) are supplied to the first and second digital multipliers 35 and 36 having a 2n-bit structure. First and second digital multipliers 35, 3
A digital reference signal CK is supplied to 6 in addition to the digital setting signal. In this example, the oscillation signal 4CK (FIG. 9A) from the reference oscillator 51 is supplied to the 4-bit shift register 52, and the phase is sequentially shifted by π / 2.
Two digital reference signals CK _{0 to} CK ₃ (Fig. 9 (B)-
(E)) is formed.

A digital reference signal having a reference phase is C
If K ₀ , then π / 2, 2π / 2,
Four digital reference signals CK ₀ ~ shifted by 3π / 2
By using CK ₃ , it is possible to correspond to a multiplication value that repeatedly changes in the order of state 1 → state 0 → state (−1) → state 0. The signal that repeatedly changes is a reference signal when a digital reference signal is converted into an analog signal, and the above-mentioned states are 0, π / 2, and sine wave signal sin (2πfct) of the same frequency as the reference signal CK. 2π /
It is possible to correspond to the amplitude value in the phase of 2,3π / 2. Therefore, four digital reference signals CK ₀
~ One sine wave signal sin (2πfct) can be expressed by CK ₃ , and the amplitude values at that time are 0, 1, (-1), respectively.
Becomes In the following description, four digital reference signals C
K _{0 to} CK ₃ are sine digital reference signals sin (2πfct)
Say.

Now, the sine digital reference signal sin (2π
fct) four digital reference signals CK _{0 to} CK
₃ is supplied to a 1-clock delay unit 31 composed of a register, and each is delayed by 1 clock. Since this delay amount corresponds to π / 2 in terms of phase, the cosine digital reference signal CKc {= − cos (2πfct)} is output by passing through this 1-clock delay unit 31. Due to the presence of the one-clock delay unit 31, the reference signal CK is a component of the first and second digital reference phase signals in the periodic function of the quadrature phase relation {sinusoidal digital reference signal sin (2
πfct) and cosine digital reference signal − cos (2πfct)}
It has been converted to.

Sine digital reference signal sin (2πfct)
And the cosine digital setting signal cos (C) are supplied to the first digital multiplier 35, and the cosine digital reference signal −
cos (2πfct) and sine digital setting signal sin (C)
Are supplied to the second digital multiplier 36. The multiplication operation of the digital multiplier 35 will be described. Four digital reference signals CK _{0 to} C as sine digital reference signals
In order to realize the above-mentioned four states by using K ₃ , for example, in the state 0 (0 phase and 2π / 2 phases), bit D of the cosine digital setting signal cos (C) is used.
0 (L level) is output regardless of the contents of i (i = 0 to 9), Di is output as it is in the state 1, and the Di bit is logically inverted in the state (-1). It suffices to realize a multiplication operation that is output as

Such a multiplication operation can be configured by a simple logic circuit. FIG. 10 shows an example thereof, and the 10-bit digital multiplier 35 includes 10 NAND circuits 35A.
And exclusive OR circuits 35B and 35C. Bit D ₀ constituting the cosine digital setting signal
Each of D ₉ to D ₉ is supplied to the corresponding NAND circuit 35A, and two digital reference signals CK ₀ and CK _{2 of} the sine digital reference signals are commonly supplied to the NAND circuit 35A. NAND output is supplied to the exclusive OR circuit 35B each, these except for exclusive OR circuit 35C that NAND output is supplied for the most significant bit, a digital reference signal CK ₃ is commonly supplied. Since the most significant bit D ₉ is the sign bit,
In the exclusive OR circuit 35C corresponding to this,
An inverted signal of the digital reference signal CK ₁ is supplied.

The truth table in this configuration is shown in FIG. FIG. 11A shows the input / output relationship of bits D ₀ to D ₈ . The upper row is when bits D ₀ to D ₈ are "L", and the lower row is when it is "H". In state 0, “L” (this level is 0) is output, in state 1, the input is output as it is, and the state (−
In 1), it is inverted and output. Similarly, FIG.
A truth table for bits D _9, "L" is minus (-), and it is assumed that "H" represents a plus (+) polarity. Then, when an analog reference signal (sine wave signal) is considered, its zero point is set to “0 (= 100000000
0) ”, and the minimum value is“ −512 (= 0000000000).
00) ”and the maximum value is“ +511 (= 111111111111)
1) ”, the multiplication output with the bit D _{9 in the} state 0 is 0. Therefore, it is necessary to set it to (1000000000) instead of (0000000000). The logical configuration has been made so. Also,
As is clear from FIG. 11 (B), the sign bit D ₉ is output as it is in the state 1, and is inverted and output in the state (−1). Since the digital multiplier 36 has the same structure, its description is omitted.

As described above, the digital multipliers 35 and 36
With the above configuration, it is possible to obtain the digital multiplication output of the sine signal and the cosine signal from each with a relatively simple configuration.
Therefore, sin (2πfct) · cos (C) (1) is output from the first digital multiplier 35. The second digital multiplier 36 outputs -cos (2πfct) · sin (C) (2). The output of each multiplication is the buffer register 3
After 7 and 38, addition is performed by the digital adder 39, and subtraction is performed in this example. The output of the digital adder 39 is as follows. sin (2πfct) ・ cos (C) + cos (2πfct) ・ sin (C) = sin (2πfct + C) (3) Thus, the sine digital reference signal sin (2πfct)
Sine digital reference signal whose phase is advanced by C relative to
sin (2πfct + C) is output. This sine digital reference signal sin (2πfct + C) is applied to the D / A converter 40.
Is converted into a discrete analog signal by the band pass filter 41, which is then band-limited by the band pass filter 41 to become a true analog signal.
A value clock signal is output. In this way, in the clock signal obtained at the output terminal 43, the phase of the clock signal can be rapidly changed (1 / fc) according to the amplitude of the input setting signal with respect to each cycle of the digital reference signal. Time), and as a result, FM modulation can be performed. This means that the output clock frequency itself is controlled by the input setting signal.

FIG. 1 shows the band characteristic of the bandpass filter 41.
4 shows. With the carrier frequency f ₀ at the center, the attenuation is 1 / [(2 to the nth power) −1] or more at ± 4f ₀ , and ±
It is desirable that the frequency in the range of 1 / 2f ₀ be selected as a band characteristic that allows sufficient passage. Furthermore, centering on the carrier frequency f ₀ , within a frequency range of ± 1 / 2f ₀ ,
It is desirable to select the phase characteristic of the bandpass filter 41 so that the phase delay characteristic maintains a linear characteristic with respect to frequency as shown in FIG. By the way, the sine digital reference signal input to the digital multipliers 35 and 36 described above.
sin (2πfct) and cosine digital reference signal −cos
The phase resolution of (2πfct) is 0.35 ° (= 360 ° / 1023) when the digital multipliers 35 and 36 each have a 10-bit configuration.

The relationship between the minimum phase change dC per unit time and the frequency change df is expressed by the following equation. df = (1 / 2π) (dC / dt) (4) Therefore, the relationship between the minimum phase change dC per unit time and the maximum frequency shift Δf is given by the following equation from the Nyquist theorem. Δf = df (2 ⁹ −1) (5) Considering that the positive and negative polarities of the phase C can be selected for each cycle, the frequency f that can be generated is f = fc ± Δf (6) That is, it is possible to output a frequency within the range of ± Δf with the reference frequency fc from the reference oscillator 51 as the center frequency. Therefore, when dC = 6.14 × 10 ⁻³ radian (7) dt = 400 nsec (= 1 / fc = 2.5 MHz) (8), Δf = 1.25 MHz (9) df = 2443 Hz (10), and frequencies within the range of the equation (6) are obtained at df intervals. The value of df is determined by the resolution of the digital multipliers 35 and 36.

To sum up the above, as shown in FIG. 13, the clock signal has a frequency within the range of ± Δf centering on the frequency fc of the reference signal. Then, a, b, c,
It is possible to output a single frequency like d, .... The df interval is determined by the number of bits that can be handled by the digital multipliers 35 and 36. When the number of bits is small, the interval of df is wide, and when the number of bits is large, the interval of df is narrow (see FIGS. 12 and 13). . Which frequency is output is selected by the value of the phase C and the polarity, that is, the content of the bit data of the input setting signal. When the bit data is small, a clock signal having a frequency close to the reference signal is selected, and when the bit data is large, a clock signal having a frequency distant from the reference signal is selected.

Incidentally, when all the bit data of the above-mentioned 8-bit input setting signal are "0", C = 0.
Therefore, the reference signal itself is output. An example of the clock signal output when the bit data is small is shown by a solid line in FIGS. Further, as shown in FIGS. 12A and 13A, when the polarity of the phase C is positive, a clock signal having a frequency higher than that of the reference signal is output, and when the polarity is negative, the clock signal has a frequency higher than that of the reference signal. FIG.
As in (B), a signal having a frequency lower than that of the reference signal is output. To change the polarity of the phase C from positive to negative, for example, the digital setting signals sin (C) and cos (C) of the sine and cosine input to the digital multipliers 35 and 36 may be reversed.

As is clear from the above equation, the input voltage of the input setting signal and the output frequency of the reference signal have a completely linear relationship. That is, it has a linear characteristic. Further, since the settable frequency range fc ± Δf is limited by the Nyquist theorem, the following equation is obtained. fc (1-1 / 2) <fc ± Δf <fc (1 + 1/2) Therefore, a clock having a wide range of frequencies can be generated by the selected center frequency fc. Further, since the frequency of the reference signal from the reference oscillator 51 is changed by digital processing as a result, the fluctuation of the frequency depends only on the temperature characteristic of the reference oscillator. Therefore, it is possible to realize a clock generator having good temperature characteristics.

Although the principle of the generation frequency having a good temperature characteristic digitally has been described above, the present invention which is based on this principle and further has a method for improving the frequency of the generation frequency and improving the spurious characteristics will be described in detail below. explain. FIG. 1 shows an embodiment of a clock generator according to the present invention, which is provided with a method for increasing the frequency of generation and improving spurious characteristics.

One of the differences between FIGS. 1 and 7 is the OR gate 39 'in FIG. 1 and the adder 39 in FIG. In FIG. 7, the adder 39 under the 4CK operation condition requires a considerable time during carry-up, and limits the upper limit frequency of the clock generator. On the other hand, according to the mathematical generation principle, the outputs of the buffer registers 37 and 38 must be subjected to addition processing, and as shown in FIG. 7, an adder 39 is required as a means therefor.
It has been found that in the operation of CK ₀ to CK ₃ according to No. 2, even if the adder 39 of FIG. 7 is replaced with the OR gate 39 ′ of FIG. 1, the same logical operation is performed. Is the point for me. The reason why this same logical operation is shown according to FIG.
Since the in and cos inputs are logics in which one of them is multiplied by "0", there is no need for mathematical addition, and as a result, the OR output for each wait bit becomes the same as the adder output. is there. The logical sum synthesis output of the OR gate 39 'is lower in power consumption and IC than the adder described above.
It brings the benefits of the three beats of speeding up and speeding up the movement.

Regarding the spurious, the sine ROM 32,
This is due to the ROM description method of the cosine ROM 33. D / A converter 40 that expects high speed and high frequency like the proposed system
Must be of straight binary type. When handling alternating signals, it must be offset binary.
It is necessary to describe and create M. Figure 3 shows 10-bit D /
This shows an example of using the A converter, in which a straight binary value and an offset binary value are also shown. Since a general D / A converter is configured by the binary input method, it depends on which one defines the "0" line of the alternating signal. In other words, since the positive / negative of the signal is distinguished by the MSB, the '0' line becomes 512 or 511 (straight binary value). In FIG. 3, the positive value is MSB = 1 (H
Since it is defined as (level), the '0' line becomes 512 (in the definition of inverse logic, it becomes 511).

As shown in FIG. 3, when the sine wave function A that maximizes the amplitude utilization rate is described, the positive amplitude is 511.
It becomes a step, and it is necessary to secure 511 steps for the negative amplitude and make it a straight binary value of 1. Distortion occurs when the number of steps is 0, as indicated by the dotted line, which is one of the factors that cause spurious CK ₀ and sine wave periods. Therefore, the positive and negative amplitude of the function ROM is
There is one need to have a one step difference. When a difference of 1 step is created with respect to full scale, and the positive and negative amplitudes are set to 511 as in A and multiplied by (-1), a B curve is obtained, and the negative side of the B curve is one step over and the positive side is 1 It causes a shortage of steps. If this phenomenon is left as it is, this also appears as spurious. This phenomenon can be stopped by executing +1 addition only during (-1) multiplication.

As a concrete solution for this, FIG.
An IDR (Inrierse Detector Reg.) 46 shown in FIG. This has a function of processing a (-1) multiplication condition (K3) of sine and cosine by OR logic and detecting it by a register, and its logic diagram is shown in FIG. Then, the output of the IDR 46 is corrected (Compensa
ter) circuit 45. The correction circuit 45 is specifically achieved by adding the + 1's complement from the Ci terminal in the circuit illustrated in FIG.

Another cause of spurious is in step H (horizontal axis) in FIG. This is a method of defining dt in df = (1 / 2π) (dc / dt) shown by the equation (4). P. In the case of dt = 400 ns (= 1 / fc = 1 / 2.5 MHz) described in 10, dt corresponds to the center of the frequency band that can be generated, and fc
Since the phase shift update is performed in the cycle of, the fc component becomes spurious. The best way to avoid the above fc spurs is
A system in which the phase shift update is set outside the frequency band in which generation is possible is preferable. If dc / dt = K and K is set to a constant value, for example, the block configuration may be dc / 2, dt / 2. That is, the H step of dc / 2 FIG 3 2 ¹¹
-1 = 2047 H step cosROM32, si
The nROM 33 is described as one cycle, and the ROM drive clock is 2CK. 4C of the reference oscillator 51 of FIG.
Divide the K clock by 2 and input 2C to the terminal 25 of the integrator 20.
Is to supply K. The above-mentioned technique of spurious countermeasures is applied to cosROM32, sinROM33 and integrator 20.
When the present invention is carried out in the state of FIG. 1 when applied to, the signal output from the terminal 44 in the figure is a signal having a practical value sufficient for a wireless communication signal source because spurious is significantly lowered. Will be provided.

The present invention is not limited to the above embodiment. For example, the sine wave signal and the cosine wave signal are completely the same signal only with a phase difference of 1/4 period. Therefore, in the above-described embodiment, the same effect can be obtained by exchanging the sine wave signal and the cosine wave signal. Is obtained. Further, the digital multipliers 35, 36, 45 and 48 may be configured to multiply sine waves and cosine waves.

[0033]

【The invention's effect】

According to the present invention, according to the present invention, the first and second digital setting signals having the quadrature phase relationship are multiplied by the first and second digital reference signals having the quadrature signal relationship, and respectively. The output obtained by logically synthesizing the multiplication output of is used as a clock signal. According to this, if it is within a predetermined frequency range with respect to the reference signal, it is possible to obtain a clock signal of an arbitrary frequency by the setting signal. Therefore, a clock signal having a frequency very close to the reference signal can be easily obtained.
A clock signal having a frequency higher than that of the reference signal can be easily obtained. Further, since the digital frequency conversion processing of performing the calculation for each cycle of the reference signal is performed, according to the present invention, it is possible to realize a clock generator having excellent linear characteristics and free from higher-order distortion. Further, since the phase of the digital reference signal is defined as a timing pulse corresponding to 0, π / 2, 3π / 2 and is used in place of the sine reference signal, the digital multiplier is composed of a simple logic circuit. Have a real benefit that can It is easy to make IC. Further, since the outputs of the digital multipliers are logically combined, the power consumption can be reduced, the IC can be formed, and the operation speed can be increased, as compared with the above-mentioned adder.

Inventions of Claims 2 and 3: In addition to the effect of the invention of Claim 1, the generation of spurious noise due to the ROM description method of the sine ROM or the cosine ROM of the phase modulator used in the present invention is greatly reduced. As a result, a clock signal generator having a sufficient practical value as a signal source for wireless communication is provided.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating an embodiment of a digital clock generator of the present invention.

FIG. 2 is a diagram for explaining the data content of cos or sin ROM.

FIG. 3 is an explanatory diagram related to spurious caused by a description method in a sinROM.

FIG. 4 is a waveform diagram of sin (2nfct) and −cos (2nfct) digital reference signals.

FIG. 5 is a diagram showing an example of an IDR circuit.

FIG. 6 is a diagram showing a circuit example relating to a correction circuit.

FIG. 7 is a diagram showing an original configuration of a digital clock generator according to the present invention.

8 is a diagram for explaining the data content of cos or sin ROM of FIG. 7. FIG.

9 is a waveform diagram of the digital reference signal of FIG.

FIG. 10 is a circuit diagram of the digital multiplier shown in FIG.

11 shows a truth table of FIG. 10, (A) shows bit D
Until ₀ ~D _8, (B) is a diagram of the bit D _9.

FIG. 12 is a diagram illustrating an output clock signal, where (A) is a case where C is positive and (B) is a case where C is negative.

FIG. 13 is a diagram similar to FIG. 12 in the case where the set value is changed.

FIG. 14 is a diagram showing band characteristics of a bandpass filter which is an element of the present invention.

FIG. 15 is a diagram showing a phase characteristic diagram similar to FIG.

FIG. 16 is a diagram illustrating a conventional clock generator.

FIG. 17 is a diagram illustrating still another conventional clock generator.

[Explanation of symbols]

1 ... Crystal oscillator, 2 ... Buffer, 3 ... Resonance circuit, 4 ... Resonance transformer, 5 ... Comparator, 6 ... Divider, 7 ... Output terminal, 11 ... Crystal oscillator, 12 ... Phase comparator, 13 ... Variable oscillator, 14 ... Divider, 15 ... Comparator, 16 ...
Frequency divider, 17 ... Output terminal, 20 ... Integrator, 21 ... Terminal,
23 ... Register, 24 ... Adder, 25 ... Terminal, 26 ... Terminal, 30 ... Phase modulator, 31 ... 1 clock delay device, 3
2, 33 ... Sine and cosine ROM, 35 ... First digital multiplier, 36 ... Second digital multiplier, 37, 38
... buffer register, 39 ... digital adder, 39 '
... OR gate, 40 ... D / A converter, 41 ... Band pass filter, 42 ... Comparator, 43 ... Output terminal, 44 ... Terminal, 45 ... Compensater circuit, 50 ... Reference signal generator, 51 ... Reference oscillator, 52 ... Shift register.

[Procedure amendment]

[Submission date] October 9, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction contents]

Further, in such a clock generator, if the multiplier can be configured by a simple logic circuit or the like, the circuit configuration will be easy and it will be advantageous for IC implementation. A digital clock generator that the applicant has already proposed (Patent Document 1)
Japanese Patent Laid-Open No. 3-60501) solves such a problem. However, even in the above proposal, there is a problem in spurious characteristics that can be used for wireless communication, and since the addition time in the high-speed addition circuit is long, the increase in the frequency range that can be generated is limited.

Claims (3)

[Claims] 1. An integrator for integrating a setting signal for setting a clock frequency (Δf), a generator for a reference signal (fc), and a phase modulator for phase-modulating the output of the integrator as an input. In the digital clock generator having the above, in the reference signal generator, the reference oscillation output is π.
A digital reference signal whose phase is sequentially shifted by / 2 is formed, the integrated output signal is converted into a digital setting signal in the integrator, and the digital setting signal is quadrature phase in the digital ROM means in the phase modulator. After being converted into a component of the set phase signal in the periodic function of the relation, the digital reference signal is converted into a component of the digital reference phase signal having a quadrature phase relationship with each other by the π / 2 phase delay means, the two components are The multiplier outputs are multiplied by each other, and the outputs of the multipliers are logically summed with each other, and then the discrete analog signal is formed by the D / A converter. The D / A converter output is a bandpass filter. Where the output of the true analog signal converted by passing through is determined by the reference signal (fc) and the clock frequency (Δf) set. Frequency (fc ± △ f) digital clock generator, characterized in that it is adapted to be used as a clock signal having a. 2. The periodic function of the digital ROM means forms a sine or cosine function, and the maximum positive or negative amplitude is formed with a one-step difference from full scale, and the D / A conversion is performed. 2. A digital clock generator according to claim 1, wherein a complement correction circuit is provided in front of the device to improve spurious characteristics. 3. A reference cycle C, wherein the periodic function of the digital ROM means forms a sine or cosine function.
The phase shift update necessary for frequency generation of the periodic function formed for K is generated in 2CK cycles, and the spurious based on the reference cycle is moved outside the principle frequency generation. A digital clock generator as described.