JPH10135973A - Primary group speed interface accommodation system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the primary group speed interface accommodation circuit, in which structural data are transferred with respect to the primary group speed interface accommodation system. SOLUTION: The primary group speed interface circuit 300 is used to contain a transmission line 100, having a primary group speed interface defined by the JT-I431 of the TTC standards to an ATM communication network 200. In this case, only valid time slots for transmission of valid data are extracted from time slots continuously reached from the primary group speed interface transmission line, structural data are formed by the valid data sent through the valid time slots, the speed is converted and the result is given to an ATM cell assembly processing, structural data outputted from ATM cell disassembly processing are inverse speed converted and distributed to valid time slots of the primary group speed interface transmission line, through the provision of a speed conversion means 301.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a primary rate interface accommodating system, and more particularly to JT-I43 of the TTC standard.
The present invention relates to a primary rate interface accommodating method in a primary rate interface accommodating circuit for accommodating a transmission line having a primary rate interface defined in 1 in an ATM communication network.

[0002]

2. Description of the Related Art FIG. 21 is a diagram illustrating a conventional primary rate interface accommodating circuit, FIG. 22 is a diagram illustrating an unstructured data cell system in FIG. 21, and FIG. It is a figure which illustrates a conversion system.

[0003] In FIG. 21, reference numeral 1 denotes a JT standard of the TTC standard.
A transmission line having a primary rate interface defined by I431 [hereinafter referred to as a primary rate interface transmission path (1)], and 2 is an ATM [Asynchronous T
ransfer Mode] is a communication network (2), and 3 is a primary rate interface accommodating circuit that accommodates the primary rate interface transmission line (1) in the ATM communication network (2).

Primary group speed interface accommodating circuit (3)
Is composed of a primary rate interface protocol control unit (4), an ATM-UNI protocol control unit (5), and an ATM cell assembling / disassembling unit (6), as shown in FIG.

Primary rate interface transmission line (1)
Is a time-division multiplexing system as shown in FIG. 22, and includes 24 time slots (TS ₁ ) to (TS ₂₄ ) for transmitting 8 bits (b _{1 to} b ₈ ) and 1 bit (b), respectively.
The frame ( _F ) composed of the frame bits (b _F ) composed of the frame (F) is continuously transmitted at a cycle of 125 microseconds.

Primary group speed interface accommodating circuit (3)
Is the frame bit (b _F ) arriving from the primary rate interface transmission line (1), as shown in FIG.
When received by all the time slots (TS ₁₎ to primary rate interface protocol controller all valid and invalid data to be transmitted [hereinafter referred to as unstructured data] by _{(TS 24) (4),} ATM The cell assembling / disassembling unit (6) divides the packet into 48 octets (bytes) to form a payload (PL _C ) of each ATM cell (C) as shown in FIG. 22 and a header of the ATM cell (C) composed of 5 octets. (H _C) was added to assemble the ATM cell (C) with, and sends the ATM network (2) by ATM-UNI protocol control section (5).

The primary rate interface accommodating circuit (3) receives an ATM cell (C) arriving from the ATM communication network (2) as shown in FIG. 22 by the ATM-UNI protocol control unit (5). The ATM cell assembling / disassembling unit (6) extracts the ATM cell payload (PL _C ) from each received ATM cell (C), and the primary rate interface protocol control unit (4) extracts the ATM cell payload (P).
By continuously arranging L _C ), the data is restored to unstructured data as shown in FIG. 22 and transmitted to the primary rate interface transmission line (1).

As described above, when communication is performed between a pair of primary rate interface transmission lines (1) accommodated in the ATM communication network (2) via the primary rate interface accommodating circuit (3), transmission is performed. Unstructured data arriving from the primary rate interface transmission line (1) on the transmission side is converted into ATM cells (C) in the primary rate interface accommodating circuit (3) on the transmission side, and the ATM communication network (2) All data transferred to the primary rate interface accommodating circuit (3) on the receiving side via the interface and converted into ATM cells (C) by the primary rate interface accommodating circuit (3) on the receiving side and transferred. Is restored to the original unstructured data and transmitted to the primary rate interface transmission line (1) on the receiving side.

In addition to the above-described unstructured data, FIG.
Structured data as shown in FIG. 3 is also used. FIG.
At 3, the structured data removes the frame bits (b _F ) from the unstructured data similar to that shown in FIG. 22 and transmits 8 bits (b _{1 to} b ₈ ) respectively 24
Time slots (TS ₁ ) to (TS ₂₄ )
25 After configuring frame (F _A) to be transmitted in microseconds cycle, SAR · PDU payload in the ATM cell payload by dividing every 46 octets (PL _C) (P
L _S ).

[0010] Note that in place of the removed frame bits (b _F), in order to notify the receiving side separator frame (F _A), as shown in FIG. 23, from 1 octet in the ATM cell (C) The pointer (P _T ) is provided at a predetermined position in the ATM cell payload (PL _C ), and the pointer (P _T ) is provided.
_T) and position, and sets the offset value of the head position of the first frame (F _A).

Since the pointer (P _T ) is not provided for each ATM cell (C) but is provided only for the even-numbered ATM cell (C), the ATM cell (C) without the pointer (P _T ) is provided.
SAR PDU payload (PL _S ) is 47 octets.

Further, the structured data is one of the data transmitted in all the time slots (TS ₁ ) to (TS ₂₄ ).
It has also been proposed to transmit only valid data and remove invalid data.

However, the conventional primary rate interface accommodating circuit (3) does not have a function of transferring such structured data.

[0014]

As is apparent from the above description, the conventional primary rate interface accommodating circuit can transfer only unstructured data and does not consider the transfer of structured data. It was not possible to respond to requests to transfer structured data.

An object of the present invention is to realize a primary rate interface accommodating circuit capable of transferring structured data.

[0016]

FIG. 1 is a diagram illustrating the principle of the present invention. In the figure, 100 is JT-I4 of the TTC standard.
Primary rate interface transmission path defined by 31;
Reference numeral 00 denotes an ATM communication network, and reference numeral 300 denotes a primary rate interface accommodating circuit that accommodates the primary rate interface transmission line (100) in the ATM communication network (200).

Reference numeral 301 denotes speed conversion means provided in the primary group speed interface accommodating circuit (300) according to the present invention. Reference numeral 302 denotes a fluctuation absorption amount determining means provided in the primary group speed interface accommodating circuit (300) according to the present invention (claim 5).

The speed conversion means (301) extracts only valid time slots for transmitting valid data from the time slots continuously arriving from the primary rate interface transmission line (100), and transmits the valid time slots by the valid time slots. After the structured data is formed from the valid data, the speed is converted and transmitted to the ATM cell assembling process, and the speed of the structured data output from the ATM cell disassembly process is inversely converted. 100) to the valid time slots. [Claim 1] Note that the speed conversion means (301) synchronizes the frame boundary notification signal indicating the head time slot of the effective time slot sequence for transmitting the effective data with the head time slot in the ATM cell assembling / disassembling process. Communication is considered. [Claim 2] Further, the speed conversion means (301) is connected to the ATM communication network (20).
In order to absorb the temporal fluctuation of the reference clock extracted from 0), it is considered to check and control the number of clocks in one frame of time-division multiplexed data arriving from the primary rate interface transmission line (100). . [Claim 3] Further, the speed conversion means (301) adds a time slot for transmitting information exchanged between the primary group speed interface accommodating circuit (300) to a time slot for transmitting valid data, and Thus, it is considered that information can be transferred between the primary rate interface accommodating circuit (300) or the primary rate interface transmission line (100). [Claim 4] The fluctuation absorption amount determining means (302) is provided for the ATM communication network (2).
In order to absorb fluctuations in the arrival interval of ATM cells arriving from 00), the amount of fluctuation absorption to be accumulated for a predetermined time is determined according to the number of valid time slots.

Accordingly, only valid data is extracted from all data transmitted via the primary rate interface transmission line to form structured data, and cells are assembled based on the structured data to form an ATM communication network. , And the communication efficiency of the ATM communication network is greatly improved.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing a primary rate interface accommodating circuit according to an embodiment of the present invention, and FIG.
FIG. 4 is a diagram exemplifying the upstream speed conversion control unit in FIG. 3, FIG. 5 is a diagram exemplifying the upstream write control timing in FIG. 4, and FIG. FIG. 7 is a diagram illustrating an example of an uplink read control timing in FIG. 4, FIG. 7 is a diagram illustrating an example of an uplink reset control timing in FIG. 4, and FIG. 8 is a diagram illustrating an example of a downlink speed conversion control unit in FIG. 9, FIG. 9 is a diagram exemplifying the downlink write control timing in FIG. 8, FIG. 10 is a diagram exemplifying the downlink read control timing in FIG. 8, and FIG. 11 is an operation clock generator (part 1) in FIG. FIG. 12 is a diagram illustrating an operation timing in FIG. 11, FIG. 13 is a diagram illustrating an effective time slot setting unit in FIG. 11, and FIG. 14 is a diagram in FIG. FIG. 15 is a diagram exemplifying an operation clock generating unit (No. 2) in FIG. 15, FIG. 15 is a diagram exemplifying operation timing in FIG. 14, and FIG. 16 is structured data according to an embodiment of the present invention (claims 1 to 3). FIG. 17 is a diagram showing the history of cell assembly and disassembly, and FIG. 17 is a diagram showing the history of additional information transfer according to the embodiment of the present invention (claim 4).
8 is a diagram illustrating the ATM cell assembling / disassembling unit in FIG. 2, FIG. 19 is a diagram illustrating the fluctuation absorption amount table in FIG. 18, and FIG. 20 is a diagram illustrating the cell fluctuation absorption in FIG. The same reference numerals indicate the same objects throughout the drawings.

FIG. 2 shows a primary rate interface transmission line (1) as the primary rate interface transmission line (100) in FIG.
An ATM communication network (2) is shown as the TM communication network (200), and a primary rate interface accommodating circuit (3) is shown as the primary rate interface accommodating circuit (300) in FIG. A speed conversion unit (7) is provided as speed conversion means (301).

In FIG. 18, a fluctuation absorption amount table (611) as the fluctuation absorption amount determining means (302) in FIG. 1 is provided in the ATM cell reception control unit (61) constituting the ATM cell assembling / disassembling unit (6). It is provided in.

First, an embodiment of the present invention (claims 1 to 3) will be described with reference to Fig. 2 to Fig. 16. As shown in Fig. 3, the speed conversion unit (7) performs upstream speed conversion. It comprises a controller (71), a downstream speed conversion controller (72), and an operation clock generator (73). The upstream speed conversion controller (71) has a configuration as shown in FIG. The downstream speed conversion control unit (72) has a configuration as shown in FIG. 8, and the operation clock generation unit (73) has the configuration shown in FIG.
Having such two kinds of configurations shown in 1 and 14 [former operation clock creation portion (73 _A), referred to the latter the operation clock creation portion and (73 _B)].

First, the upstream speed conversion control unit (71)
3 will be described with reference to FIGS. In FIG. 2, time-division multiplexed data (hereinafter referred to as data (D _UI )) arriving from a primary rate interface transmission line (1) to a primary rate interface protocol control unit (4) in a primary rate interface accommodating circuit (3). FIG. 22)
The valid data is transmitted only from a specified number of time slots (TS) continuing from the first time slot (TS ₁ ), and the other time slots (TS) are invalid data. Shall be transmitted.

Hereinafter, a time slot (TS) for transmitting valid data is referred to as a valid time slot (TS _E ).
In this case, the effective time slots (TS _E ) are six time slots (TS ₁ ) to (TS ₆ ).

In such a case, the valid time slot (TS
_E ) Valid time slot setting signal (S _ETS ) indicating the number of
[This time, (S _ETS ) = (6)] is set in required parts in the primary group speed interface accommodating circuit (3).

Primary rate interface protocol control
In the unit (4), a primary group speed interface monitoring unit
(41) is the primary rate interface transmission line (1)
Data arriving from (D_UI), The data
(D_UI) To the clock signal (CLK _UI)
And a frame (F) composed of 193 bits (b)
The frame bit (b_F)
From the start, the time slot (TS_{twenty four}) At the beginning
Frame boundary notification signal (S_FP) Generated and received
Data (D_UI) And the extracted clock signal (CLK_UI)
And the generated frame boundary notification signal (S_FP) And the speed
Transfer to the upstream speed conversion control unit (71) in the conversion unit (7).
Reach.

In the upstream speed conversion control section (71), the write control section (UWR) (711) sends a preset valid time slot setting signal (S _ETS ) [=
(6)], the effective time slot (TS _E ) is changed from the first time slot (TS ₁ ) to the sixth time slot (TS
₆ ) Recognize that.

In this state, the data (D _UI ) and the clock signal (C
LK _UI ) and the frame boundary notification signal (S _FP ), the frame (F _A ) is generated by removing the frame bits (b _F ) from each frame (F).

Next, the write control unit (UWR) (711)
Frame (F_A) And the data (D _UI) To serial-parallel conversion
And the data (D_UIP),
The received clock signal (CLK_UI) Is divided by 8
Data (D_UIP) And a clock signal (CLK_UIP)
Generate

Next, the write control unit (UWR) (711)
Frame boundary notification signal (S_FP) Is predetermined
Valid time slot (TS_E) 1st time slot
(TS ₁) From the clock signal (CLK_UIP)
Write signal (WR_U), And the data (D_UIP) And
Input to the temporary storage memory (UFIFO) (712)
And sequentially stored in the temporary storage memory (UFIFO) (712).
Store.

When the number of generations of the write signal (WR _U ) is equal to the preset valid time slot setting signal (S _ETS ) [=
(6)], the generation of the subsequent write signal (WR _U ) is stopped.

As described above, the write control unit (UWR) (71)
1) is the data (D _UIP ) in each frame (F _A )
Only the first time slot (TS ₁ ) to the sixth time slot (TS ₆ ) corresponding to the valid time slot (TS _E ) are stored in the temporary storage memory (UFIFO) (712).

The write control unit (UWR) (711)
A _cellization start time slot signal (S _TSEUI1 ) consisting of one bit (logic “0”) indicating the first time slot (TS) of the effective time slot (TS _E ) is generated, and is generated in parallel with the time slot (TS ₁ ). Temporary storage memory (UFI
FO) (712).

That is, the temporary storage memory (UFIFO) (7
12) includes 8-bit data (D _UIP ) and 1
Celling start time slot signal (S
_TSEUI1 ) is stored in the same address in 9 bits in parallel.

FIG. 5 shows the lapse of time of the various signals described above. On the other hand, the read control unit (URD) (713), the write control unit (UWR) (711) is a second frame (F _A)
Of the reference clock signal (CLK _ATM ) of the ATM communication network (2) after confirming that the storage of the valid time slot (TS _E ) data (D _UIP ) in the temporary storage memory (UFIFO) (712) has started. From the time of rising, the data (D) already stored in the temporary storage memory (UFIFO) (712)
_UIP ) and the _cellization start time slot signal ( _STSEUI1 ) start to be extracted. [Here, the read control unit (URD)
(713) is a temporary storage memory (UFIFO) (71)
The data (D _UIP ) extracted from 2) and the _cellization start time slot signal (S _TSEUI1 )
_UOP ) and a _cellization start time slot signal (S _TSEUO1 ). The read control unit (URD) (713) simultaneously sets the cellization start time slot signal (S _TSEUO1 ) extracted from the temporary storage memory (UFIFO) (712) to logic “0”. The extracted data (D _UOP ) is determined as valid data, and a temporary storage memory (UFIFO)
If the _cellization start time slot signal (S _TSEUO1 ) extracted from (712) _remains set to logic “1”,
Write control unit (UWR) (711) as abnormal data,
Initialize the temporary storage memory (UFIFO) (712) and the read control unit (URD) (713).

When valid data is extracted, the extracted data (D _UOP ) is converted into data (D _UO ) by parallel-to-serial conversion, and the operation clock signal (CLK ₆ ) of the ATM cell assembling / disassembling section ( ₆ ). And the reference clock signal (CLK _ATM ) to the ATM cell assembling / disassembling section (6).

FIG. 6 shows the lapse of time of the various signals described above. On the other hand, the reset control unit (RSC) (714)
The temporary storage memory (UFIFO) (712) adds the number of _cellization start time slot signals (S _TSEUI1 ) stored in the temporary storage memory (UFIFO) (712), and a read control unit (URD) (713). Has a built-in counter for subtracting the number of _cellization start time slot signals (S _TSEUO1 ) extracted from the temporary storage memory (UFIFO) (712), and the count value of the counter is set to a predetermined reference value [this time (( 2)], the write control unit (U
WR) (711) to temporary storage memory (UFIFO)
Or become data stored in the (712) (D _UIP) is three frames (F _B) above, or the read control unit (URD)
(713) is a temporary storage memory (UFIFO) (71)
At the time of extraction from 2), it is determined that the _cellization start time slot signal (S _TSEUO1 ) has not been detected successfully, and the write control unit (UWR) (711) and the read control unit (URD) (7
13) and a temporary storage memory (UFIFO) (71)
2) Initialize.

The time lapse of the various signals described above is shown in FIG.
It is. The ATM cell assembling / disassembling unit (6) performs the speed change in the up direction.
Valid time slot transmitted from the exchange control unit (71)
(TS_E) Is a time slot (TS₁) Through (TS
₆) Data (D_UOP), ATM cell assembly / disassembly unit (6)
Clock signal (CLK₆) And start cellization
Time slot signal (S_TSEUO1) Is received, 46
Or 47 octets of data (D_UOP) Or 46
Octet data (D_UOP) And pointer (P_T)When
SAR / PDU payload (PL_S)
Further, the required SAR / PDU header (H_S) And ATM
Cell header (H_C) Is added to the ATM cell of the predetermined format.
Assembling (C), ATM-UNI protocol control unit
The packet is sent to the ATM communication network (2) via (5).

Next, the operation of the downstream speed conversion control section (72) will be described with reference to FIGS. The ATM cell assembling / disassembling unit (6) receives an ATM cell (C) arriving at the primary rate interface accommodating circuit (3) from the ATM communication network (2) via the ATM-UNI protocol control unit (5). , The received ATM cell (C) is decomposed, the ATM cell header (H _C ) and the SAR / PDU header (H _S ) are removed, and the ATM including the pointer (P _T ) is decomposed.
By the pointer (P _T ) extracted from the cell (C), SA
R · PDU payload (PL _S) of the data (D _RI) a frame (F _B) units of 6 valid time slot (TS _E)
The data is classified every minute and stored in a temporary storage memory (not shown).

In the speed conversion unit (7), the write control unit (DWR) (72) in the downstream speed conversion control unit (72) is used.
1) is a clock signal (CLK ₆ ) for the operation of the ATM cell assembling / disassembling section ( ₆ ) and 6 effective time slots (T
A frame boundary notification signal (S _FP ) corresponding to S _E )
Each frame is transmitted to the TM cell assembling / disassembling unit (6) in synchronization with the transmitted operation clock signal (CLK ₆ ) and the reference clock signal (CLK _ATM ) held by the ATM cell assembling / disassembling unit (6). (F _B ) data (D _DI ) is received.

Next, the write control unit (DWR) (721)
The received data (D _DI ) is serial-parallel converted, converted into parallel 8-bit data (D _DIP ), the clock signal (CLK ₆ ) is divided by 8, and a clock signal synchronized with the data (D _DIP ) (CLK _DIP ).

Next, the write control unit (DWR) (721)
From the rise of the reference clock signal (CLK _ATM ), the first time slot (T _E ) of the effective time slot (TS _E )
From S ₁ ), a write signal (WR _D ) synchronized with the clock signal (CLK _DIP ) is generated, and together with the data (D _DIP ),
Input to the temporary storage memory (DFIFO) (722),
The data is sequentially stored in a temporary storage memory (DFIFO) (722).

The number of generations of the write signal (WR) is equal to the preset effective time slot setting signal (S _ETS ) [=
If matching (6)], to exit the store one frame (F _B) of data (D _{DI P),} to start storing a next one frame (F _B) of data (D _DIP).

The write control unit (DWR) (721)
A _deceleration start time slot signal (S _TSEDI1 ) consisting of one bit (logic “0”) indicating the first time slot (TS) of the effective time slot (TS _E ) is generated, and is generated in parallel with the time slot (TS ₁ ). Temporary storage memory (DF
IFO) (722).

That is, the temporary storage memory (DFIFO) (7
22) has 8-bit data (D _DIP ) and 1
Deceleration start time slot signal (S
_TSEDI1 ) is stored in the same address in 9 bits in parallel.

FIG. 9 shows the lapse of time of the various signals described above. On the other hand, the read control unit (DRD) (723), the write control unit (DWR) (721) is a second frame (F _B)
After confirming that the data (D _DIP ) of the effective time slot (TS _E ) has been started to be stored in the temporary storage memory (DFIFO) (722), the data is first transmitted from the primary group speed interface monitor (41). From the rise of the transmission reference timing signal (S _DO ), the temporary storage memory (DF
IFO) (starts extraction of the already stored data to 722) (D _DIP) and disassemble the starting time slot signal (S _TSEDI1). [Here, the read control unit (DRD) (723) extracts the data (D _DIP ) extracted from the temporary storage memory (DFIFO) (722) and the deceleration start time slot signal (S _TSEDI1 ) into the data (D _DOP ) _{And the deceleration} start time slot signal (S _TSEDO1 ). When the deceleration start time slot signal ( _STSEDO1 ) extracted from the temporary storage memory (DFIFO) (722) is set to logical "0", the read control unit (DRD) (723) The extracted data (D _DOP ) is determined as valid data, and a temporary storage memory (DFIF) is determined.
O) If the _deceleration start time slot signal ( _STSEDO1 ) extracted from (722) _remains set to logic "1", the write control unit (DWR) (72)
1) Initialize the temporary storage memory (DFIFO) (722) and the read control unit (DRD) (723).

When valid data is extracted, the extracted data (D _DOP ) is converted into data (D _DO ) by parallel-to-serial conversion, and a clock signal (41) transmitted from the primary group speed interface monitoring unit (41). CLK _D0 ) and transmits it to the primary group speed interface monitor (41).

FIG. 10 shows the lapse of time of the various signals described above. On the other hand, a reset control unit (RSC) (724)
Is a write control unit (DSC) similar to the reset control unit (RSC) (714) in the upstream speed conversion control unit (71).
WR) (721) is a temporary storage memory (DFIFO)
(722) is added to the number of _deceleration start time slot signals (S _TSEDI1 ), and the read control unit (DRD)
(723) is a temporary storage memory (DFIFO) (72)
2) The deceleration start time slot signal (S
_TSEDO1 ) is built in. When the count value of the counter exceeds a predetermined reference value (this time, (2) pieces), the write control unit (DWR) (721) _{temporarily stops} the count value. storage memory (DFIFO) (722) data stored in (D _DIP) has three became frame (F _B) above, or the read control unit (DRD) (723) temporary storage memory (DFIFO) (722) At the time of extraction, it is determined that the _deceleration start time slot signal (S _TSEDO1 ) has been unsuccessfully detected, and the write control unit (DWR) (72)
1) Initialize the read control unit (DRD) (723) and the temporary storage memory (DFIFO) (722).

The time lapse of the various signals described above is shown in FIG.
Reset control unit (RSC) (714)
You. The primary group speed interface monitoring unit (41)
Transmission from group speed interface protocol control unit (4)
Valid time slot (TS_E) Minutes data
(D_DO) In the first time slot (TS₁)-6th tie
Slot (TS₆) And the remaining 7th time slot
To (TS₇) To 24th time slot (TS_{twenty four})
Is invalid data generated internally (for example, all bits
(B₁) Through (b)₈) Is set to logic "1"]
Frame (F_A) To assemble and further frame bit
(B _F) Is added to assemble the frame (F), and the primary group speed
To the interface transmission path (1).

Next, the operation of the operation clock generator (73) will be described with reference to FIGS. The operation clock creating section (73) creates a clock signal (CLK ₆ ) for operating the ATM cell assembling / disassembling section (6), supplies the clock signal to the inside of the speed conversion section (7), and also generates the ATM cell assembling / disassembling section (6). ) Also supplies.

The operation clock generation unit (73) has the configuration shown in FIG.
Operation clock creation portion (73 _A) as shown in the operation clock creation portion shown in FIG. 14 (73 _B) and is taken into account. First operation clock creation portion the operation of the (73 _A), will be described with reference to FIG. 11 to FIG. 13.

The operation clock generator (73 _A )
As shown in FIG. 3, the oscillation unit (OSC) (731), the frequency division unit (DIV) (732), the effective time slot setting unit (E
TS) (733) and operation clock output unit (CMK)
(734).

The oscillating unit (OSC) (731) operates at 2
A 4.576 megabit clock signal (CLK ₀ ) is output. The frequency divider (DIV) (732) includes an oscillator (OS
C) The clock signal (CL) output from (731)
K ₀ ) is divided by a factor of 384 using a reference clock signal (CLK _ATM ) input from the ATM communication network (2), and a clock signal (CLK ₁ ) of 64 kilobits per second is output.

Effective time slot setting unit (ETS) (7)
33) is the number of valid time slots (N) [where (N) =
From the effective time slot setting signal corresponding to 1 to 24] (S _{ET S)} [see FIG. 13], the primary rate interface receiving circuit (3) to enable the number of time slots defined (N) [this time (N) = 6], the valid time slot setting signal (S _ETS ) = (00110)
_B [where B indicates a binary number] is selected and output.

Operation clock output unit (CMK) (734)
Receives a clock signal (CLK ₀ ) [= 24.576 Mbits / sec] from an oscillation unit (OSC) (731) at a terminal (C) and an effective time slot setting unit (ETS) (733) at a terminal (D). ) Receives an effective time slot setting signal (S _ETS ) [= (00110) _B ],
Further, a clock signal (CLK ₁ ) (= 64 kilobits per second) is inputted to the terminal (L) from the frequency divider (DIV) (732), and a clock signal (CL of 384 kilobits per second) is input.
A clock signal (CLK ₂ ) synchronized with K ₁ ) is output.

FIG. 12 shows the lapse of time of the various signals described above. However, the clock signal (CLK
₀ ) and the accuracy of the reference clock signal (CLK _ATM ), the clock signal (CLK ₁ ), and hence the clock signal (CLK ₂ ) as shown in FIG.
It was not output normally.

In addition, in the elapse of time shown in FIG.
Reference clock signal (CLK _ATM ) and clock signal (CL
K ₂ ) means that the preset timing may not be synchronized due to a jitter component or the like.

Therefore, the reference clock signal (CLK_ATM)
The number of each valid time slot within the standard (N)
The required number of clocks is calculated and the actual clock signal (C
LK _Two) To count the number of clocks
, The next reference clock signal (CLK_ATM)But
Until it comes, a function to stop output is added.

The operation clock creating section (73 _B ) to which the above functions are added will be described with reference to FIGS. 14, 15 and 13. Oscillator (OSC) (731), frequency divider (DIV)
(732), an effective time slot setting unit (ETS) (7
33) and operation clock output section (CMK) (734)
Is the same as the operation clock generator (73 _A ) shown in FIG.
5), clock number reference value setting unit (CST) (736),
Comparison unit (CMP) (737) and output control unit (OP)
C) (738) is newly added.

Clock number reference value setting unit (CST) (73)
6) presets and outputs a clock number reference value corresponding to the number of valid time slots (N). The clock number counter (CNT) (735) outputs the clock signal (C) output from the operation clock output unit (CMK) (734).
LK ₂ ), and outputs the counting result.

The comparison unit (CMP) (737) compares the count result output from the clock number counter (CNT) (735) with the clock number reference value output from the clock number reference value setting unit (CST) (736). In comparison, when the count result output from the clock number counter (CNT) (735) matches the clock number reference value output from the clock number reference value setting unit (CST) (736), a match signal is output.

The output control section (OPC) (738) operates the operation clock output section (CMK) (734) when no coincidence signal is output from the comparison section (CMP) (737).
The clock signal (CLK ₂ ) output from the comparator (CMP) (737) is output as it is, but when the match signal is output from the comparator (CMP) (737), the operation clock output unit (CMK) (7
The clock signal (CLK ₂ ) output from 34) is cut off.

As a result, the reference clock signal (CL
At the time of the rise of K _ATM ), the output control unit (OPC) (7
Period of the clock signal output from the 38) (CLK ₂₎ is varied, but the change point of the clock signal (CLK _2),
If the phase relationship of the data (D) is not disturbed, the subsequent operation is not affected.

FIG. 15 shows the lapse of time of the various signals described above. FIG. 16 shows the process of assembling and disassembling the structured data cell according to the embodiment of the present invention (claims 1 to 3).

As is apparent from the above description, according to the embodiments of the present invention (claims 1 to 3), the primary rate interface transmission lines (1) accommodated in the ATM communication network (2) are: The transfer of structured data becomes possible, and the economics, speed and convenience of the communication system are greatly improved.

FIGS. 2 to 16 are merely one embodiment of the present invention (claims 1 to 3). For example, the number of effective time slots (N) to be processed is 6 time slots (T
The present invention is not limited to S) and many other modifications are considered, but the effect of the present invention does not change in any case. Further, the configuration of the primary group speed interface accommodating circuit (3) to which the present invention is applied is not limited to the illustrated one, and many other modifications are considered. The effect remains the same.

Further, it goes without saying that the primary rate interface to which the present invention is applied is not limited to the illustrated one. Next, an embodiment of the present invention (claim 4) will be described with reference to FIG.
This will be described with reference to FIG.

In the embodiments of the present invention shown in FIGS. 2 to 16 (claims 1 to 3), 6 out of 24 time slots (TS ₁ ) included in one frame (F) of the primary rate interface. The time slot (TS) [ie, time slots (TS ₁ ) to (TS ₆ )] is a valid time slot (TS _E ), and the remaining 18 time slots (TS) [ie, time slots (TS ₇ ) to (T ₇ )
S _24)] is for transferring invalid data, not included in the structured data format.

Using the invalid time slot (TS _NE ), for example, it is considered to transfer required information between the primary rate interface accommodating circuits (3). For example, in FIG. 2, the OAM control unit (43) provided in the primary rate interface protocol control unit (4)
Is the primary rate interface protocol controller (4)
It is assumed that the operation and maintenance information (OAM) in the network is collected and transferred to the opposite primary rate interface accommodating circuit (3) in communication via the ATM communication network (2).

In the same manner as described above, the speed converter (7) converts the data (D _SI ) arriving from the primary group speed interface transmission line (1) into a primary group speed interface monitor (41).
Received via the extracts is valid time slot (TS _E) time slot (TS ₁₎ to (TS ₆₎ data of only (D _SI), assembled frame (F _B).

On the other hand, the OAM control unit (43) sets the collected operation and maintenance information (OAM) in an arbitrary invalid time slot (the seventh time slot (TS ₇ ) in FIG. 17), and sets it in the frame (F _B ). adding to assemble such frames (F _C) shown in FIG. 17, and transmits the ATM cell assembly and disassembly unit (6).

The ATM cell assembling / disassembling unit (6) assembles the ATM cell (C) as shown in FIG. 17 for storing the frame (F _C ) in the SAR PDU payload (PL _S ) in the same manner as described above. The data is transmitted to the ATM communication network (2) via the ATM-UNI protocol control unit (5).

On the other hand, when an ATM cell (C) as shown in FIG. 17 arrives from the opposed primary rate interface accommodating circuit (3), the ATM cell assembling / disassembling unit (6)
From ATM-UNI protocol control section (5) ATM cells received via the (C), and extracts such as frame (F _C) is shown in Figure 17.

In the primary rate interface protocol control unit (4), the OAM control unit (43)
Only the time slot (TS ₇ ) is separated from the frame (F _C ) extracted from the cell assembling / disassembling section (6), and the frame (F _B ) composed of the remaining time slots (TS ₁ ) to (TS ₆ ) is speed-converted. while it transmitted to the unit (7), operation and maintenance information to be transmitted by a time slot (TS ₇₎ (O
AM) is extracted and subjected to necessary analysis processing.

On the other hand, the speed converter (7) receives the transmitted frame (F _B ) in the same manner as described above. The transition of the various frames and ATM cells described above is shown in FIG.

As is apparent from the above description, according to the embodiment of the present invention (claim 4), the valid time slot (T
Using an invalid time slot (TS _NE ) other than S _E ), maintenance operation information (OAM) and the like can be transferred between the primary rate interface accommodating circuits (3), thereby improving the operation performance of the communication system. I do.

FIGS. 2 and 17 are merely an embodiment of the present invention. For example, the information to be transferred is not limited to the maintenance and operation information (OAM). Although considered, the effect of the present invention does not change in any case. Further, the transfer of information by the invalid time slot (TS _NE ) is not limited to between the primary rate interface accommodating circuits (3), and the terminal connected via the primary rate interface transmission line (1). Many other variations, such as between devices, may be considered, but the effect of the present invention does not change in any case.

Next, an embodiment of the present invention (claim 5) will be described.
This will be described with reference to FIGS. FIG. 2, FIG.
8 to 20, the transfer time of the ATM cell (C) transferred via the ATM communication network (2) is not constant, but is transmitted at regular intervals from the transmission side primary rate interface accommodating circuit (3). The ATM cell (C) also slightly fluctuates in the time interval at which it arrives at the primary rate interface accommodating circuit (3) on the receiving side.

In order to absorb this kind of fluctuation of the arrival interval, the incoming primary cell rate interface accommodating circuit (3) stores the arriving ATM cells (C) for a certain period of time, and then receives the receiving primary group speed interface at a constant interval. The technique of transferring the data to the transmission path (1) is widely used. [The time accumulated to absorb fluctuations is referred to as fluctuation absorption guarantee time (T _CDV ). Here, if the transmission interval of the ATM cell (C) is fixed,
Guarantee absorption time for fluctuation of received ATM cell (C) (T _CDV )
The means for storing only ATM cells can be realized by storing a fixed amount of ATM cells (C).

On the other hand, the transmission interval of the ATM cell (C) according to the embodiment of the present invention (claims 1 to 3) varies variously depending on the number (N) of valid time slots. Therefore, in order to realize the fluctuation absorption guaranteed time (T _CDV ), the ATM cell (C) to be stored corresponding to the number of effective time slots (N)
Changing the number becomes effective.

The ATM cell assembling / disassembling section (6) shown in FIG. 16 is provided with an ATM cell reception control section (61), a temporary storage memory (FIFO) (62), and a reception data assembling / sending section (63). Further, a fluctuation absorption table (611) as shown in FIG. 19 is provided in the ATM cell reception control section (61).

In the fluctuation absorption table (611), the number of effective time slots (N) [=] that can be adopted in the primary rate interface transmission line (1) in FIG.
(1) to (24)], the transmission rate (kb /
s), cell rate (cell / s), cell arrival interval (m
s) and the fluctuation absorption guarantee time (T _CDV ) is 1.5
The fluctuation absorption amount (X) (cell) in the case of milliseconds is set.

For example, if the number of valid time slots (N) is 3
In the case of the time slot (TS), the arrival interval of the ATM cell (C) is 1.94 ms as shown in FIGS. 19 and 20 (a).

In such a case, the fluctuation absorption guarantee time (T
_{In order} to guarantee ( _CDV ) = 1.5 ms, it is necessary to accumulate two or more ATM cells (C) from FIGS. 19 and 20 (a).

The number of effective time slots (N) is set to 20
In the case of the time slot (TS), the arrival interval of the ATM cell (C) is 0.29 ms as shown in FIGS. 19 and 20 (a).

In such a case, the fluctuation absorption guarantee time (T
_{In order} to guarantee _CDV ) = 1.5 milliseconds, it is necessary to accumulate seven or more ATM cells (C) from FIGS. 19 and 20 (a).

Based on the above principle, prior to the operation of the primary group speed interface accommodating circuit (3), an effective time slot setting signal (S _ETS ) [for example, the number of effective time slots (N) = (20)] is input. The ATM cell reception control unit (61) includes a built-in ATM cell reception control unit (6).
Referring to 1), the fluctuation absorption amount (X) corresponding to the number of effective time slots (N) [= (20)] set by the input effective time slot setting signal (S _ETS ).
[= (7)] is selected.

In this state, when an ATM cell (C) arrives at the primary rate interface accommodating circuit (3) from the ATM communication network (2), the ATM cell reception control section (61) in the ATM cell assembling / disassembling section (6). ) Receives the arriving ATM cell (C) via the ATM-UNI protocol control unit (5), sets a write signal (WR), and
A memory (FIFO) (6) for temporarily storing cells (C) sequentially
2).

The ATM cell reception controller (61) counts the number of stored ATM cells (C) in the temporary storage memory (FIFO) (62), and determines the fluctuation absorption amount (X) When [= (7)] is reached, the received data assembling / sending unit (63) is started, and the temporary storage memory (FI) is started.
FO) (62) to extract the ATM cell (C) being stored.

The activated received data assembling / sending unit (63)
Extracts the ATM cells (C) currently stored in the temporary storage memory (FIFO) (62) at predetermined intervals on a first-come, first-served basis, executes the above-described disassembly process, and extracts the extracted valid time slot (TS).
The data ( _DDI ) of _E ) is transmitted to the speed converter (7).

The ATM cell reception control section (61) is adapted to store the ATM cell (C) in the temporary storage memory (FIFO) (62).
When the accumulated number of 減少 decreases to the fluctuation absorption amount (X) described above,
The activation and reception of the reception data assembling / sending unit (63) is stopped, and the extraction of the ATM cell (C) being accumulated in the temporary accumulation memory (FIFO) (62) is stopped.

As described above, the temporary storage memory (FIF
O) (62) always contains the fluctuation absorption amount (X) [=
(7)], the same number of ATM cells (C) are accumulated, and the fluctuation absorption guarantee time (T _CDV ) is guaranteed.

As is apparent from the above description, according to the embodiment of the present invention (claim 5), even when the number of effective time slots (N) in the primary rate interface transmission line (1) changes, the reception time is not changed. It is possible to always set the specified fluctuation absorption guarantee time (T _CDV ) for the ATM cell (C), thereby improving the transmission quality of the primary rate interface transmission line (1).

FIGS. 2 and 18 to 20 are merely examples of the present invention. For example, the number of valid time slots (N) is 3 time slots (TS) or 20 time slots (TS) shown in FIG. ) Is not limited to
Many other variations are considered, but the effect of the invention remains the same in any case. Further, the configurations of the ATM cell assembling / disassembling unit (6) and the primary rate interface accommodating circuit (3) to which the present invention (claim 5) is applied are not limited to those shown in the drawings, and there are many other modifications. Is considered,
In any case, the effect of the present invention does not change.

[0096]

As described above, according to the present invention, only valid data is extracted from all data transmitted via the primary rate interface transmission line to form structured data,
The cells can be assembled by the structured data and transferred via the ATM communication network, and the communication efficiency of the ATM communication network is greatly improved.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 illustrates a primary rate interface accommodating circuit according to an embodiment of the present invention.

FIG. 3 shows a speed converter in FIG.

4 is an upstream speed conversion control unit in FIG. 3;

FIG. 5 is an uplink write control timing in FIG. 4;

FIG. 6 is an uplink read control timing in FIG. 4;

FIG. 7 is an uplink reset control timing in FIG. 4;

8 is a downlink speed conversion control unit in FIG.

FIG. 9 is a timing chart of the downlink write control in FIG.

FIG. 10 is a timing chart of the downlink read control in FIG.

FIG. 11 is an operation clock generation unit in FIG. 3 (part 1)

FIG. 12 is an operation timing in FIG. 11;

FIG. 13 shows a valid time slot setting unit in FIG.

FIG. 14 is an operation clock generation unit (part 2) in FIG. 3;

FIG. 15 is an operation timing in FIG. 14;

FIG. 16 is a process of assembling and disassembling a structured data cell according to an embodiment of the present invention (claims 1 to 3);

FIG. 17 shows the background of additional information transfer according to the embodiment of the present invention (claim 4).

FIG. 18 is an ATM cell assembling / disassembling unit in FIG. 2;

19 is a fluctuation absorption amount table in FIG. 18;

FIG. 20 is a diagram for explaining cell fluctuation absorption in FIG. 18;

FIG. 21 shows a conventional primary group speed interface accommodating circuit.

FIG. 22 shows an unstructured data cell method in FIG. 21.

FIG. 23: Structured data cell method

[Explanation of symbols]

Reference Signs List 1, 100 Primary rate interface transmission line 2, 200 ATM communication network 3, 300 Primary rate interface accommodating circuit 4 Primary rate interface protocol control unit 5 ATM-UNI protocol control unit 6 ATM cell assembly / disassembly unit 7 Speed conversion unit 41 Primary rate interface monitoring unit 42, 52 Alarm signal transmission unit 43, 53 OAM control unit 51 UNI interface monitoring unit 61 ATM cell reception control unit 62 Temporary storage memory (FIFO) 63 Received data assembly transmission unit 71 Upward speed conversion control Unit 72 Downstream speed conversion control unit 73 _A , 73 _B Operation clock generation unit 301 Speed conversion unit 302 Fluctuation absorption amount determination unit 611 Fluctuation absorption amount table 711 Write control unit (UWR) 712 Temporary storage memory (UFIFO) 713 Read Control unit (U RD) 714 Reset control unit (RSC) 721 Write control unit (DWR) 722 Temporary storage memory (DFIFO) 723 Read control unit (DRD) 724 Reset control unit (RSC) 725 Phase-locked oscillation unit (PLO) 726 Selector ( SEL) 731 Oscillator (OSC) 732 Divider (DIV) 733 Effective time slot setting (ETS) 734 Operation clock output (CMK) 735 Clock counter (CNT) 736 Clock reference setting (CST) 737 Comparison unit (CMP) 738 Output control unit (OPC)

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Takayuki Takeda 1-21-1, Akebonocho, Tachikawa-shi, Tokyo Inside Fujitsu ACS Co., Ltd. (72) Inventor Hiroomi Hariba 1-13-3 Higashisakura, Higashi-ku, Nagoya-shi, Aichi Prefecture Inside Fujitsu Nagoya Communication System Co., Ltd. (72) Inventor Takayuki Iwasa 1-33-1 Higashisakura, Higashi-ku, Nagoya-shi, Aichi Prefecture Inside Fujitsu Nagoya Communication System Co., Ltd. No. 3 Fujitsu Nagoya Communication System Co., Ltd. (72) Inventor Yasushi Sasakawa 4-1-1 Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu Co., Ltd.

Claims (5)

[Claims] 1. A primary rate interface accommodating circuit for accommodating, in an ATM communication network, a transmission line having a primary rate interface defined in a standard (JT-I431) of the Telegraph and Telephone Technical Committee (TTC), From time slots continuously arriving from the speed interface transmission line, only valid time slots for transmitting valid data are extracted, and after structured data is formed by the valid data transmitted by the valid time slots, the speed is converted. Speed conversion means for transmitting the data to the ATM cell assembling process, converting the speed of the structured data output from the ATM cell disassembly process, and distributing the data to the available time slots of the primary group speed interface transmission line. Primary rate interface accommodating method. 2. The speed conversion means transmits a frame boundary notification signal indicating a head time slot of a valid time slot sequence transmitting the valid data to the ATM cell assembling / disassembling process in synchronization with the head time slot. 2. The primary rate interface accommodating method according to claim 1, wherein the signal is transmitted. 3. The clock converting means in one frame of time-division multiplexed data arriving from the primary rate interface transmission line, for absorbing a temporal variation of a reference clock extracted from the ATM communication network. Check the number
The primary rate interface accommodating method according to claim 1, wherein the primary rate interface is controlled. 4. The speed conversion means according to claim 1, further comprising: adding a time slot for transmitting information to be exchanged between said primary rate interface accommodating circuits to a time slot for transmitting said valid data to form structured data. 2. The primary rate interface accommodating method according to claim 1, wherein information can be transferred between said primary rate interface accommodating circuits or primary rate interface transmission lines. 5. A primary rate interface accommodating circuit for accommodating, in an ATM communication network, a transmission line having a primary rate interface defined in a standard (JT-I431) of the Telegraph and Telephone Technical Committee (TTC), From time slots continuously arriving from the speed interface transmission line, only valid time slots for transmitting valid data are extracted, and after structured data is formed by the valid data transmitted by the valid time slots, the speed is converted. Rate conversion means for transmitting the structured data output from the ATM cell disassembly processing to the ATM cell assembling processing, performing speed reverse conversion, and then distributing the structured data to effective time slots of the primary rate interface transmission path; In order to absorb the fluctuation of the arrival interval of ATM cells arriving from the network, store for a predetermined time. Fluctuation absorption amount, primary rate interface accommodating method characterized by providing a fluctuation absorbing amount determination means for determining in response to the number of effective time slots for that.