KR0128839B1 - Apparatus for controlling high speed packet scheduling - Google Patents

Abstract

A high speed packet scheduling control apparatus is provided to improve a multiplexing efficiency and minimize a loss of packet. The scheduling control apparatus comprises a flag extractor(11) for outputting an input control signal and a packet input data a plurality of buffer(12) for storing the packet data and the input control signal for the flag extractor(11) a packet scheduler(13) for outputting a buffer selective signals(1-n) according to the extracting flag and a packet output(14) for supplying an output control signal to the buffers(12) and transferring the stored packet data stored in the buffer(12) to output lines. Thereby, it is possible to minimize the packet losses.

Description

High speed packet scheduling controller

1 is a block diagram of a fast packet scheduling control device according to the present invention.

FIG. 2 is a detailed block diagram of the flag extraction unit of FIG.

3 is a detailed block diagram of the packet scheduler of FIG.

4 is a detailed configuration diagram of the packet output unit of FIG.

* Explanation of symbols for main parts of the drawings

11: flag extractor 12: buffer

13: packet scheduler 14: packet output unit

21: buffer control logic section 22: packet counter

23: flag extraction logic section 31: flag comparator

32: packet selection and feedback logic section 33: packet timing logic section

41: output control logic section 42: packet transmission logic section

The present invention stores a packet unit information, such as a cell, in a buffer in a Broadband Integrated Information Network (B-ISDN): B-ISDN) provided with various services having a wide bandwidth through a single interface. The present invention relates to a fast packet scheduling controller for extracting a level and multiplexing the packet at high speed.

In general, with the development of communication technology, users demand various services of high quality and occur intensively such as high-speed data service such as file transfer and real-time video service with variable bit rate, as well as continuous service such as sex service or video service. In order to provide bursty services over the same link, B-ISDN of ATM (Asynchronous Transfer Mode) has emerged. In the B-ISDN environment, a technique suitable for ATM is different from that of TDM (Time Division Multiplexing) based on the conventional STM (Synchronous Transfer Mode) method. In order to flexibly handle not only traffic but also traffic with burst characteristics, a multiplexing technique based on statistical methods is adopted.

However, the conventional ATM multiplexing device continuously generates empty slots with processing nodes, which causes a problem in the fairness of cell transmission due to the line adjacent to the processing node taking up more slots, and it is not easy to implement the switch structure. There was a problem.

Accordingly, the present invention devised to solve the problems of the prior art between the above and the present invention is easy to implement while operating at a high speed at a simple gate level when the cells are transmitted in a fair manner while maintaining a low loss rate of the packet-based information. And to provide a high speed packet scheduling controller that can be used for the transmission of the majority of packets having a fixed length.

The present invention for achieving the above object is a flag extraction means for receiving a packet from a plurality of input lines to extract and output the flag, and receives the buffer (1 ~ n) selection signal and outputs an input control signal and packet input data, the Buffering means for storing packet data transferred together with the input control signal from the flag extracting means; Packet scheduling means for receiving a flag extracted by the flag extracting means and outputting a buffer (1 to n) selection signal for determining a packet transmission order to the flag extracting means; Means for supplying an output control signal to the buffering means in accordance with the buffer selection signals input from the packet scheduling means to receive the packet data stored in the buffering means and transmit the packet data to an output line; . Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a fast packet scheduling control apparatus according to the present invention. As shown in the figure, the apparatus for controlling a high speed packet scheduling according to the present invention receives a packet with a plurality of input lines and extracts a flag consisting of n pieces for each input line, and the flag extracting unit 11. N buffers 12 for storing the packet data transferred from the packet output unit, a packet output unit 14 for transmitting the packet data stored in each buffer 12 to an output line, and flags extracted from the flag extraction unit 11; And a packet scheduler 13 for outputting the n buffers 1 to n selection signals for determining the packet transmission order to the flag extraction section 11 and the packet output section 14.

Referring to the operation of the high-speed packet scheduling controller configured as described above, each component receives and operates a system clock, and the flag extractor 11 is composed of n flags each in a packet input from a plurality of input lines. Is extracted and transmitted to the packet scheduler 13, and the packet scheduler 13 selects buffers 1 to n according to priorities among the n buffers 12 according to the input flags. Outputs When the flag extractor 11 receives the buffer 1 to n selection signals from the packet scheduler 13, the flag extractor 11 transmits the packet input data input from the input line to the corresponding buffer 12 together with the input control signal. In addition, the packet output unit 14 controls the buffer 12 as an output control signal according to the buffer 1 to n selection signals, and transmits the received packet output data to the output line.

2 is a detailed block diagram of the flag extraction unit 11 according to the present invention.

As shown in the figure, the flag extractor 11 is composed of an n-definition counter, and upon receiving packet input data from the input line, outputs the packet arrival signals 1 to n, and the full flag of the flag logic extractor 23. A buffer control logic section 21 for transmitting the packet input data to the buffer 12 in packet units with an input control signal in consideration of the (FF) signal, and n up-down counters. The number of packets stored in the buffer 12 is calculated by receiving the packet arrival signals 1 to n outputted from the buffer control logic unit 21 and the buffer 1 to n selection signals outputted from the packet scheduler 13. And a flag extracting logic unit 23 for extracting a flag through a comparator when the packet counter 22 to be outputted is received and the number of packets is received from the packet counter 22. A flag extracting unit 11 configured as described above is provided. Looking at the operation of the buffer control logic unit 21 The packet input data are stored in the buffer 12 allocated to each input line one by one, and when one complete packet arrives, the packet arrival signals 1 to n are output to the packet counter 22, and the flag extraction logic section 23 Receive the FF (Full Flag) signal indicating that the packet in the buffer 12 is full so that there is no more space for the packet to occupy, so that the data is no longer stored in the buffer 12 to prevent loss of existing data. On the other hand, the packet counter 22 keeps the counter unchanged when the buffer 12 is full, and increments the counter when the packet arrival signals 1 to n are received, and the packet is transferred to the buffer 12. Receiving the buffer selection signal 1 to n indicating that the signal is transmitted, the counter is decremented to determine the number of packets The flag extracting logic unit 23 receiving the determined number of packets indicates that one or more packets exist in the buffer 12. Notifying Flag (NEF) Generates a flag divided into an AFF (Almost Full Flag) signal and an FF signal indicating that a call and a packet occupy more than two-thirds of the capacity of the buffer 12. Among the flags, the NEF signal and the AFF signal are the packet scheduler 13. The buffer 12 is notified to output the buffer 1 to n selection signals.

3 is a detailed block diagram of the packet scheduler 13 according to the present invention.

As shown in the figure, the packet scheduler 13 determines the packet to be transmitted by using the flags (NEF, AFF) received from the flag extracting unit 11, and the buffers 1 to 1 according to the initial packet length value. n) To generate a selection signal, the configuration is a packet timing logic section for generating a synchronized packet synchronization signal of the system clock according to the fixed packet length value initially set for a packet having an octal counter internally up to 256 lengths (33), a plurality of packet selection and feedback logic sections 32 for generating buffers (1 to n) selection signals that are activated for each initially set packet length using the packet synchronization signal as a clock; and the packet selection and feedback. The packet 1-n selection signal is combined with the buffer 1-n selection signal generated by the logic unit 32 and the NEF signal and the AFF signal output from the flag extraction logic unit 23. And a flag comparator 31 and outputting to the hollow weave portion 32.

Referring to the operation of the packet scheduler 13 configured as described above, when delivering an 53-octet long ATM packet, the initial packet length is set to 53, and the packet timing logic unit 33 includes an operation circuit and a D flip-flop ( Flip-Flop) generates a packet sync signal asserted every 53 clocks.

The n packet selection and feedback logic sections 32 using the generated packet synchronization signals as clocks generate buffer 1 to n selection signals that are activated for each packet length of 53, for example, the first. The first packet selection and feedback logic section 32 selects the buffer (1) selection signal (CTX-SB (1)) and the kth packet selection and feedback logic section 32 selects the buffer (k) selection signal (CTX-SB (k). The nth packet selection and feedback logic section 32 generates a buffer n selection signal CTX-SB (n). In addition, during initialization, each buffer 12 has priority in the order of buffer 1 to buffer k, and the packet is transmitted from the buffer 12 where the packet arrives first, and the priority of the buffer except for initialization is As follows.

If the present packet (k) is being transmitted, the packet present in the buffer (k + 1) has a buffer k + 1 of AFF (Almost Full Frag) or the buffer ( If there is no packet in k + 2 and there is a packet in buffer k + 1, the packet is output. If a packet exists in buffer k + 2, the buffer (k + is expressed as in the following equation (2). If packet exists in 2) and there is no packet in buffer (k + 1) or buffer (k + 2) is AFF (Almost Full Frag) and buffer (k + 1) is not AFF (Almost Full Frag) .

(CTX-SB (k + 1) = CTX-SB (k) (NEF (k + 1) & NEF * (k + 2)) ∥

AFF (k + 1). … Formula (1)

(CTX-SB (k + 2) = (CTX-SB (k) (AFF * (k + 1) & AFF (k + 2)) ∥

(NEF * (k + 1) & NF * (k + 2)). … Formula (2)

The packet present in the buffer (k + i) can be outputted when there is no packet in the buffer (k + i) in the buffer (k + i) as shown in Equation (3) below. If the packet is present, the packet is delivered from the buffer (k) as shown in Equation (4) below.

(CTX-SB (k + i) = (CTX-SB (k) (AFF (k + 1) & NEF * (k + 2) & NENE * (k + 3) &)

… & NEF * (ki-1) & NEF * (k + 1)). … Formula (3)

(CTX-SB (k) = (CTX-SB (k) (AFF * (k + 1) & NEF * (k + 2) & NEF * (k + 3) &)

… & NEF * (n) & NEF * (1) &… & NEF (k)... … Formula (4)

As shown in Equations (1), (2), (3), and (4), the buffer k in which the current packet is transmitted occupies the dominant priority during the next packet transmission time and occupies the current transmission time. Compare the AFF (Almost Full Flag) of the next two buffers (12) (e.g., buffer (k + 1) and buffer (k + 2) when sending packets from the current buffer (k)) The packet is transmitted from the buffer 12 generating the AFF (Almost Full Flag). If both buffers 12 generate the Almost Full Flag, the buffer (k + 1) has priority. ) Are ranked from buffer (k + 3) to buffer (n), buffer (1), and buffer (k-1) in this case.In this case, only the Empty Flag (NEF) is compared to the AFF (Almost Full Flag). Only the buffers 12 that have generated suffice to occupy all the transfer time.

The (n) generated by each flag comparator 31 is a combination of a buffer 1 to n selection signal generated by the packet selection and feedback logic unit 32 and a flag Not Empty Flag (NEF) or Almost Full Flag (AFF). The -1) packet selection signals are used as inputs of the JK flip-flop inside the packet selection and feedback logic section 32 to assert only one signal of the n buffer 1 to n selection signals for the set length of the packet.

4 is a detailed block diagram of the packet output unit 14 according to the present invention.

As shown in the figure, the packet output unit 14 receives the buffer 1 to n selection signals from the packet scheduler 13 and generates an output control signal for reading out the packets in the buffer 12 to generate the buffer 12. A thrust control logic section 41 for controlling the transmission of the signal and a packet transmission logic section 42 for transmitting the packet output data through the output control logic section 41 to the output line together with the output timing signal.

According to the present invention configured and operated as described above, logic is configured to perform flag comparison and selection of a packet to be transmitted next within one packet transmission time, thereby preventing waste of a channel, and one buffer during the packet transmission time. Since only one packet is transmitted, all buffers share the output line, effectively minimizing the traffic to each input line while minimizing the packet.

In addition, it is easy to implement while multiplexing packets at high speed by configuring at a simple gate level, and it is possible to transmit a large number of packets having a fixed length as well as cell data.

Claims (4)

Flag extracting means for receiving packets from a plurality of input lines, extracting and outputting flags, receiving buffer selection signals 1 to n, and outputting input control signals and packet input data; Buffering means for storing packet data transferred together with an input control signal from the flag extracting means; Packet scheduling means for receiving a flag extracted by the flag extracting means and outputting a buffer (1 to n) selection signal for determining a packet transmission order to the flag extracting means; And a packet output means for supplying an output control signal to the buffering means in response to the buffer selection signals input from the packet scheduling means and receiving packet data stored in the buffering means and transmitting the packet data to an output line. High speed packet scheduling controller. The method of claim 1, wherein the flag extracting means outputs packet arrival signals 1 to n upon receiving one packet from an input line, and packetizes the packet input data together with the input control signal in consideration of the full flag (FF) signal. Buffer control means for transmitting to the buffering means in units; Packet counting means for receiving a packet arrival signal (1 to n) drawn from the buffer control means and a buffer (1 to n) selection signal output from the packet scheduling means and outputting the number of packets stored in the buffering means; And flag extracting means for receiving the number of packets from the packet counting means, extracting a flag, outputting the flag to the packet scheduling means, and outputting a full flag (FF) signal to the buffer control means. The apparatus of claim 1 or 2, wherein the packet scheduling means comprises: packet synchronization means for generating a packet synchronization signal synchronized with a system clock according to an initially set length of a packet; A plurality of packet selection and feedback means for generating a buffer (1 to n) selection signal that is activated for each initially set packet length by using the packet synchronization signal output from the packet synchronization means as a clock; And generating a packet (1 to n) selection signal by combining the buffer (1 to n) selection signal generated by the packet selection and feedback means and the flag output from the flag extraction means to output to the plurality of packet selection and feedback means. A fast packet scheduling control device comprising a plurality of corresponding flag comparison means. 4. The apparatus of claim 3, wherein the packet output means comprises: output control means for receiving a buffer (1 to n) selection signal from the packet scheduling means and controlling the buffering means with an output control signal to receive packet output data; And packet transmission means for transmitting the packet output data through the output control means to an output line together with an output timing signal.