KR950000672B1 - Cell demultiplexing device in asynchronous transfer mode - Google Patents

Abstract

The cell demultiplexer separates the cells by the destination and transfers them to the designated destination when various types of cells are received from the one line in the ATM. The demultiplexer comprises a data shift circuit (10), a VCI/VPI extracting and analyzing circuit (12), a cell buffer (11), an idle cell generating and controlling circuit (13).

Description

Cell Demultiplexer in ATM System

1 is a block diagram of an apparatus of the present invention.

2nd data shift circuit.

3 is a VCI / VPI area in a cell structure and a cell header of an ATM.

4 is a VCI / VPI extraction and analysis circuit.

5 is a timing diagram for a data shift circuit, a VCI / VPI extraction and analysis circuit.

6 is a cell buffer configuration diagram.

* Explanation of symbols for main parts of the drawings

10: data shift circuit 11: cell buffer

41: VCI / VPI extraction circuit 42: VCI / VPI analysis circuit

44: Cell Destination Latch

According to the present invention, in the Asynchronous Transfer Mode (ATM) method, which is a transmission method used in a broadband ISDN (Integrated Services Digital Network), various types of cells are multiplexed through a single transmission path and inputted to each cell destination. The present invention relates to a cell demultiplexing device that transmits separately.

Synchronous Transfer Mode (STM), which is used as a transmission technology of circuit switching and narrow-band ISDN, is a time slot of a certain size for a certain time interval in which a single bandwidth of a frame is called a frame. By dividing the data into time slots and assigning the corresponding channel to each time slot, this method can process only signals and data having a constant communication speed, and thus it is impossible to easily accommodate services having different communication speeds. In this scheme, time slots are fixedly allocated to subscribers or data terminals to be transmitted through a single transmission path, so that multiple timeslots are transmitted in an empty channel state even when there is no data to be transmitted. Channel use is inefficient when multiplexing or demultiplexing.

On the other hand, in the ATM method to which the present invention is applied, unlike the synchronous delivery method, a channel is allocated only to a terminal having data ready to transmit data (statistical multiplexing) so that a transmission path can be efficiently used. In the ATM method, information to be sent is divided into 48 bytes, and a 53-byte header is attached to transmit 5 bytes as one cell. Therefore, in ATM, 53 bytes of fixed-length cell are transmitted, but the number of cells to be transmitted can be changed according to the communication speed, so that low-speed data of several kbps, 64kbps information such as voice, and 100Mbps or more information such as HDTV can be simultaneously transmitted. Can be. In the header attached to the beginning of the cell, the VCI (Virtual Channel Identifier), which is control information for flow control, error control, etc. during cell transmission, and information for identifying a destination of a communication call to be transmitted. (Virtual channel identifier) and VPI (Virtual Path Identifier), cell demultiplexing according to the present invention is performed by distributed processing for each cell destination according to VCI and VPI indicating a destination of each cell. .

As described above, the present invention has been proposed as a method for performing a cell demultiplexing function in an ATM method that transmits information in units of cells, and thus cell demultiplexing is used to interpret a VCI / VPI region of a cell header. According to the determination of the cell destination, the type of information contained in the currently reached cell is transmitted to the switch or the terminal according to the flow direction of the cell in the case of voice or data information, which is broadband ISDN information or narrowband ISDN information. In the case of the signal information for setting the flow path of the purpose of transmitting to the predetermined destination, such as transmitting to the processor for controlling the flow path of each cell.

In the system in which cells having different destinations are multiplexed and input through a single transmission path to achieve the above object, a cell clock is used as a latch clock to shift data to be multiplexed until the destination of each cell is determined. A data shift circuit used to prevent cell loss, and a VCI / VPI (VCI / VPI) extracting VCI / VPI composed of 24 bits of each cell header using the VCI / VPI (Virtual Channel Identifier / Virtual Path Identifier) extraction clock from the data shift circuit. / VPI extraction circuit, VCI / VPI analysis circuit that informs the destination of the cell corresponding to the extracted VCI / VPI, and latches the destination of each cell as the cell buffer enable clock to be stored in the destination signal of each cell and each cell buffer. Cell destination latches that synchronize with data and cell buffers to store cells according to cell types are used in ATM systems. It characterized in that it performs a demultiplexing function.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

1 is a diagram illustrating an embodiment of a cell demultiplexing apparatus of an ATM method according to the present invention, and a destination to be transmitted in a system in which multiple (N-1) valid cells and one idle cell are multiplexed and inputted (N-2). The same species is considered, and one cell is divided into two paths with different destinations. In general, the ATM scheme can accommodate services with different bandwidths for a given bandwidth. Therefore, in view of bandwidth, narrowband ISDN information with bandwidths of several tens of kbps and broadband ISDN information with bandwidths of tens of Mbps or hundreds of Mbps are multiplexed. When considering from the traffic point of view of the information source, the ratio of information such as signal information generated randomly to the information source of the traffic pattern having periodicity such as voice or video information that periodically generates a cell Cells of the periodic traffic pattern may be multiplexed and transmitted. Since multiplexing in ATM is performed only within a predetermined bandwidth, the present invention is an example in which there are (N-1) types of valid cells that satisfy a predetermined bandwidth. It can be applied to the demultiplexer. FIG. 1 is a schematic diagram showing the cell demultiplexing structure of the data shift circuit 10, the VCI / VPI extraction and analysis circuit 12, (N-1) cell buffers 11, and the idle cell generation and control circuit 13. Consists of. Since the data shift circuit is multiplexed and the cell buffer in which the cell is to be stored is selected according to the destination of the inputted cells, the VCI / VPI extraction and analysis circuit 12 determines the cell buffer to store the currently input cell after the cell destination is determined. It is a circuit used to wait for a time that can be memorized, and the VCI / VPI extraction and interpretation circuit 12 extracts VCI / VPI representing the destination of each cell from the header of each cell, and inputs the current according to the destination of the cell. The cell buffer is used to store a cell buffer in which cells to be stored, and the cell buffer is a circuit for storing a cell according to a cell destination, where (N-1) idle cells and one idle cell are multiplexed. A cell is input, but an idle cell is stored in (N-1) cell buffers, one idle cell is discarded, and the output of the cell buffer is a bandwidth in which (N-2) idle cells and one idle cell are defined. Multiplexed according to characteristics (N-1) The contents of the buffer is output to the other path. In addition, when the demultiplexing result requires the remultiplexing, the cell buffers are configured with an idle cell generation and control circuit 13 for transmitting an idle cell when there is no data to be transmitted. In general, in case of having (N-1) paths, which is an extension of the demultiplexing device, and a result of demultiplexing having groups by the same destination, the demultiplexing is performed in the above manner. Demultiplexing can be performed.

2 is a data shift circuit, which is composed of six 8-bit latches. The data shift circuit prevents cell loss during this process because the destination of successive cells is determined by the VCI / VPI value of the header, or the cell buffer in which the currently input cell is to be stored after the cell destination is determined. It was used to The inputs of these latches are shifted by one bit by a latch clock commonly connected to these latches as a continuous stream of multiplexed cells. The output of the shifted cell is commonly connected to the (N-1) cell buffers, and if the corresponding cell buffers of (N-1) are selected by the VCI / VPI extraction and analysis circuit, the corresponding cell is controlled by the cell input control circuit. It is stored in the order entered in the buffer.

3 shows the VCI / VPI region in the cell structure and header in the ATM scheme. The cell structure is recommended in the CCITT. A cell consists of a total of 53 bytes as a header of 5 bytes and an information area of 48 bytes. The double VCI consists of 16 bits including the lower nibble 4 bits of the second byte of the header 5 bytes of each cell, the 8 bits (the third byte) and the upper nibble 4 bits of the 4th byte. Depending on the configuration of the broadband network, the case of UNI (User Network Interface: physical connection between terminal and switching period) and NNI (Network Node Interface: interface between network nodes) are different. For UNI, the VPI consists of the lower nibble of the first byte of the header and the upper nibble of the second byte, which consists of a total of 8 bits.For the NNI, the VPI consists of the upper nibble of the first byte and the second byte of 12 Although it is composed of bits, the VCI / VPI extraction and interpretation for the two cases can be the same.

4 is a VCI / VPI extraction and analysis circuit comprising a VCI / VPI extraction circuit 41, a VCI / VPI analysis circuit 42, a VCI / VPI control device 43, and a cell destination analysis signal latch 44. . The VCI / VPI extraction circuit 41 composed of a total of 16 bits of latches latches and extracts VCI / VPI composed of 24 bits from the data shift circuit with a VCI / VPI extraction clock. This VCI / VPI extraction clock is generated only once every cell, and the extracted VCI / VPI is input to the VCI / VPI analysis circuit 42. In general, since the destination of the cell according to the VCI / VPI value is determined at the system design time, the destination of the cell according to the VCI / VPI value is determined at the system design time. Therefore, the VCI / VPI control device 43 determines the VCI / VPI at system initialization time. The destination of the cell corresponding to the value is initialized in the VCI / VPI analysis circuit, and the VCI / VPI analysis circuit 42 compares the output of the VCI / VPI extraction circuit with the value initialized in the VCI / VPI analysis circuit and selects the corresponding destination. The result of the determination is output to the cell destination latch 44. The signal input to the cell destination latch 44 is latched to the cell buffer enable clock, and these signals are output as the cell destination signal to enable the cell buffer determined for each cell destination.

FIG. 5 relates to timing with respect to FIG. 2 and FIG. The cell start clock is repeated for every 53 bytes of data in a cell that has a width of one cycle of the cell clock low. The cell clock and cell multiplexing inputs are synchronized to the cell start clock low as shown in the figure, An example of the present invention is a case in which the second data is input while being maintained during the low period of the cell start clock. Each latch of the data shift circuit uses the cell clock as a latch signal, and the data input to each latch is latched at the rising edge of the cell clock so that the output of latch 0 is half clocked delayed with respect to the cell multiplexing input. Is output. Since VCI / VPI consists of a cell header and a total of 24 bits among the 1st, 2nd, 3rd, and 4th bytes, the VCI / VPI extraction clock for each byte extracts 24 bits of VCI / VPI. The clock is generated only once every cell, and the data extracted by each VCI / VPI extraction clock is maintained for one cell interval. According to the extracted VCI / VPI, the output of the VCI / VPI analysis circuit is output to the output data bus to designate the destination corresponding to the current VCI / VPI during the analysis circuit-enabled signal period. It is latched by a clock and used as a cell destination signal output. By using the cell buffer enable clock generated only once every cell, the cell destination signal is maintained for one cell, and the output signal is selected in synchronization with the first bind data of the cell buffer input data which is the output of the data shift circuit. The cell buffer is stored without losing cell multiplexing input data.

6 is a diagram illustrating a cell buffer configuration in which the input and output of each cell buffer operate independently of each other. Examples of cell buffers that can be used for this purpose are first-in first-out (FIFO) memory or dual port random access memory (DPRAM). When data input to each cell buffer in synchronization with the reception clock is desired to be transmitted, transmission data is output in synchronization with the transmission clock according to the transmission condition. As the input and output of each cell buffer is operated asynchronously, various services having different communication speeds can be provided by adjusting the number of cell transmissions in the ATM method.

The apparatus of the present invention configured as described above can adjust the number of cell transmissions according to the communication speed by operating a cell buffer in which cell buffer input and output operate asynchronously for each cell destination in cell demultiplexing in the ATM method. The low speed data and the high speed data can be demultiplexed, and the destination of each cell can be easily extracted as the VCI / VPI value, thereby facilitating the cell demultiplexing, which is essential for ATM system design.

Claims (3)

In a system in which cells having different destinations are multiplexed and input through a single transmission path, a cell clock is used as a latch clock to shift the multiple input data to prevent cell loss until the destination of each cell is determined. VCI / VPI for extracting VCI / VPI composed of 24-bits of each cell header using the data shift circuit 10 used and the VCI / VPI virtual channel identifier / virtual path identifier extraction clock from the data shift circuit 10. VPI extraction circuitry 41 VCI / VPI analysis circuitry 42 that informs the destination of the cell corresponding to the extracted VCI / VPI and the destination signal of each cell by latching the destination of each cell with the cell buffer enable clock. Cell de-neutralization in ATM method with cell destination latch 44 to synchronize with data to be stored in cell buffer and cell buffer 11 for storing cells according to cell type Cell demultiplexing apparatus in the ATM method, characterized in that to perform a function. The VCI / VPI analysis circuit 42 stores data for determining a destination of a cell corresponding to a VCI / VPI value at system initialization, and stores the VCI / VPI extracted by the data shift circuit 10. A cell demultiplexing apparatus in an ATM system, characterized in that a destination signal of each cell is specified in accordance with an address. 3. The method according to claim 1 or 2, wherein the signal specifying the cell destination from the VCI / VPI is latched by a cell buffer enable clock that occurs only once in each cell, and the first byte of the output of the data shift circuit 10 A cell demultiplexing apparatus in an ATM system, characterized by being synchronized with a signal specifying a cell buffer.